Infineon TLE9262BQXV33 Manual Download Page 160

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Data Sheet

160

Rev. 1.00

2017-07-31

TLE9262BQXV33

Serial Peripheral Interface

Note:

The OC/OT bit might be set for V

POR,f

< VS < 5.5V (see also

Chapter 4.2

)

HS_OC_OT_STAT
High-Side Switch Overload Status (Address 101 0100

)

POR / Soft Reset Value: 0000 0000

;

Restart Value: 0000 xxxx

Reserved

HS4_OC_OT HS3_OC_OT HS2_OC_OT HS1_OC_OT

Field

Bits

Type

Description

Reserved

7:4

Reserved, always reads as 0

HS4_OC_OT

Overcurrent & Overtemperature Detection HS4

0B , No OC or OT
1B , OC or OT detected

HS3_OC_OT

Overcurrent & Overtemperature Detection HS3

0B , No OC or OT
1B , OC or OT detected

HS2_OC_OT

Overcurrent & Overtemperature Detection HS2

0B , No OC or OT
1B , OC or OT detected

HS1_OC_OT

Overcurrent & Overtemperature Detection HS1

0B , No OC or OT
1B , OC or OT detected

Summary of Contents for TLE9262BQXV33

Page 1: ...SO 11898 2 2016 SAE J2284 LIN transceiver LIN2 2A J2602 4 high side outputs 7 typ 2 HV GPIOs 3 HV wake inputs Integrated fail safe and supervision functions e g fail safe watchdog interrupt and reset...

Page 2: ...p Mode 29 5 1 5 SBC Restart Mode 30 5 1 6 SBC Fail Safe Mode 31 5 1 7 SBC Development Mode 32 5 2 Wake Features 34 5 2 1 Cyclic Sense 34 5 2 1 1 Configuration and Operation of Cyclic Sense 35 5 2 1 2...

Page 3: ...apable Mode 69 10 2 5 TXD Time out Feature 72 10 2 6 Bus Dominant Clamping 72 10 2 7 Undervoltage Detection 72 10 3 Electrical Characteristics 73 11 LIN Transceiver 80 11 1 Block Description 80 11 1 1...

Page 4: ...5 15 6 VCC1 Over Undervoltage and Undervoltage Prewarning 115 15 6 1 VCC1 Undervoltage and Undervoltage Prewarning 115 15 6 2 VCC1 Overvoltage 116 15 7 VCC1 Short Circuit and VCC3 Diagnostics 117 15 8...

Page 5: ...Data Sheet 5 Rev 1 00 2017 07 31 TLE9262BQXV33 19 Revision History 174...

Page 6: ...N and CAN bus network To support these applications the System Basis Chip SBC provides the main functions such as a 3 3V low dropout voltage regulator LDO for e g a microcontroller supply another 5V l...

Page 7: ...with configurable TXD timeout feature and LIN Flash Mode Fully compliant to Hardware Requirements for LIN CAN and FlexRay Interfaces in Automotive Applications Revision 1 3 2012 05 04 Four High Side O...

Page 8: ...CSN VCC1 CAN cell LIN cell Window Watchdog WK TXDLIN1 RXDLIN 1 LIN1 TXDCAN RXDCAN VCAN CANH CANL WK1 RESET GENERATOR INT GND WAKE REGISTER VS VS Fail Safe RO FO3 TEST FO2 FO1 VCC2 VCC2 High Side HS2...

Page 9: ...d 1 GND 2 n c 3 VCC3REF 4 VCC3B 5 VCC3SH 6 n c 7 n c 8 HS1 9 HS2 10 HS3 11 HS4 12 n c FO3 TEST 48 FO2 47 n c 46 n c 45 N U 44 GND 43 LIN1 42 n c 41 CANH 40 CANL 39 GND 38 VCAN 37 13 VSHS 14 VS 15 VS 1...

Page 10: ...upply is not needed 14 VS Supply Voltage Supply voltage for chip internal supply and voltage regulators Connected to Battery Voltage with external reverse protection Diode and Filter against EMC 15 VS...

Page 11: ...SAE J2602 2 43 GND Ground 44 N U Not Used Used for internal testing purpose Do not connect leave open 45 n c not connected internally not bonded 46 n c not connected internally not bonded 47 FO2 Fail...

Page 12: ...on the board an open bridge has to be foreseen to avoid external disturbances The bridge can be shorted by a 0 resistance if signal is needed 3 4 Hints for Alternate Pin Functions In case of alternat...

Page 13: ...ulator 3 VCC3REF VCC3REF max 0 3 28 V VCC3REF 40V for Load Dump max 400 ms P_4 1 5 Voltage Regulator 3 VCC3B VCC3B max 0 3 VS 10 V VCC3B 40V for Load Dump max 400 ms P_4 1 25 Voltage Regulator 3 VCC3S...

Page 14: ...ESD 12 2 2 kV HBM3 P_4 1 18 ESD Resistivity to GND CANH CANL LINx VESD 13 8 8 kV HBM4 3 P_4 1 19 ESD Resistivity to GND VESD 21 500 500 V CDM5 P_4 1 20 ESD Resistivity Pin 1 12 13 24 25 36 37 48 corne...

Page 15: ...n the SPI register BUS_STAT_1 and the transmitter will be disabled as long as the UV condition is present 5 25V VCAN 5 50V CAN transceiver still functional However the communication might fail due to...

Page 16: ...Test Condition Number Min Typ Max Junction to Soldering Point RthJSP 6 K W Exposed Pad P_4 3 1 Junction to Ambient RthJA 33 K W 2 2 According to Jedec JESD51 2 5 7 at natural convection on FR4 2s2p b...

Page 17: ...on VCC1 I_PEAK_TH 0 P_4 4 2 Stop Mode current consumption IStop_1 85 50 70 A 1 2 Tj 85 C VCC2 3 HSx OFF CAN LINx WKx not wake capable Watchdog OFF no load on VCC1 I_PEAK_TH 0 P_4 4 3 Stop Mode curren...

Page 18: ...l Stop Mode LIN Normal Mode VTXDLIN VCC1 no RL on LIN P_4 4 10 Current consumption per LIN module dominant state ILIN dom 1 0 1 5 mA 2 SBC Normal Stop Mode LIN Normal Mode VTXDLIN GND no RL on LIN P_4...

Page 19: ...Sleep Mode ISleep VCC2 25 25 35 A 1 3 SBC Sleep Mode VCC2 ON no load LIN CAN WK1 3 OFF P_4 4 19 Current consumption for VCC2 in SBC Sleep Mode ISleep VCC2 85 30 40 A 1 2 3 SBC Sleep Mode Tj 85 C VCC2...

Page 20: ...by typ 2 9mA to ensure optimum dynamic load behavior Same applies to VCC2 For VCC3 the current consumption will increase by typ 1 4mA See also Chapter 6 Chapter 7 Chapter 8 2 Not subject to production...

Page 21: ...to SBC Normal Mode after a delay time tRD1 SBC Fail Safe Mode A safe state mode after critical failures e g WD failure VCC1 undervoltage reset to bring the system into a safe state and to ensure a pr...

Page 22: ...See Chapter5 1 5 and 14 1 for detailed FOx behavior WD Config HSx OFF SBC Normal Mode VCC1 ON VCC2 config VCC3 config FOx act inact CAN 3 config LINx 3 config WD config HSx config SBC Sleep Mode VCC1...

Page 23: ...e in case of a watchdog failure 1 or 2 fails To set this configuration Config 2 4 the INT pin does not need an external pull up resistor In case VCC1 should not be switched OFF Config 1 3 the INT pin...

Page 24: ...after the 1st Config 2 or 2nd Config 4 watchdog trigger failure The first watchdog trigger failure in Config 4 will lead to SBC Restart Mode A VCC1 overvoltage detection will lead to SBC Fail Safe Mo...

Page 25: ...VPOR f Table 6 Device Behavior in Case of VCC1 Overvoltage Detection Config INT Pin CFGP CFG Bit VCC1_O V_RST Event VCC1_ OV FOx Activation SBC Mode Entry 1 4 any value x 0 1 x VCC1 OV 1 no FOx activa...

Page 26: ...l cause a watchdog failure and the device will enter SBC Restart Mode Wake events are ignored during SBC Init Mode and will therefore be lost Note Any SPI command will bring the SBC to SBC Normal Mode...

Page 27: ...is configurable OFF coming from SBC Init Mode OFF or wake capable coming from SBC Restart Mode see also Chapter 5 1 5 HS Outputs can be switched ON or OFF default OFF or can be controlled by PWM HS Ou...

Page 28: ...igured in SBC Normal Mode VCC3 is fixed as configured in SBC Normal Mode CAN mode is fixed as configured in SBC Normal Mode LIN mode is fixed as configured in SBC Normal Mode WK pins are fixed as conf...

Page 29: ...BC Normal Mode Cyclic sense is fixed as configured in SBC Normal Mode Cyclic wake is not available Watchdog is OFF FOx outputs are fixed i e the state from SBC Normal Mode is maintained As VCC1 is OFF...

Page 30: ...behavior of the blocks is listed below All FOx outputs are activated in case of a 1st watchdog trigger failure if Config1 or Config2 is selected or in case of VCC1 overvoltage detection if VCC1_OV_RS...

Page 31: ...WK_STAT_1 and all output drivers and all voltage regulators are switched off When WK1 and WK2 are configured for the alternate measurement function WK_MEAS 1 then WK1 and WK2 will stay configured for...

Page 32: ...T MODE and entering SBC Normal Mode from SBC Init Mode is ON instead of OFF The SBC Development Mode is reached automatically if the FO3 TEST pin is set and kept LOW during SBC Init Mode The voltage l...

Page 33: ...QXV33 System Features Note Theabsolute maximum ratings ofthe pin FO3 TEST must be observed To increase the robustness of this pin during debugging or programming a series resistor between FO3 TEST and...

Page 34: ...and the application In the cyclic sense configuration one or more high side drivers are switched on periodically controlled by TIMER1_CTRL and TIMER2_CTRL The respective high side drivers supply exter...

Page 35: ...Configure the initial level Mapping of a Timer to the respective HSx outputs Configuring the respective filter timing and WK pins Configuring the timer period and on time Figure 6 Cyclic Sense Configu...

Page 36: ...leep Mode or an interrupt during SBC Normal or SBC Stop Mode A filter time of 16 s is implemented to avoid a parasitic wake up due to transients or EMC disturbances The filter time tFWK1 is triggered...

Page 37: ...entical except that in Stop Mode INT will be triggered to signal a change of WK input levels and in SBC Sleep Mode VCC1 will power up instead Figure 7 Wake Input Timing Figure 8 Cyclic Sense Example i...

Page 38: ...essary to activate the cyclic sense in SBC Normal Mode before going to the low power mode A wake event due to cyclic sense will set the respective bit WK1_WU WK2_WU or WK3_WU In Stop Mode the wake eve...

Page 39: ...or Timer2 Also an on time any value must be selected to start the cyclic wake even if the value is ignored Figure 10 Cyclic Wake Configuration and Sequence As in cyclic sense the cyclic wake function...

Page 40: ...erefore the timers can be mapped to the dedicated HS switches by SPI via HS_CTRL1 2 Following periods and on times can be selected via the register TIMER1_CTRL and TIMER2_CTRL respectively Period 10ms...

Page 41: ...tion VRT1 2 3 4 VPW f Please refer to Chapter 15 6 and Chapter 15 7 for more information Short circuit detection and switch off with undervoltage fail threshold device enters SBC Fail Safe Mode 470nF...

Page 42: ...power mode regulator will be also activated to support an optimum dynamic load behavior The current consumption will then increase by typ 2 9mA If the load current on VCC1 falls below the selected thr...

Page 43: ...Ipeak P_6 3 16 Output Voltage including line and Load regulation VCC1 3 3V VCC1 out72 3 29 3 3 3 47 V SBC Stop Mode 10 A IVCC1 1mA P_6 3 21 Output Drop VCC1 d1 500 mV IVCC1 50mA VS 3V P_6 3 3 Output D...

Page 44: ...esults of VCC1 pass device during low drop operation for ICC1 100mA 1 In SBC Stop Mode the specified output voltage tolerance applies when IVCC1 has exceeded the selected active peak threshold IVCC1 I...

Page 45: ...Data Sheet 45 Rev 1 00 2017 07 31 TLE9262BQXV33 Voltage Regulator 1 Figure 13 Characterization results of on resistance range of VCC1 pass device during low drop operation for ICC1 150mA...

Page 46: ...apter 15 8 for more information Can be active in SBC Normal SBC Stop and SBC Sleep Mode not SBC Fail Safe Mode VCC2 switch off after entering SBC Restart Mode Switch off is latched LDO must be enabled...

Page 47: ...current on VCC2 exceeds IVCC2 IVCC2 Ipeak r then the high power mode regulator will also be enabled to support an optimum dynamic load behavior The current consumption will then increase by typ 2 9mA...

Page 48: ...ation SBC Normal Mode VCC2 out3 4 9 5 0 5 1 V 1 SBC Normal Mode 10 A IVCC2 40mA P_7 3 2 Output Voltage including line and Load regulation SBC Normal Mode VCC2 out4 4 97 5 07 V 2 SBC Normal Mode 10 A I...

Page 49: ...Data Sheet 49 Rev 1 00 2017 07 31 TLE9262BQXV33 Voltage Regulator 2 Figure 15 Typical on resistance of VCC2 pass device during low drop operation for ICC2 30mA...

Page 50: ...Data Sheet 50 Rev 1 00 2017 07 31 TLE9262BQXV33 Voltage Regulator 2 Figure 16 On resistance range of VCC2 pass device during low drop operation for ICC2 50mA...

Page 51: ...10 kHz to achieve the voltage regulator control loop stability based on the safe phase margin bode diagram Overcurrent limitation with external shunt in stand alone configuration Adjustable load curre...

Page 52: ...because a low power mode regulator with a lower accuracy will be active for small loads If the base current on VCC3 exceeds IVCC3base IVCC3base Ipeak r then the high power mode regulator is enabled a...

Page 53: ...e switched ON or OFF but the configuration cannot be changed anymore However the SPI_FAIL is not set while trying to change the configuration An overcurrent limitation function is realized with the ex...

Page 54: ..._LS for the first time while VCC3_ON has no function i e keep VCC3_ON 0 Trying to change the VCC3 configuration after VCC3_LS has been set will result in the SPI_FAIL bit being set and keeping the VCC...

Page 55: ...he PCB layout and properties of the application to prevent thermal damage e g via the shunt current limitation in stand alone configuration or by selecting the proper ICC1 ICC3 ratio in load sharing c...

Page 56: ...hunt resistor determines the load sharing ratio between VCC1 and VCC3 The ratio can be calculated as following 8 2 Example A shunt resistor with 470m and a load current of 100mA out of VCC1 would resu...

Page 57: ...e 20 mA Figure 21 P_8 6 7 Current decrease regulation reaction time trIdec 5 s 4 VCC3 0 V to 3 3V ICC3base 20 mA Figure 21 P_8 6 8 Leakage current of VCC3base when VCC3 disabled IVCC3base_lk 5 A VCC3b...

Page 58: ...SBC Normal Mode LS ratio for a 470 m shunt resistor and total load current of 300mA P_8 6 16 Load Sharing Ratio ICC1 ICC3 RatioLS_2 VCC3 1 0 67 1 0 95 1 1 23 4 5 6 0V VS 28V SBC Normal Mode LS ratio...

Page 59: ...r is turned on off To prevent an overvoltage condition at no load due to this increased leakage an internal clamping structure will automatically turn on at typ 200mV above the upper limit of the prog...

Page 60: ...QXV33 External Voltage Regulator 3 Timing diagram for regulator reaction time current increase regulation reaction time and current decrease regulation reaction time Figure 21 Regulator Reaction Time...

Page 61: ...vs the total load current Figure 23 Load Sharing Behavior of ICC1 vs the total load current 0 0 2 0 4 0 6 0 8 1 0 1 2 1 4 0 0 05 0 10 0 15 0 20 0 25 0 30 0 35 Load Sharing Ratio Icc1 vs Icc3 Total Cu...

Page 62: ...hes can be used for control of LEDs as supply for the wake inputs and for other loads The High Side outputs can be controlled either directly via SPI by HS_CTRL1 HS_CTRL2 by the integrated timers or b...

Page 63: ...onfiguration has to be set to ON 001 or be programmed to a timer function It is recommended to clear the overcurrent bit before activation the High Side switch as the bits are not cleared automaticall...

Page 64: ...generator to respective HS switch es in HSx_CTRL The PWM generation will start right after the HSx is assigned to the PWM generator HS_CTRL1 HS_CTRL2 Assignment options of HS1 HS4 Timer 1 Timer 2 PWM...

Page 65: ...subject to production test specified by design P_9 3 3 Output Slew Rate falling SRfall HS 2 5 0 8 V s 1 80 to 20 VSHS 6 to 18V RL 220 P_9 3 4 Switch on time HSx tON HS 3 30 s CSN HIGH to 0 8 VSHS RL...

Page 66: ...ce current consumption This supports networks with partially powered down nodes To support software diagnostic functions a CAN Receive only Mode is implemented It is designed to provide excellent pass...

Page 67: ...pport CAN FD but also the CAN controller In case the CAN controller is not able to support CAN FD then the respective CAN node must at least tolerate CAN FD communication This CAN SBC Normal Mode SBC...

Page 68: ...nput of the SBC The bus driver switches the CANH L output stages to transfer this input signal to the CAN bus lines Enabling sequence The CAN transceiver requires an enabling time tCAN EN before a mes...

Page 69: ...are connected to GND via the input resistors A wake up signal on the bus results in a change of behavior of the SBC as described in Table 16 The pins CANH L are terminated to typ 2 5V through the inpu...

Page 70: ...Stop SBC Sleep or SBC Fail Safe Mode to ensure wake up capability Note It is not necessary to clear the CAN wake up bit CAN_WU to become wake capable again It is sufficient to toggle the CAN mode Note...

Page 71: ...to HIGH before Wake Up in SBC Sleep Mode Wake up is possible via a CAN message filter time t tWake1 The wake up automatically transfers the SBC into the SBC Restart Mode and from there to Normal Mode...

Page 72: ...ly switched back to CAN Normal Mode The transceiver configuration stays unchanged 10 2 6 Bus Dominant Clamping If the HS CAN bus signal is dominant for a time t tBUS_CAN_TO in CAN Normal and Receive O...

Page 73: ...Common Mode Range CMR 12 12 V 1 P_10 3 4 CANH CANL Input Resistance Rin 20 40 50 k CAN Normal Wake capable Mode Recessive state 2 V VCANL H 7 V P_10 3 6 Differential Input Resistance Rdiff 40 80 100 k...

Page 74: ...ANH CANL Dominant Output Voltage Difference Vdiff VCANH VCANL Vdiff_d_N 1 5 3 0 V CAN Normal Mode VTXD 0 V VCAN 5 V 50 RL 65 P_10 3 16 CANH CANL Dominant Output Voltage Difference Vdiff VCANH VCANL Vd...

Page 75: ...CC1 0 5 VCC1 V 1 P_10 3 25 TXD Pull up Resistance RTXD 20 40 80 k P_10 3 26 CAN Transceiver Enabling Time tCAN EN 8 13 18 s 4 CSN HIGH to first valid transmitted TXD dominant P_10 3 27 Dynamic CAN Tra...

Page 76: ...essive to RXD HIGH td H R 100 ns CAN Normal Mode CL 100pF 50 RL 60 VCAN 5 V CRXD 15 pF P_10 3 35 Received Recessive Bit Width CAN FD up to 2Mbps tbit RXD 400 550 ns CAN Normal Mode CL 100pF RL 60 VCAN...

Page 77: ...definitionin according to Figure 31 P_10 3 53 Receiver Timing Symmetry CAN FD up to 5 Mbps tRec 45 15 ns CAN Normal Mode CL 100pF RL 60 VCAN 5 V CRXD 15 pF tbit TXD 200 ns Parameterdefinitionin accord...

Page 78: ...is simulated by a square signal 50 duty cycle with a frequency of up to 1 MHz 2 MBit s 3 Rtest between supply VS VCAN and 0V GND 4 Not subject to production test tolerance defined by internal oscillat...

Page 79: ...07 31 TLE9262BQXV33 High Speed CAN Transceiver Figure 31 From ISO 11898 2 tloop tbit TXD tbit Bus tbit RXD definitions 500mV TXDCAN 70 30 RXDCAN Vdiff CANH CANL 30 70 900mV 5x tBit TXD tBit TXD tLoop_...

Page 80: ...LIN 2 2a is a super set of the previous LIN specifications like LIN 2 0 or LIN 1 3 The integrated LIN transceivers are according to the LIN 2 2 standard The device is compliant to the physical layer...

Page 81: ...connected between the LIN bus and the power supply VSHS The different transceiver modes can be controlled via the SPI LIN1 bits Figure 33 shows the possible transceiver mode transitions when changing...

Page 82: ...xt dominant bit will be transmitted on the bus Figure 34 shows different scenarios and explanations for LIN enabling Figure 34 LIN Transceiver Enabling Sequence Reduced Electromagnetic Emission To red...

Page 83: ...to LIN Wake Capable Mode again Rearming is done automatically when the SBC is changed to SBC Stop SBC Sleep or SBC Fail Safe Mode to ensure wake up capability Wake Up in SBC Stop and SBC Normal Mode I...

Page 84: ...Function 11 2 6 Bus Dominant Clamping If the LIN bus signal is dominant for a time t tBUS_LIN_TO in LIN Normal and Receive Only Mode then a bus dominant clamping is detected and the SPI bit LIN1_FAIL...

Page 85: ...l Slope Mode The selection of LIN Low Slope Mode is done by an SPI bit LIN_LSM and will become effective as soon as CSN goes HIGH Only the LIN Slope is changed The selection is accessible in SBC Norma...

Page 86: ...VCC1 0 5 VCC1 V 1 P_11 3 4 LOW Level Input Voltage VTXD L 0 3 VCC1 V Dominant State P_11 3 5 TXD Pull up Resistance RTXD 20 40 80 k VTXD 0 V P_11 3 6 LIN Bus Receiver LIN Pin Receiver Threshold Volta...

Page 87: ...k Normal Mode LIN 2 2 Param 26 P_11 3 22 LIN Input Capacitance CBUS 20 25 pF 1 P_11 3 23 Receiver propagation delay bus dominant to RXD LOW td L R 1 6 s VCC 3 3 V CRXD 20 pF LIN 2 2 Param 31 P_11 3 24...

Page 88: ...VSHS VSHS 7 0 18 V tbit 96 s D3 tbus_rec min 2 tbit LIN 2 2 Param 29 P_11 3 33 Duty Cycle D4 for worst case at 10 4 kbit s SAE J2602 Low Slope D4 0 590 3 THRec min 0 389 VSHS THDom min 0 251 VSHS VSHS...

Page 89: ...Data Sheet 89 Rev 1 00 2017 07 31 TLE9262BQXV33 LIN Transceiver Figure 36 Simplified Test Circuit for Dynamic Characteristics GND LIN 100 nF VSHS CLIN TxD WK RLIN RxD CRxD...

Page 90: ...holds of receiving node 1 Thresholds of receiving node 2 THRec max THDom max THRec min THDom min tBus _dom min tBus_rec max td L R 1 td H R 1 td H r 2 t L R 2 VSUP Transceiver supply of transmitting n...

Page 91: ...voltage sensing via WK1 and WK2 Wake up capability for power saving modes Edge sensitive wake feature LOW to HIGH and HIGH to LOW Pull up and Pull down current sources configurable via SPI Selectable...

Page 92: ...configuration The filter time tFWK1 tFWK2 is triggered by a level change crossing the switching threshold and a wake signal is recognized if the input level will not cross again the threshold during t...

Page 93: ...tomatic Switching Configuration Config A and B are intended for static sense with two different filter times Table 20 Pull Up Pull Down Resistor WKx_PUPD_ 1 WKx_PUPD_ 0 Current Sources Note 0 0 no cur...

Page 94: ...re intended for cyclic sense configuration With the filter settings the respective timer needs to be assigned to one or more HS output which supplies an external circuit connected to the WKx pin e g H...

Page 95: ...is set to 1 then the measurement function is enabled and switch S1 is closed in SBC Normal Mode S1 is open in all other SBC modes If this function the pull up and down currents of WK1 and WK2 are disa...

Page 96: ...erial resistor RS with RS V IPD PU RS hysteresis included P_12 3 1 Threshold hysteresis VWKNth hys 0 1 0 7 V without external serial resistor RS with RS V IPD PU RS P_12 3 2 WK pin Pull up Current IPU...

Page 97: ...3 Wake and Voltage Monitoring Inputs Figure 41 Typical Drop Voltage Characteristics of S1 between WK1 WK2 800 900 1000 1100 AGE DROP OF SWITCH S1 mV VS 13 5V 250 A 500 A 500 600 700 50 0 50 100 150 V...

Page 98: ...L 1 in addition to the wake up events all signalled failures stored in the other status registers cause an interrupt the register WK_LVL_STAT is not generating interrupts Note The errors which will ca...

Page 99: ...t Signalization Behavior Interrupt_Behavior vsd INT WK1 WK2 tINT tINTD Update of WK_STAT register SPI Read Clear Update of WK_STAT register WK_STAT contents Scenario 1 WK1 no WK WK2 no WK optional SPI...

Page 100: ...T INT High Output Voltage VINT H 0 8 VCC1 V 1 IINT 1 mA INT OFF 1 Output Voltage Value also determines device configuration during SBC Init Mode P_13 2 1 INT Low Output Voltage VINT L 0 2 VCC1 V 1 IIN...

Page 101: ...ignalled in the SPI bit FAILURE of the register DEV_STAT For testing purposes only the Fail Outputs can also be activated via SPI by setting the bit FO_ON This bit is independent of the FO failure bit...

Page 102: ...l Purpose I O block diagram for FO2 and FO3 TEST The pins are by default configured as FO pins The configuration is done via the SPI register GPIO_CTRL The alternate function can be Wake Inputs The de...

Page 103: ...fter leaving SBC Restart Mode the previously configured function will be resumed SPI register is not modified if configured as FO and activated due to a failure FO will stay activated during SBC Resta...

Page 104: ...2 5 5 10 k VTEST 0V SBC Init Mode P_14 2 5 TEST Input Filter Time tTEST 50 64 80 s 3 P_14 2 6 FO3 pulsed light frequency fFO3PL 80 100 120 Hz 3 P_14 2 7 FO3 pulsed light duty cycle dFO3PL 16 20 24 3...

Page 105: ...al capacitance on this pin must be limited to less than 10nF to ensure proper detection of SBC Development Mode and SBC User Mode operation 3 Not subject to production test tolerance defined by intern...

Page 106: ...present plus a reset delay time tRD1 When connecting the SBC to battery voltage the reset signal remains LOW initially When the output voltage Vcc1 has reached the reset default threshold VRT1 r the r...

Page 107: ...es see SPI Chapter 16 5 and Chapter 16 6 Two different soft reset configurations are possible via the SPI bit SOFT_ RESET_RO The reset output RO is triggered when the soft reset is executed default se...

Page 108: ...en window tLW 200ms allows the microcontroller to run its initialization sequences and then to trigger the watchdog via SPI The watchdog timer period can be selected via the watchdog timing bit field...

Page 109: ...successfully disabling it in SBC Sleep Mode or in SBC Fail Safe Mode except for a watchdog failure 15 2 1 Time Out Watchdog The time out watchdog is an easier and less secure watchdog than a window w...

Page 110: ...area of tWD x 0 72 safe trigger area tWD x 1 20 The typical closed window is defined to a width of 60 of the selected window watchdog timer period Taking the tolerances of the internal oscillator into...

Page 111: ...ther setting the bit CHECKSUM to 0 or 1 If the check sum is wrong then the SPI command is ignored i e the watchdog is not triggered or the settings are not changed and the bit SPI_FAIL is set The chec...

Page 112: ...g in SBC Stop Mode or by switching back to SBC Normal Mode via SPI command In both cases the watchdog will start with a long open window and the bits WD_STM_EN_1 and WD_STM_ EN_0 are cleared After the...

Page 113: ...ult value after POR The bit can only be changed in SBC Normal Mode and needs to be programmed before starting the watchdog disable sequence A wake on CAN and LINx will generate an interrupt and the RX...

Page 114: ...sed once VCC1 has crossed VRT1 r and after tRD1 has elapsed In case VS VPOR f an device internal reset will be generated and the SBC is switched OFF and will restart in INIT mode at the next VS rising...

Page 115: ...o other error bits are set The bit can be cleared once the condition is not present anymore VCC1 VCC2 WKx and CAN are not affected by VSHS undervoltage 15 5 Overvoltage VSHS If the supply voltage VSHS...

Page 116: ...e VCC1_UV bit once it was set and detected 15 6 2 VCC1 Overvoltage For fail safe reasons a configurable VCC1 overvoltage detection feature is implemented for SBC Init and Normal Mode In case the VCC1...

Page 117: ..._OFF 0 or when in SBC Stop Mode if VCC3_LS_ STP_ON 0 All other diagnostic features are disabled because they are provided via VCC1 Stand alone configuration The external PNP is disabled when VCC3 VS U...

Page 118: ...esent anymore VCC3 has to be configured again by SPI It is recommended to clear the VCC3_OT bit before enabling the regulator again VCC3 in load sharing configuration in case of overtemperature at VCC...

Page 119: ...3 SBC Thermal Shutdown As a highest level of thermal protection a temperature shutdown of the SBC is implemented if the main supply VCC1 reaches the thermal shutdown temperature threshold TjTSD2 Once...

Page 120: ...15 V default setting VCC1 falling P_15 10 37 Reset Threshold Voltage RT1 r 3 3V option VRT1 r 3 0 3 1 3 2 V default setting VCC1 rising P_15 10 38 Reset Threshold Voltage RT2 f 3 3V option VRT2 f 2 5...

Page 121: ...2 5 ms 1 2 P_15 10 18 VCC2 Monitoring VCC2 Undervoltage Threshold Voltage falling VCC2 UV f 4 5 4 75 V VCC2 falling P_15 10 19 VCC2 Undervoltage Threshold Voltage rising VCC2 UV r 4 6 4 9 V VCC2 risin...

Page 122: ...holdforVCC3 and VCC1 SC detection hysteresis included P_25 10 46 VSHS Overvoltage Detection Threshold VSHS OVD 20 22 V Supply OV supervision for HSx hysteresis included P_15 10 28 VSHS Overvoltage Det...

Page 123: ...Vrtx threshold 2 Not subject to production test tolerance defined by internal oscillator tolerance 3 This time applies for all failure entries except a device thermal shutdown TSD2 has a typ 1s waitin...

Page 124: ...thereby releasing the SDO bus for other use The state of SDI is shifted into the input register with every falling edge on CLK The state of SDO is shifted out of the output register after every risin...

Page 125: ...the M_S_CTRL register The other modifications will be ignored SBC Sleep Mode attempt to go to Sleep Mode when all bits in the BUS_CTRL_1 and WK_CTRL_2 registers are cleared In this case the SPI_FAIL b...

Page 126: ...this case RO is LOW and SPI frames are being sent at the same time The ERR flag will be set when the RO pin is triggered during SBC Restart and SPI frames are being sent to the SBC at the same time T...

Page 127: ...transmitted in a compressed way with each SPI response on SDO in the so called Status Information Field register see also Figure 55 The purpose of this register is to quickly signal the information t...

Page 128: ...e 55 SPI Operation Mode 0 1 2 3 4 5 7 6 8 9 10 11 12 13 15 14 Data Bits DI Address Bits x x x x x x x x R W 0 1 2 3 4 5 7 6 8 9 10 11 12 13 15 14 Data Bits DO Status Information Field x x x x x x x x...

Page 129: ...nging to a different SBC Mode certain configurations bits will be cleared automatically or modified The SBC Mode bits are updated to the actual status e g when returning to Normal Mode When changing t...

Page 130: ...L rw 0 0 0 1 0 0 1 WK_FLT_CTRL rw 0 0 0 1 1 0 0 TIMER1_CTRL rw 0 0 1 0 0 0 0 SW_SD_CTRL rw 0 0 1 0 1 0 0 HS_CTRL_1 rw 0 0 1 0 1 0 1 HS_CTRL_2 rw 0 0 1 1 0 0 0 PWM1_CTRL rw 0 0 1 1 0 0 1 PWM2_CTRL rw 1...

Page 131: ...10101 GPIO_CTRL FO_DC_1 FO_DC_0 GPIO2_2 GPIO2_1 GPIO2_0 GPIO1_2 GPIO1_1 GPIO1_0 read write 0010111 PWM1_CTRL PWM1_DC_7 PWM1_DC_6 PWM1_DC_5 PWM1_DC_4 PWM1_DC_3 PWM1_DC_2 PWM1_DC_1 PWM1_DC_0 read write...

Page 132: ...here are three different bit types r READ read only bits or reserved bits rw READ WRITE readable and writable bits rwh READ WRITE Hardware readable writable bits which can also be modified by the SBC...

Page 133: ...rwh rwh rwh rwh rwh rwh rw rw Field Bits Type Description MODE 7 6 rwh SBC Mode Control 00B SBC Normal Mode 01B SBC Sleep Mode 10B SBC Stop Mode 11B SBC Reset Soft Reset is executed configuration of R...

Page 134: ...No RO triggering during a Soft Reset FO_ON 5 rwh Failure Output Activation FO1 3 0B FOx not activated by software FO can be activated by defined failures see Chapter 14 1B FOx activated by software vi...

Page 135: ...outputs will be disabled See also Chapter 14 for FOx activation and deactivation 2 After triggering a SBC Soft Reset the bits VCC3_V_CFG and VCC3_LS are not reset if they were set before i e it stays...

Page 136: ...ing Check Sum Bit The sum of bits 7 0 needs to have even parity see Chapter 15 2 3 0B Counts as 0 for checksum calculation 1B Counts as 1 for checksum calculation WD_STM_ EN_0 6 rwh Watchdog Deactivat...

Page 137: ...that the device can be woken again BUS_CTRL_1 Bus Control Address 000 0100B POR Soft Reset Value 0010 0000B Restart Value xxxy y0yyB 7 6 5 4 3 2 1 0 LIN_FLASH LIN_LSM LIN_TXD_TO LIN1_1 LIN1_0 Reserve...

Page 138: ...ailure TSD2 WD Failure then the wake registers BUS_CTRL_1 and WK_CTRL_2 are reset to following values wake sources xxx0 1001 and x0x0 0111 in order to ensure that the device can be woken again BUS_CTR...

Page 139: ...Field Bits Type Description TIMER2_WK _EN 7 rw Timer2 Wake Source Control for cyclic wake 0B Timer2 wake disabled 1B Timer2 is enabled as a wake source TIMER1_WK _EN 6 rw Timer1 Wake Source Control fo...

Page 140: ...rnal Wake Source Control Address 000 0111B POR Soft Reset Value 0000 0111B Restart Value x0x0 0xxxB 7 6 5 4 3 2 1 0 INT_GLOBAL Reserved WK_MEAS Reserved Reserved WK3_EN WK2_EN WK1_EN w r rw r rw r r r...

Page 141: ...3_PUPD 5 4 rw WK3 Pull Up Pull Down Configuration 00B No pull up pull down selected 01B Pull down resistor selected 10B Pull up resistor selected 11B Automatic switching to pull up or pull down WK2_PU...

Page 142: ...n time a filter time of 16 s cyclic sensing is selected Timer1 11B Configuration D Filtering at the end of the on time a filter time of 16 s cyclic sensing is selected Timer2 WK2_FLT 3 2 rw WK2 Filter...

Page 143: ...ontrol and Selection Address 000 1100B POR Soft Reset Value 0000 0000B Restart Value 0000 0000B 7 6 5 4 3 2 1 0 Reserved TIMER1_ ON_2 TIMER1_ ON_1 TIMER1_ ON_0 Reserved TIMER1_ PER_2 TIMER1_ PER_1 TIM...

Page 144: ...Restart Value 0000 0000B 7 6 5 4 3 2 1 0 Reserved TIMER2_ ON_2 TIMER2_ ON_1 TIMER2_ ON_0 Reserved TIMER2_ PER_2 TIMER2_ PER_1 TIMER2_ PER_0 r r rwh rwh rwh r rwh rwh rwh Field Bits Type Description Re...

Page 145: ...7 r Reserved always reads as 0 HS_OV_SD_ EN 6 rw Shutdown Disabling of HS1 4 in case of VSHS OV 0B shutdown enabled in case of VSHS OV 1B shutdown disabled in case of VSHS OV HS_UV_SD_ EN 5 rw Shutdo...

Page 146: ...0 Reserved HS1_2 HS1_1 HS1_0 r rw rwh rwh rwh r rwh rwh rwh Field Bits Type Description Reserved 7 r Reserved always reads as 0 HS2 6 4 rwh HS2 Configuration 000B Off 001B On 010B Controlled by Timer1...

Page 147: ..._0 Reserved HS3_2 HS3_1 HS3_0 r r rwh rwh rwh r rwh rwh rwh Field Bits Type Description Reserved 7 r Reserved always reads as 0 HS4 6 4 rwh HS4 Configuration 000B Off 001B On 010B Controlled by Timer1...

Page 148: ...GPIO2_1 GPIO2_0 GPIO1_2 GPIO1_1 GPIO1_0 r rw rw rw rw rw rw rw rw Field Bits Type Description FO_DC 7 6 rw Duty Cycle Configuration of FO3 if selected 00B 20 01B 10 10B 5 11B 2 5 GPIO2 5 3 rw GPIO2 C...

Page 149: ...Value xxxx xxxxB 7 6 5 4 3 2 1 0 PWM1_DC_7 PWM1_DC_6 PWM1_DC_5 PWM1_DC_4 PWM1_DC_3 PWM1_DC_2 PWM1_DC_1 PWM1_DC_0 r rw rw rw rw rw rw rw rw Field Bits Type Description PWM1_DC 7 0 rw PWM1 Duty Cycle b...

Page 150: ...ddress 001 1100B POR Soft Reset Value 0000 0000B Restart Value 0000 0x0xB 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved PWM2_FREQ Reserved PWM1_FREQ r r r r r r rw r rw Field Bits Type...

Page 151: ...o the data byte and correspond to the bits D0 D7 and to the SPI bits 8 15 see also figure There are two different bit types r READ read only bits or reserved bits rc READ CLEAR readable and clearable...

Page 152: ...Description Reserved 7 r Reserved always reads as 0 VS_UV 6 rc VS Undervoltage Detection VS UV 0B No VS undervoltage detected 1B VS undervoltage detected Reserved 5 r Reserved always reads as 0 VCC3_...

Page 153: ...Value xxxx xx0xB 7 6 5 4 3 2 1 0 POR VSHS_UV VSHS_OV VCC2_OT VCC2_UV VCC1_SC VCC1_UV_FS VCC1_UV r rc rc rc rc rc rc rc rc Field Bits Type Description POR 7 rc Power On Reset Detection 0B No POR 1B POR...

Page 154: ...Reset Value 0000 0000B Restart Value 0000 0xxxB 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved TSD2 TSD1 TPW r r r r r r rc rc rc Field Bits Type Description Reserved 7 3 r Reserved alw...

Page 155: ...only by SPI command 4 In case of Config 2 4 the WD_Fail counter is frozen in case of WD trigger failure until a successful WD trigger 5 If CFG 0 then a 1st watchdog failure will not trigger the FO ou...

Page 156: ...rc rc rc Field Bits Type Description Reserved 7 r Reserved always reads as 0 LIN1_FAIL 6 5 rc LIN1 Failure Status 00B No error 01B LIN1 TSD 10B LIN1_TXD_DOM TXD dominant time out for more than 20ms 11...

Page 157: ...ved LIN1_WU CAN_WU TIMER_WU Reserved WK3_WU WK2_WU WK1_WU r r rc rc rc r rc rc rc Field Bits Type Description Reserved 7 r Reserved always reads as 0 LIN1_WU 6 rc Wake up via LIN1 Bus 0B No Wake up 1B...

Page 158: ...0 0000B Restart Value 00xx 0000B 7 6 5 4 3 2 1 0 Reserved Reserved GPIO2_WU GPIO1_WU Reserved Reserved Reserved Reserved r r r rc rc r r r r Field Bits Type Description Reserved 7 6 r Reserved always...

Page 159: ...2 1 0 SBC_DEV _LVL CFGP GPIO2_LVL GPIO1_LVL Reserved WK3_LVL WK2_LVL WK1_LVL r r r r r r r r r Field Bits Type Description SBC_DEV _LVL 7 r Status of SBC Operating Mode at FO3 TEST Pin 0B User Mode a...

Page 160: ...Reserved HS4_OC_OT HS3_OC_OT HS2_OC_OT HS1_OC_OT r r r r r rc rc rc rc Field Bits Type Description Reserved 7 4 r Reserved always reads as 0 HS4_OC_OT 3 rc Overcurrent Overtemperature Detection HS4 0...

Page 161: ...3 2 1 0 Reserved Reserved Reserved Reserved HS4_OL HS3_OL HS2_OL HS1_OL r r r r r rc rc rc rc Field Bits Type Description Reserved 7 4 r Reserved always reads as 0 HS4_OL 3 rc Open Load Detection HS4...

Page 162: ...set Value 0011 yyyy B Restart Value 0011 yyyyB 7 6 5 4 3 2 1 0 FAM_3 FAM_2 FAM_1 FAM_0 PROD_3 PROD_2 PROD_1 PROD_0 r r r r r r r r r Field Bits Type Description FAM 7 4 r SBC Family Identifier bit4 LS...

Page 163: ...7 x VCC1 P_16 7 5 Pull down Resistance at pin SDI and CLK RICLK SDI 20 40 80 k VSDI CLK 0 2 x VCC1 P_16 7 6 Input Capacitance at pin CSN SDI or CLK CI 10 pF 1 P_16 7 7 Logic Output SDO H output Voltag...

Page 164: ...CL 100 pF P_16 7 25 SDO Fall Time tfSDO 30 80 ns CL 100 pF P_16 7 26 SDO Enable Time tENSDO 50 ns low impedance P_16 7 27 SDO Disable Time tDISSDO 50 ns high impedance P_16 7 28 SDO Valid Time tVASDO...

Page 165: ...N CLK SDO SDI FOx VCC1 C4 VCC1 C5 WK1 HS1 VS Reset INT RO VCAN GND Q1 VCC GND IC1 VS LOGIC State Machine Application _information _TLE9262 vsd VS T1 CANH CANL CAN cell VBAT VBAT VS TLE9262 VS VCC3REF...

Page 166: ...ery close to VCAN pin for optimum EMC behavior C7 33nF As required by application mandatory protection for off board connections C8 33nF As required by application mandatory protection for off board c...

Page 167: ...pincurrentlimitation e g for ISOpulses foralternatemeasurement function see also Simplified Application Diagram with the Alternate Measurement Function R16 depending on application and microcontroller...

Page 168: ...output to the microcontroller supervision function The maximum current into WK1 must be 500uA The minimum current into WK1 should be 5uA to ensure proper operation C1 e g 470uF C2 VSS VDD CSN CLK SDI...

Page 169: ...17 07 31 TLE9262BQXV33 Application Information Figure 61 Hint for Increasing the Robustness of pin FO3 TEST during Debugging or Programming FO3 TEST REXT Connector Jumper 5V_int RTEST SBC Init Mode Fa...

Page 170: ...formed Tested by external test house UL LLC Table 32 ESD Gun Test Performed Test Result Unit Remarks ESD at pin CANH CANL LIN VS WK1 3 HSx VCC2 VCC3 versus GND 6 kV 1 2 positive pulse 1 ESD Test Gun T...

Page 171: ...tion 17 3 Thermal Behavior of Package Below figure shows the thermal resistance Rth_JA of the device vs the cooling area on the bottom of the PCB for Ta 85 C Every line reflects a different PCB and th...

Page 172: ...rmal via array under the exposed pad contacting the first inner copper layer and 300mm2 cooling area on the bottom layer 70 m PCB top view PCB bottom view Detail SolderArea 1 5 mm 1 5 mm 70 m modelled...

Page 173: ...wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product Green products are RoHS Compliant i e Pb fre...

Page 174: ...Data Sheet 174 Rev 1 00 2017 07 31 TLE9262BQXV33 Revision History 19 Revision History Revision Date Changes Rev 1 00 2017 07 31 Initial Release...

Page 175: ...luding without limitation warranties of non infringement of intellectual property rights of any third party In addition any information given in this document is subject to customer s compliance with...

Page 176: ...ETC T MAX1856EUB T STNRG011TR IRPS5401MXI03TRP S6AE102A0DGN1B200 MMPF0100FDAEP MCZ33903DS5EK S6AE101A0DGNAB200 NCP6924CFCHT1G MAX17117ETJ L9916 L9915 CB MCZ33905DS3EK MMPF0100FCANES MMPF0100FBANES WM8...

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