Data Sheet
114
Rev. 1.00
2017-07-31
TLE9262BQXV33
Supervision Functions
15.3
VS Power On Reset
At power up of the device, the VS Power on Reset is detected when VS >
V
POR,r
and the SPI bit
POR
is set to
indicate that all SPI registers are set to POR default settings. VCC1 is starting up and the reset output will be
kept LOW and will only be released once VCC1 has crossed
V
RT1,r
and after
t
RD1
has elapsed.
In case VS <
V
POR,f
, an device internal reset will be generated and the SBC is switched OFF and will restart in
INIT mode at the next VS rising. This is shown in
Figure 51
.
Figure 51 Ramp up / down example of Supply Voltage
t
VCC1
t
V
POR,f
RO
t
VS
V
POR,r
t
RD1
V
RT1,r
V
RTx,f
t
SBC Mode
SBC OFF
SBC OFF
SBC INIT MODE
Any SBC MODE
SPI
Command
The reset threshold can be
configured via SPI in SBC
Normal Mode , default is V
RT1
Re-
start
SBC Restart Mode is
entered whenever the
Reset is triggered
