Document Number: 002-10634 Rev. *J
Page
217 of 307
S6J3350 Series
Common timing between read and write
(T
A
: Recommended operating conditions, Vcc53 = 5.0 V ± 10 %, V
SS
= 0.0 V)
(External load capacitance 16 pF)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Max
Cycle time
(without MRDY)
t
CYC
MCLK
2mA is selected in
ODR bit in
PPC_PCFGR register.
62.5
-
ns
Cycle time
(with MRDY)
t
CYC
MCLK
62.5
-
ns
If using MRDY,
set MCLK to
20 MHz or
less.
CS delay time
t
CSO
MCLK,
MCSX0 to MCSX3
0.5
18
ns
Address delay time
t
AO
MCLK,
MAD00 to MAD23
0.5
18
ns
RDY setup time
t
RDYS
MCLK, MRDY
"CMOS Schmitt input"
and "Disable noise
filter" are selected in
PPC_PCFGR register.
21
-
ns
RDY hold time
t
RDYH
MCLK, MRDY
0
-
ns
Notes: This is Target Spec.
−
External bus I/F common timing
