Infineon Technologies CYPRESS Traveo S6J335 Series Manual Download Page 221

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Document Number: 002-10634 Rev. *J

Page

220 of 307

S6J3350 Series

9.1.4.15

DDR-HSSPI

(1) DDR-HSSPI Interface Timing (SDR Mode)

: Recommended operating conditions, Vcc3 = 3.3 V ± 0.3 V, V

= DV

= AV

= 0.0 V)

Parameter

Symbol

Pin Name

Conditions

Value

Unit

Remarks

Min

Max

HSSPI clock cycle

cyc

M_SCLK0

(CL = 20pF,

= -10mA,

= 10mA),

when

Quad Page

Program

M_SCLK↑ ->
delayed sample clock↑

spcnt

31.5

M_SDATA -> M_SLCK↑
Input setup time

isdata

M_SDATA0_0-3
M_SDATA1_0-3

M_SCLK↑ -> M_SDATA
Input hold time

ihdata

M_SDATA0_0-3
M_SDATA1_0-3

M_SCLK↑ -> M_SDATA
Output delay time

oddata

M_SDATA0_0-3
M_SDATA1_0-3

cyc

/2 + 2

M_SCLK↑ -> M_SDATA
Output hold time

ohdata

M_SDATA0_0-3
M_SDATA1_0-3

cyc

/2 - 3

M_SCLK↑ -> M_SSEL
Output delay time

odsel

M_SSEL0, 1

12.00+(SS2

CD+0.5)* t

cyc

M_SCLK↑ -> M_SSEL
Output hold time

ohsel

M_SSEL0, 1

cyc

- 2

Notes: This is Target Spec.

−

SS2CD [1:0] should be configured as 01, 10, or 11.

−

For *1, the delay of the delay sample clock can be configured (DLP function).

Summary of Contents for CYPRESS Traveo S6J335 Series

Page 1: ...ers as part of the Infineon product portfolio Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document Future revisions will occur when appropriate and any changes will be set out on the document history page Continuity of ordering part numbers Infineon continues to support existing pa...

Page 2: ... a microcontroller series for body and gateway Features System 32bit Arm Cortex R5F CPU core at up to 240 MHz General purpose I O port up to 148 12 bit A D converter up to 64 channels External interrupt up to 24 channels Base timer up to 64 channels 32 bit reload timer up to 6 channels 32 bit free run timer 8 channels Input capture unit 12 channels Output compare unit 12 channels Built in CR oscil...

Page 3: ...I O Circuit Type 21 5 2 Note 25 6 Port Description 26 6 1 Port Description List 26 6 2 Remark 44 7 Port Configuration 45 7 1 Resource Input Configuration Module 45 7 2 Port Output Function Configuration 135 8 Precautions and Handling Devices 146 8 1 Handling Precautions 146 8 2 Handling Devices 149 9 Electric Characteristics 151 9 1 Electrical Characteristics 151 10 Acronyms 243 11 Ordering Inform...

Page 4: ...scribed Software Engineer 002 10185 Traveo Platform Hardware Manual 32 Bit Microcontroller Traveo Family S6J33xx S6J34xx S6J35xx Series Hardware Manual Platform Part The function and its operation of CPU core platform are described Software Engineer 002 07884 Application Note The reference software sample application the reference board design and so on are explained Software and Hardware Engineer...

Page 5: ...ction cache 16 Kbyte Program FLASH Option See 2 2 1 Work FLASH 112 Kbyte TCRAM 128 Kbyte System SRAM 384 Kbyte Backup RAM 32 Kbyte Security SHE Option Low latency interrupt Available Power domain 5 domains External power supply 5 V VCC5 VCC53 3 V VCC3 VCC53 1 2 V VCC12 Embedded LDO power supply for 5 0V Available Low voltage detection of external power supply Available Low voltage detection of int...

Page 6: ...l interrupt 512 vectors DDR HSSPI 1 ch A type of Quad SPI Hyper BUS 1 ch See the AC specification on 9 1 4 16 Multi function serial interface 12 ch CAN FD 8 ch CAN FD RAM ECC supported 16 KB ch It equivalents to 128 message buffer per channel of MCAN module Ethernet AVB 1 unit See 2 2 1 External BUS 1 ch Notes The options are described in 2 2 Optional Function ...

Page 7: ...tem RAM 384KB D TCRAM 128KB System RAM 256KB x x x x x x x x x x x x 3 3 J 6 S Ordering options 7 digit Revision Digit C D E Description Fixed Operation frequency of embedded Program Flash and CPU Fixed Stabilization time for sub oscillator Fixed TCFLASH Sector Write Permission and Data Retention after Reset Leakage current improvement Option Digit S B U SHE ON A MK_CEER OFF C D Fixed to Enable VC...

Page 8: ...X7_0 RX7_1 TX7_1 RX0_1 TX0_1 RX0_2 TX0_2 RX1_1 TX1_1 RX2_1 TX2_1 RX3_1 TX3_1 RX3_2 TX3_2 RX4_0 TX4_0 RX5_1 TX5_1 RX6_1 TX6_1 RX7_0 TX7_0 RX7_1 TX7_1 BaseTimer PPG16 17 18 19_TOUT0_0 PPG16 17 18 19_TOUT2_0 PPG20 21 22 23_TOUT0_0 PPG20 21 22 23_TOUT2_0 PPG24 25 26 27_TOUT0_0 PPG24 25 26 27_TOUT2_0 PPG28 29 30 31_TOUT0_0 PPG28 29 30 31_TOUT2_0 PPG16 17 18 19 20 21_TIN1_0 PPG22 23 24 25 26 27_TIN1_0 P...

Page 9: ...T2_2 EINT2_4 EINT3_1 EINT3_2 EINT3_4 EINT4_2 EINT4_4 EINT5_4 EINT5_5 EINT6_1 EINT6_4 EINT7_1 EINT7_4 EINT8_1 EINT8_4 EINT8_5 EINT9_1 EINT9_2 EINT10_1 EINT10_2 EINT10_4 EINT10_5 EINT11_2 EINT11_5 EINT12_1 EINT12_2 EINT12_5 EINT13_2 EINT13_3 EINT13_5 EINT14_1 EINT14_2 EINT14_3 EINT14_5 EINT15_2 EINT15_3 EINT16_1 EINT16_2 EINT16_3 EINT16_4 EINT16_5 EINT17_1 EINT17_3 EINT17_5 EINT18_1 EINT18_3 EINT18_...

Page 10: ...n detail Standard 5 pin JTAG interface 4 kB Embedded Trace Buffer 4 bit trace support for TEQFP package System Control See the Traveo Platform Hardware Manual in detail Main and sub oscillator is available A wide range of 3 6 16 MHz is available for main oscillator 32 KHz is available for sub oscillator Sub clock is enable disable by register settings Clock See the Traveo Platform Hardware Manual ...

Page 11: ... and center spread modes with the conditions defined in 9 1 4 3 Internal Clock Timing Stabilization time is as follows 100 us for PLL 200 us for SSCG External Interrupts See the Traveo Platform Hardware Manual in detail NMI See the Traveo Platform Hardware Manual in detail 1 NMI pin Memory Protection MPU16 AHB See the Traveo Platform Hardware Manual in detail MPU for AXI ch 0 MPU for AHB ch 1 Addi...

Page 12: ... for external voltage is supported LVD for internal voltage is supported See 9 1 4 11 and 9 1 4 12 Low voltage detection for RAM retention RVD RVD for RAM retention is effective during the standby mode only That is it is only for the Backup RAM of 32 KB that the function is available Resource inter connect The output signal of some resources can be inputted to the other resource I O Ports 5 V gene...

Page 13: ...d SPI ch 0 HSSPI as a MCU peripheral Hyper BUS I F ch 0 Hyper Bus as a MCU peripheral The following register is not supported and cannot be used Controller Status Register HYPERBUSIn_CSR Interrupt Enable Register HYPERBUSIn_IEN Interrupt Status Register HYPERBUSIn_ISR Write Protection Register HYPERBUSIn_WPR Test Register HYPERBUSIn_TEST GPO signal can only be used for Internal Control example by ...

Page 14: ...rface Additional Low Latency TX FIFO Interface for DMA configurations MAC Transmit Block half duplex collision back pressure MAC Filtering Block external address match Wakeup On Lan Energy Efficient Ethernet support LPI Operation in Cadence IP PHY Interface GMII SGMII TBI 10 100 1000 Operation 1000 M SGMII Operation Jumbo Frames Physical Control Sub Layer ...

Page 15: ..._1 SOT1_1 PPG5_TOUT0_1 EINT10_2 MAD17 TXD3_1 P3_02 T 27 130 G P4_17 AN33 EINT5_4 PPG25_TOUT2_0 SOT12_1 SCS10_1 PPG5_TOUT2_1 EINT11_2 MAD18 TXER_1 P3_03 T 28 129 H P1_15 AN32 EINT16_0 PPG5_TOUT2_0 OCU10_OTD0_0 ICU10_IN1_0 TIN49_0 SCK17_0 SCK12_1 SCL17 INDICATOR0_1 SCS11_1 PPG0 1 2 3 4 5_TIN1_1 EINT12_2 MAD19 RXD0_1 P3_04 T 29 128 G P1_14 AN31 EINT15_0 PPG5_TOUT0_0 OCU9_OTD1_0 ICU10_IN0_0 TOT48_0 TX...

Page 16: ...OUT0_0 OCU9_OTD1_0 ICU10_IN0_0 TOT48_0 TX3_0 SIN17_0 SYSC0_CLK_1 SCS11_1 PPG0 1 2 3 4 5_TIN1_1 EINT12_2 MAD19 RXD0_1 P3_04 T 23 110 G P3_23 AN30 EINT4_4 TX6_1 SCS120_1 SCS12_1 SIN4_1 EINT15_2 MAD20 RXD3_1 P3_05 T 24 109 G P3_22 AN29 EINT19_1 RX6_1 SCS91_1 SCS13_1 SOT4_1 EINT16_2 MAD21 MDIO_1 P3_06 T 25 108 G P3_21 AN28 EINT3_4 TOT49_1 SCS90_1 SCK4_1 EINT17_2 MOEX P0_14 S 26 107 E P3_20 EINT2_4 PPG...

Page 17: ...2 MAD13 P0_12 S 14 95 AVRH5 PPG3_TOUT2_1 EINT8_2 MAD14 P0_13 S 15 94 AVCC5 VCC53 16 93 H P1_16 ADTRG0_0 EINT9_4 PPG0 1 2 3 4 5_TIN1_0 OCU10_OTD1_0 TOT49_0 SOT17_0 SDA17 WOT SYSC0_CLK_0 VSS 17 92 VCC5 VCC12 18 91 VSS SCK4_1 EINT17_2 MOEX P0_14 S 19 90 VCC12 SCS40_1 EINT18_2 MWEX P0_15 S 20 89 VCC12 SCS41_1 EINT19_2 MCLK P0_16 S 21 88 H P1_15 AN32 EINT16_0 PPG5_TOUT2_0 OCU10_OTD0_0 ICU10_IN1_0 TIN49...

Page 18: ...ANE A A b 0 08 C A B D 8 SIDE VIEW TOP VIEW BOTTOM VIEW b SECTION A A c 10 L1 L θ R1 R2 GAUGE PLANE DETAIL A L2 E1 EXPOSED PAD L 1 1 00 REF L c 0 45 0 09 0 60 0 75 0 20 NOM MIN 28 00 BSC D1 R 2 E 1 E 0 0 08 4 28 00 BSC 30 00 BSC D A 1 A 30 00 BSC 0 05 SYMBOL MAX 8 0 20 1 70 0 15 θ D2 D3 E 2 E 3 7 05 REF 6 05 REF 7 05 REF 6 05 REF b 0 17 0 22 0 27 DIMENSION 1 R 0 08 e 0 50 BSC L 2 0 25 PACKAGE OUTL...

Page 19: ... D A 1 A 26 00 BSC 0 05 SYMBOL MAX 8 0 20 1 70 0 15 θ D2 D3 E 2 E 3 6 65 REF 5 45 REF 6 65 REF 5 45 REF b 0 17 0 22 0 27 e 0 50 BSC DIMENSION 1 R 0 08 L 2 0 25 EXPOSED PAD D1 D 4 5 7 E1 E 0 20 C A B D 0 20 C A B D D3 D2 E3 E2 A A1 2 11 DETAIL A e 0 08 C SEATING PLA NE A A b 0 08 C A B D 8 SIDE VIEW TOP VIEW BOTTOM VIEW b SECTION A A c 10 L1 L θ R1 R2 GAUGE PLANE DETAIL A L2 24 0X24 0X1 7 MM LEV176...

Page 20: ... 00 BSC D A 1 A 22 00 BSC 0 05 SYMBOL MAX 8 0 20 1 70 0 15 θ D2 D3 E 2 E 3 5 80 REF 4 60 REF 5 80 REF 4 60 REF b 0 17 0 22 0 27 e 0 50 BSC DIMENSION 1 R 0 08 L 2 0 25 D1 D 4 5 7 E1 E 0 20 C A B D 0 20 C A B D D3 D2 E3 E2 A A1 2 11 DETAIL A e 0 08 C SEATING PLANE A A b 0 08 C A B D 8 SIDE VIEW TOP VIEW BOTTOM VIEW b SECTION A A c 10 L1 L θ R1 R2 GAUGE PLANE DETAIL A L2 EXPOSED PAD 20 0X20 0X1 7 MM ...

Page 21: ... R L 2 0 25 18 00 BSC 16 00 BSC 5 80 REF 4 60 REF 18 00 BSC 16 00 BSC 5 80 REF 4 60 REF 0 08 0 08 0 20 0 09 0 20 0 13 0 18 0 23 0 45 0 60 0 75 1 00 REF 0 40 BSC D1 D 4 5 7 E1 E 0 20 C A B D 0 20 C A B D D3 D2 E3 E2 A A1 2 11 DETAIL A e 0 08 C SEATING PLANE A A b 0 08 C A B D 8 SIDE VIEW TOP VIEW BOTTOM VIEW b SECTION A A c 10 L1 L θ R1 R2 GAUGE PLANE DETAIL A L2 EXPOSED PAD PACKAGE OUTLINE 144 LEA...

Page 22: ... kΩ with pull down resistor control CMOS hysteresis input D External 1 2 V regulator control Output 2 mA E General purpose I O port Output 1 mA 2 mA or 5 mA selectable 50 kΩ with pull up resistor control 50 kΩ with pull down resistor control CMOS hysteresis input Automotive hysteresis input Pull up control Digital output Digital output Pull down control PSS control TTL input PSS control CMOS hys i...

Page 23: ... kΩ with pull up resistor control 50 kΩ with pull down resistor control CMOS hysteresis input Automotive hysteresis input TTL input I 50 kΩ with pull up CMOS hysteresis input K Main oscillation I O L JTAG_NTRST 50 kΩ with pull down TTL input Pull up control Digital output Digital output Pull down control PSS control Automotive input PSS control CMOS hys input Analog input Pull up control Digital o...

Page 24: ... down resistor control CMOS hysteresis input Automotive hysteresis input Q General purpose I O port Output 1 mA 2 mA 5 mA or 30 mA selectable 50 kΩ with pull up resistor control 50 kΩ with pull down resistor control CMOS hysteresis input Automotive hysteresis input TTL input Digital output Digital output Pull up control Digital output Digital output Pull down control PSS control Automotive input P...

Page 25: ...e 50 kΩ with pull up resistor control 50 kΩ with pull down resistor control CMOS hysteresis input Automotive hysteresis input TTL input PSS OSC control OSC input Pull up control Digital output Digital output Pull down control PSS OSC control Automotive input PSS OSC control CMOS hys input Pull up control Digital output Digital output Pull down control PSS OSC control Automotive input PSS OSC contr...

Page 26: ...istor control 50 kΩ with pull down resistor control CMOS hysteresis input Automotive hysteresis input TTL input 5 2 Note Alphabet which shows I O circuit type is described with corresponding pin number in pin assignment figure Pull up conrol Pull down control PSS control Automotive input PSS contor CMOS hys input TTL input PSS control ...

Page 27: ...V 5 V external power supply pin 1 16 26 133 1 16 34 161 1 22 42 193 VSS GND 17 27 36 43 45 52 59 73 86 91 132 144 17 35 44 51 53 60 67 89 104 115 160 176 23 43 52 59 61 68 75 105 121 134 192 208 NC No connection 29 30 33 34 37 38 41 42 45 46 49 50 AVCC5 A D converter analog power supply pin 94 118 142 AVRH5 A D converter upper limit reference voltage pin 95 119 143 AVRL5 A D converter lower limit ...

Page 28: ...ut pin 1 75 87 TRACE3_1 Trace data 3 output pin 1 76 88 TRACE_CLK_1 Trace clock 1 80 92 TRACE_CTL_1 Trace control 1 79 91 ADTRG0_0 A D converter external trigger input pin 0 93 117 139 ADTRG1_0 A D converter external trigger input pin 0 140 ADTRG0_1 A D converter external trigger input pin 1 134 166 198 ADTRG1_1 A D converter external trigger input pin 1 66 82 94 ADTRG1_2 A D converter external tr...

Page 29: ...nit1 ch 43 input pin 104 128 152 AN44 ADC Unit1 ch 44 input pin 105 129 153 AN45 ADC Unit1 ch 45 input pin 106 130 154 AN46 ADC Unit1 ch 46 input pin 107 131 155 AN47 ADC Unit1 ch 47 input pin 110 134 158 AN48 ADC Unit1 ch 48 input pin 159 AN49 ADC Unit1 ch 49 input pin 111 135 160 AN50 ADC Unit1 ch 50 input pin 112 136 161 AN51 ADC Unit1 ch 51 input pin 113 137 162 AN52 ADC Unit1 ch 52 input pin ...

Page 30: ...84 RX2_1 CAN reception data 2 input pin 1 79 91 RX3_1 CAN reception data 3 input pin 1 98 114 RX5_1 CAN reception data 5 input pin 1 106 123 RX6_1 CAN reception data 6 input pin 1 109 126 RX7_1 CAN reception data 7 input pin 1 206 RX0_2 CAN reception data 0 input pin 2 6 RX3_2 CAN reception data 3 input pin 2 15 EINT0_0 External interrupt input pin 0 137 169 201 EINT1_0 External interrupt input pi...

Page 31: ...6 123 EINT18_1 External interrupt input pin 1 69 81 EINT19_1 External interrupt input pin 1 109 126 EINT20_1 External interrupt input pin 1 105 122 EINT21_1 External interrupt input pin 1 75 87 EINT22_1 External interrupt input pin 1 140 EINT23_1 External interrupt input pin 1 9 9 12 EINT0_2 External interrupt input pin 2 10 10 13 EINT1_2 External interrupt input pin 2 11 11 14 EINT2_2 External in...

Page 32: ...6 88 EINT19_3 External interrupt input pin 3 80 92 EINT20_3 External interrupt input pin 3 96 EINT21_3 External interrupt input pin 3 97 EINT22_3 External interrupt input pin 3 99 EINT23_3 External interrupt input pin 3 100 EINT0_4 External interrupt input pin 4 99 115 EINT1_4 External interrupt input pin 4 116 EINT2_4 External interrupt input pin 4 107 124 EINT3_4 External interrupt input pin 4 1...

Page 33: ...t input pin 6 140 172 204 EINT1_6 External interrupt input pin 6 141 173 205 EINT2_6 External interrupt input pin 6 142 174 206 EINT3_6 External interrupt input pin 6 143 175 207 SCS00_0 Multi function serial ch 0 chip select 0 I O pin 0 64 78 90 SCS10_0 Multi function serial ch 1 chip select 0 I O pin 0 6 6 9 SCS11_0 Multi function serial ch 1 chip select 1 output pin 0 7 7 10 SCS12_0 Multi funct...

Page 34: ... 200 SCS40_1 Multi function serial ch 4 chip select 0 I O pin 1 20 27 35 SCS41_1 Multi function serial ch 4 chip select 1 output pin 1 21 28 36 SCS42_1 Multi function serial ch 4 chip select 2 output pin 1 29 37 SCS43_1 Multi function serial ch 4 chip select 3 output pin 1 22 30 38 SCS80_1 Multi function serial ch 8 chip select 0 I O pin 1 72 84 SCS90_1 Multi function serial ch 9 chip select 0 I O...

Page 35: ...124 148 177 SIN16_0 Multi function serial ch 16 serial data input pin 0 66 82 94 SIN17_0 Multi function serial ch 17 serial data input pin 0 87 111 128 SIN0_1 Multi function serial ch 0 serial data input pin 1 6 6 9 SIN1_1 Multi function serial ch 1 serial data input pin 1 19 25 SIN2_1 Multi function serial ch 2 serial data input pin 1 184 SIN3_1 Multi function serial ch 3 serial data input pin 1 ...

Page 36: ...lock I O pin 107 131 155 SCL10 I2 C ch 10 clock I O pin 114 138 164 SCL11 I2 C ch 11 clock I O pin 120 144 171 SCL12 I2 C ch 12 clock I O pin 125 149 178 SCL16 I2 C ch 16 clock I O pin 67 83 95 SCL17 I2 C ch 17 clock I O pin 88 112 129 SDA0 I2 C ch 0 serial data I O pin 63 77 89 SDA1 I2 C ch 1 serial data I O pin 5 5 5 SDA4 I2 C ch 4 serial data I O pin 139 171 203 SDA8 I2 C ch 8 serial data I O p...

Page 37: ...2_0 Base timer 35 output pin 0 15 PPG18_TOUT0_0 Base timer 36 output pin 0 16 PPG18_TOUT2_0 Base timer 37 output pin 0 17 PPG19_TOUT0_0 Base timer 38 output pin 0 30 PPG19_TOUT2_0 Base timer 39 output pin 0 31 PPG20_TOUT0_0 Base timer 40 output pin 0 77 PPG20_TOUT2_0 Base timer 41 output pin 0 78 PPG21_TOUT0_0 Base timer 42 output pin 0 79 PPG21_TOUT2_0 Base timer 43 output pin 0 80 PPG22_TOUT0_0 ...

Page 38: ...4 186 PPG12_TOUT2_1 Base timer 25 output pin 1 155 187 PPG13_TOUT0_1 Base timer 26 output pin 1 156 188 PPG13_TOUT2_1 Base timer 27 output pin 1 157 189 PPG14_TOUT0_1 Base timer 28 output pin 1 130 158 190 PPG14_TOUT2_1 Base timer 29 output pin 1 162 194 PPG15_TOUT0_1 Base timer 30 output pin 1 163 195 PPG15_TOUT2_1 Base timer 31 output pin 1 164 196 PPG0 1 2 3 4 5_TIN1_0 Base timer 0 2 4 6 8 10 i...

Page 39: ...IN1_0 Input Capture 2 ch 1 input pin 0 66 82 94 ICU8_IN0_0 Input Capture 8 ch 0 input pin 0 67 83 95 ICU8_IN1_0 Input Capture 8 ch 1 input pin 0 68 84 98 ICU9_IN0_0 Input Capture 9 ch 0 input pin 0 70 86 102 ICU9_IN1_0 Input Capture 9 ch 1 input pin 0 71 87 103 ICU10_IN0_0 Input Capture 10 ch 0 input pin 0 87 111 128 ICU10_IN1_0 Input Capture 10 ch 1 input pin 0 88 112 129 ICU0_IN0_1 Input Capture...

Page 40: ...115 TOT49_1 Reload timer ch 49 output pin 1 108 125 AIN8 Up Down counter AIN input pin ch 8 61 73 85 AIN9 Up Down counter AIN input pin ch 9 64 78 90 BIN8 Up Down counter BIN input pin ch 8 62 74 86 BIN9 Up Down counter BIN input pin ch 9 65 81 93 ZIN8 Up Down counter ZIN input pin ch 8 63 77 89 ZIN9 Up Down counter ZIN input pin ch 9 66 82 94 RXD0_0 Ethernet pin 0 47 55 63 RXD1_0 Ethernet pin 0 4...

Page 41: ...pin 50 58 66 M_CK MCU Hyper Bus clock output pin 44 52 60 M_CS _1 MCU Hyper Bus select 1 output pin 42 50 58 M_CS _2 MCU Hyper Bus select 2 output pin 54 62 70 M_DQ0 MCU Hyper Bus Data 0 pin 41 49 57 M_DQ1 MCU Hyper Bus Data 1 pin 40 48 56 M_DQ2 MCU Hyper Bus Data 2 pin 39 47 55 M_DQ3 MCU Hyper Bus Data 3 pin 38 46 54 M_DQ4 MCU Hyper Bus Data 4 pin 48 56 64 M_DQ5 MCU Hyper Bus Data 5 pin 49 57 65 ...

Page 42: ...External Bus pin 155 187 MDATA10 External Bus pin 156 188 MDATA11 External Bus pin 157 189 MDATA12 External Bus pin 162 194 MDATA13 External Bus pin 163 195 MDATA14 External Bus pin 164 196 MDATA15 External Bus pin 165 197 MCLK External Bus pin 21 28 36 MOEX External Bus pin 19 26 34 MWEX External Bus pin 20 27 35 MDQM0 External Bus pin 22 30 38 MDQM1 External Bus pin 29 37 MCSX0 External Bus pin ...

Page 43: ... 54 62 70 P1_01 General Purpose I O port 55 63 71 P1_02 General Purpose I O port 56 64 72 P1_03 General Purpose I O port 61 73 85 P1_04 General Purpose I O port 62 74 86 P1_05 General Purpose I O port 63 77 89 P1_06 General Purpose I O port 64 78 90 P1_07 General Purpose I O port 65 81 93 P1_08 General Purpose I O port 66 82 94 P1_09 General Purpose I O port 67 83 95 P1_10 General Purpose I O port...

Page 44: ...203 P2_16 General Purpose I O port 140 172 204 P2_17 General Purpose I O port 141 173 205 P2_18 General Purpose I O port 142 174 206 P2_19 General Purpose I O port 143 175 207 P3_00 General Purpose I O port 19 25 P3_01 General Purpose I O port 20 26 P3_02 General Purpose I O port 21 27 P3_03 General Purpose I O port 22 28 P3_04 General Purpose I O port 23 29 P3_05 General Purpose I O port 24 32 P3...

Page 45: ...pose I O port 80 P4_12 General Purpose I O port 96 P4_13 General Purpose I O port 97 P4_14 General Purpose I O port 99 P4_15 General Purpose I O port 100 P4_16 General Purpose I O port 116 P4_17 General Purpose I O port 130 P4_18 General Purpose I O port 131 P4_19 General Purpose I O port 136 P4_20 General Purpose I O port 137 P4_21 General Purpose I O port 138 P4_22 General Purpose I O port 140 P...

Page 46: ...which are available through only one port does not have the multiplexer implemented i e No RIC_RESIN register 7 1 1 RIC Register Offset Resource RESSEL 3 0 PORT SEL 3 0 Source for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RIC_RE SIN000 0x0000 SIN16 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P1_08 P4_19 PORTSEL 8 15 RIC_RE SIN001 0x0002 SCK16 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P1_09 P4_21 PORTSE...

Page 47: ...TOT49 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN005 0x000A SCS16 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P1_11 P4_23 PORTSEL 8 15 RIC_RE SIN007 0x000E SIN17 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P1_14 P0_09 PORTSEL 8 15 RIC_RE SIN008 0x0010 SCK17 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P1_15 P4_04 PORTSEL 8 15 RIC_RE SIN009 0x0012 SCL17 RESSEL 0 7 80ns noise filter disable 80ns noise filter enable RESSEL ...

Page 48: ...ter disable 80ns noise filter enable RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN011 0x0016 MFS17_T RIGGER RESSEL 0 7 TOT48 TOT49 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN012 0x0018 SCS17 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P1_17 P4_03 PORTSEL 8 15 RIC_RE SIN021 0x002A SIN0 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P1_03 P0_04 PORTSEL 8 15 RIC_RE SIN022 0x002C SCK0 RESSEL 0 7 RESSEL 8 15 PORTSEL ...

Page 49: ...oise filter enable RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN024 0x0030 SDA0 RESSEL 0 7 80ns noise filter disable 80ns noise filter enable RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN025 0x0032 MFS0_TR IGGER RESSEL 0 7 TOT0 TOT1 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN026 0x0034 SCS0 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P1_06 P0_07 PORTSEL 8 15 RIC_RE SIN028 0x0038 SIN1 RESSEL 0 7 RES...

Page 50: ..._01 PORTSEL 8 15 RIC_RE SIN030 0x003C SCL1 RESSEL 0 7 80ns noise filter disable 80ns noise filter enable RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN031 0x003E SDA1 RESSEL 0 7 80ns noise filter disable 80ns noise filter enable RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN032 0x0040 MFS1_TR IGGER RESSEL 0 7 TOT0 TOT1 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN033 0x0042 SCS1 RESSEL 0 7 RES...

Page 51: ... 12 13 14 15 RIC_RE SIN035 0x0046 SIN2 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P0_21 P4_30 PORTSEL 8 15 RIC_RE SIN036 0x0048 SCK2 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P0_22 P4_31 PORTSEL 8 15 RIC_RE SIN039 0x004E MFS2_TR IGGER RESSEL 0 7 TOT0 TOT1 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN040 0x0050 SCS2 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P0_24 P3_25 PORTSEL 8 15 ...

Page 52: ...ffset Resource RESSEL 3 0 PORT SEL 3 0 Source for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RIC_RE SIN042 0x0054 SIN3 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P0_28 P3_28 PORTSEL 8 15 RIC_RE SIN043 0x0056 SCK3 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P0_29 P3_29 PORTSEL 8 15 ...

Page 53: ...0 TOT1 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN047 0x005E SCS3 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P0_31 P3_31 PORTSEL 8 15 RIC_RE SIN049 0x0062 SIN4 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P2_13 P3_05 PORTSEL 8 15 RIC_RE SIN050 0x0064 SCK4 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P2_14 P0_14 PORTSEL 8 15 RIC_RE SIN051 0x0066 SCL4 RESSEL 0 7 80ns noise filter disable 80ns noise filter enable RESSEL 8 1...

Page 54: ...disable 80ns noise filter enable RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN053 0x006A MFS4_TR IGGER RESSEL 0 7 TOT0 TOT1 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN054 0x006C SCS4 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P2_16 P0_15 PORTSEL 8 15 RIC_RE SIN077 0x009A SIN8 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P1_19 P3_08 P0_27 PORTSEL 8 15 RIC_RE SIN078 0x009C SCK8 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 ...

Page 55: ...lter enable RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN080 0x00A0 SDA8 RESSEL 0 7 80ns noise filter disable 80ns noise filter enable RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN081 0x00A2 MFS8_TR IGGER RESSEL 0 7 TOT16 TOT17 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN082 0x00A4 SCS8 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P1_22 P3_11 P0_30 PORTSEL 8 15 RIC_RE SIN084 0x00A8 SIN9 RESSEL 0 7 RE...

Page 56: ...23 PORTSEL 8 15 RIC_RE SIN086 0x00AC SCL9 RESSEL 0 7 80ns noise filter disable 80ns noise filter enable RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN087 0x00AE SDA9 RESSEL 0 7 80ns noise filter disable 80ns noise filter enable RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN088 0x00B0 MFS9_TR IGGER RESSEL 0 7 TOT16 TOT17 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN089 0x00B2 SCS9 RESSEL 0 7 RE...

Page 57: ...2 PORTSEL 8 15 RIC_RE SIN092 0x00B8 SCK10 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P1_29 P3_13 PORTSEL 8 15 RIC_RE SIN093 0x00BA SCL10 RESSEL 0 7 80ns noise filter disable 80ns noise filter enable RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN094 0x00BC SDA10 RESSEL 0 7 80ns noise filter disable 80ns noise filter enable RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN095 0x00BE MFS10_T RIGGER RESSEL 0 7...

Page 58: ...5 PORTSEL 8 15 RIC_RE SIN100 0x00C8 SCL11 RESSEL 0 7 80ns noise filter disable 80ns noise filter enable RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN101 0x00CA SDA11 RESSEL 0 7 80ns noise filter disable 80ns noise filter enable RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN102 0x00CC MFS11_T RIGGER RESSEL 0 7 TOT16 TOT17 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN105 0x00D2 SIN12 RESSEL 0 7...

Page 59: ...5 PORTSEL 8 15 RIC_RE SIN107 0x00D6 SCL12 RESSEL 0 7 80ns noise filter disable 80ns noise filter enable RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN108 0x00D8 SDA12 RESSEL 0 7 80ns noise filter disable 80ns noise filter enable RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN109 0x00DA MFS12_T RIGGER RESSEL 0 7 TOT16 TOT17 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN110 0x00DC SCS12 RESSEL 0 7...

Page 60: ...9 PORTSEL 8 15 RIC_RE SIN134 0x010C RX6 RESSEL 0 7 PORT_ PIN MCAN6 _PIN_A ND_TX RESSEL 8 15 PORTSEL 0 7 P1_21 P3_22 PORTSEL 8 15 RIC_RE SIN135 0x010E RX7 RESSEL 0 7 PORT_ PIN MCAN7 _PIN_A ND_TX RESSEL 8 15 PORTSEL 0 7 P4_22 P2_18 PORTSEL 8 15 RIC_RE SIN136 0x0110 RX0 RESSEL 0 7 PORT_ PIN MCAN0 _PIN_A ND_TX RESSEL 8 15 PORTSEL 0 7 P1_05 P3_09 P4_00 PORTSEL 8 15 RIC_RE SIN137 0x0112 RX1 RESSEL 0 7 P...

Page 61: ... 9 10 11 12 13 14 15 RIC_RE SIN138 0x0114 RX2 RESSEL 0 7 PORT_ PIN MCAN2 _PIN_A ND_TX RESSEL 8 15 PORTSEL 0 7 P1_11 P3_14 PORTSEL 8 15 RIC_RE SIN139 0x0116 RX3 RESSEL 0 7 PORT_ PIN MCAN3 _PIN_A ND_TX RESSEL 8 15 PORTSEL 0 7 P1_13 P3_16 P4_03 PORTSEL 8 15 RIC_RE SIN140 0x0118 RX4 RESSEL 0 7 PORT_ PIN MCAN4 _PIN_A ND_TX RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 ...

Page 62: ...9 RLT49_ UFSET RESSEL 8 15 PORTSEL 0 7 P1_13 P3_16 PORTSEL 8 15 RIC_RE SIN142 0x011C TIN49 RESSEL 0 7 PORT_ PIN TOT48 RLT48_ UFSET RESSEL 8 15 PORTSEL 0 7 P1_15 P3_20 PORTSEL 8 15 RIC_RESI N144 0x0120 TIN0 RESSEL 0 7 PORT_PI N TOT1 RLT1_UF SET PPG0_T OUT0 RESSEL 8 15 PORTSEL 0 7 P1_03 P3_08 PORTSEL 8 15 RIC_RESI N145 0x0122 TIN1 RESSEL 0 7 PORT_PI N TOT0 RLT0_UF SET PPG1_T OUT0 RESSEL 8 15 PORTSEL...

Page 63: ...rce for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RIC_RE SIN160 0x0140 TIN16 RESSEL 0 7 PORT_ PIN TOT17 RLT17_ UFSET PPG6_T OUT0 RESSEL 8 15 PORTSEL 0 7 P1_07 P3_12 PORTSEL 8 15 RIC_RE SIN161 0x0142 TIN17 RESSEL 0 7 PORT_ PIN TOT16 RLT16_ UFSET PPG7_T OUT0 RESSEL 8 15 PORTSEL 0 7 P1_11 P3_14 PORTSEL 8 15 ...

Page 64: ...16 PORTSEL 8 15 RIC_RE SIN193 0x0182 EINT1 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P0_01 P3_00 P0_09 P0_22 P4_16 P4_27 P2_17 PORTSEL 8 15 RIC_RE SIN194 0x0184 EINT2 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P0_21 P4_30 P4_03 P0_23 P3_20 P2_02 P2_18 PORTSEL 8 15 RIC_RE SIN195 0x0186 EINT3 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P0_28 P3_28 P4_04 P0_24 P3_21 P2_03 P2_19 PORTSEL 8 15 RIC_RE SIN196 0x0188 EINT4 RESSEL...

Page 65: ...17 P4_28 PORTSEL 8 15 RIC_RE SIN198 0x018C EINT6 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P1_05 P3_09 P0_11 P0_27 P4_18 P2_06 PORTSEL 8 15 RIC_RE SIN199 0x018E EINT7 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P1_06 P4_00 P0_12 P0_29 P4_20 P2_07 PORTSEL 8 15 RIC_RE SIN200 0x0190 EINT8 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P1_07 P3_11 P0_13 P0_30 P4_21 P4_29 PORTSEL 8 15 RIC_RE SIN201 0x0192 EINT9 RESSEL 0 7 RESSEL ...

Page 66: ...3 P4_31 PORTSEL 8 15 RIC_RE SIN203 0x0196 EINT11 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P1_10 P0_04 P3_03 P1_01 P1_18 P3_24 PORTSEL 8 15 RIC_RE SIN204 0x0198 EINT12 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P1_11 P3_14 P3_04 P1_02 P1_20 P3_25 PORTSEL 8 15 RIC_RE SIN205 0x019A EINT13 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P1_12 P0_05 P4_06 P4_08 P1_22 P3_26 PORTSEL 8 15 RIC_RE SIN206 0x019C EINT14 RESSEL 0 7 RESS...

Page 67: ...5 P2_09 PORTSEL 8 15 RIC_RE SIN208 0x01A0 EINT16 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P1_15 P4_19 P3_06 P4_11 P4_24 P3_29 PORTSEL 8 15 RIC_RE SIN209 0x01A2 EINT17 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P1_17 P3_19 P0_14 P3_10 P1_26 P3_30 PORTSEL 8 15 RIC_RE SIN210 0x01A4 EINT18 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P1_19 P3_08 P0_15 P3_13 P1_27 P3_31 PORTSEL 8 15 RIC_RE SIN211 0x01A6 EINT19 RESSEL 0 7 RESS...

Page 68: ...0 7 RESSEL 8 15 PORTSEL 0 7 P1_23 P3_18 P3_07 P4_12 P1_29 P2_11 PORTSEL 8 15 RIC_RE SIN213 0x01AA EINT21 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P1_28 P3_12 P0_17 P4_13 P1_30 P2_12 PORTSEL 8 15 RIC_RE SIN214 0x01AC EINT22 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P2_00 P4_22 P0_18 P4_14 P1_31 P2_14 PORTSEL 8 15 RIC_RE SIN215 0x01AE EINT23 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P2_05 P0_07 P0_19 P4_15 P4_26 P2_15 ...

Page 69: ...0 RESSEL 0 7 PORT_ PIN TOT0 TOT1 PPG0_T OUT2 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN217 0x01B2 TEXT1 RESSEL 0 7 PORT_ PIN TOT0 TOT1 PPG1_T OUT2 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN218 0x01B4 TEXT2 RESSEL 0 7 PORT_ PIN TOT0 TOT1 PPG2_T OUT2 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN219 0x01B6 TEXT3 RESSEL 0 7 PORT_ PIN TOT0 TOT1 PPG3_T OUT2 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 ...

Page 70: ...TOT0 TOT1 PPG4_T OUT2 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN224 0x01C0 TEXT8 RESSEL 0 7 PORT_ PIN RLT0_U FSET RLT16_ UFSET PPG6_T OUT2 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN225 0x01C2 TEXT9 RESSEL 0 7 PORT_ PIN RLT0_U FSET RLT16_ UFSET PPG7_T OUT2 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN226 0x01C4 TEXT10 RESSEL 0 7 PORT_ PIN RLT0_U FSET RLT16_ UFSET PPG8_T OUT2 RESSEL 8 15...

Page 71: ...0 7 PORTSEL 8 15 OCU0_CK 1 RESSEL 0 7 FRT0 FRT1 FRT2 FRT3 FRT4 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU0_D OWNB0 RESSEL 0 7 FRT0_D OWNB FRT1_D OWNB FRT2_D OWNB FRT3_D OWNB FRT4_D OWNB RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU0_D OWNB1 RESSEL 0 7 FRT0_D OWNB FRT1_D OWNB FRT2_D OWNB FRT3_D OWNB FRT4_D OWNB RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU0_FC MD0 RESSEL 0 7 FRT0_F CMD FRT1_F CMD FRT2_F CMD FR...

Page 72: ...0 7 PORTSEL 8 15 OCU0_MT SF0 RESSEL 0 7 FRT0_M TSF FRT1_M TSF FRT2_M TSF FRT3_M TSF FRT4_M TSF RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU0_MT SF1 RESSEL 0 7 FRT0_M TSF FRT1_M TSF FRT2_M TSF FRT3_M TSF FRT4_M TSF RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU0_T0 31 0 RESSEL 0 7 FRT0_T 31 0 FRT1_T 31 0 FRT2_T 31 0 FRT3_T 31 0 FRT4_T 31 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU0_T1 31 0 RESSEL 0 7 FRT0_T 3...

Page 73: ...SF FRT4_Z TSF RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU0_ZT SF1 RESSEL 0 7 FRT0_Z TSF FRT1_Z TSF FRT2_Z TSF FRT3_Z TSF FRT4_Z TSF RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN233 0x01D2 OCU0_M OD0 RESSEL 0 7 set 1 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN234 0x01D4 OCU0_M OD1 RESSEL 0 7 set 1 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN235 0x01D6 OCU1_CK 0 RESSEL 0 7 FRT0 FRT...

Page 74: ...8 15 OCU1_D OWNB0 RESSEL 0 7 FRT0_D OWNB FRT1_D OWNB FRT2_D OWNB FRT3_D OWNB FRT4_D OWNB RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU1_D OWNB1 RESSEL 0 7 FRT0_D OWNB FRT1_D OWNB FRT2_D OWNB FRT3_D OWNB FRT4_D OWNB RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU1_FC MD0 RESSEL 0 7 FRT0_F CMD FRT1_F CMD FRT2_F CMD FRT3_F CMD FRT4_F CMD RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU1_FC MD1 RESSEL 0 7 FRT0_F CMD FRT1...

Page 75: ...1_M TSF FRT2_M TSF FRT3_M TSF FRT4_M TSF RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU1_MT SF1 RESSEL 0 7 FRT0_M TSF FRT1_M TSF FRT2_M TSF FRT3_M TSF FRT4_M TSF RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU1_T0 31 0 RESSEL 0 7 FRT0_T 31 0 FRT1_T 31 0 FRT2_T 31 0 FRT3_T 31 0 FRT4_T 31 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU1_T1 31 0 RESSEL 0 7 FRT0_T 31 0 FRT1_T 31 0 FRT2_T 31 0 FRT3_T 31 0 FRT4_T 31 0 RE...

Page 76: ...SF0 RESSEL 0 7 FRT0_Z TSF FRT1_Z TSF FRT2_Z TSF FRT3_Z TSF FRT4_Z TSF RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU1_ZT SF1 RESSEL 0 7 FRT0_Z TSF FRT1_Z TSF FRT2_Z TSF FRT3_Z TSF FRT4_Z TSF RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN236 0x01D8 OCU1_M OD0 RESSEL 0 7 set 1 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN237 0x01DA OCU1_M OD1 RESSEL 0 7 set 1 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL...

Page 77: ... 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RIC_RE SIN238 0x01DC OCU2_CK 0 RESSEL 0 7 FRT0 FRT1 FRT2 FRT3 FRT4 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU2_CK 1 RESSEL 0 7 FRT0 FRT1 FRT2 FRT3 FRT4 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU2_D OWNB0 RESSEL 0 7 FRT0_D OWNB FRT1_D OWNB FRT2_D OWNB FRT3_D OWNB FRT4_D OWNB RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 ...

Page 78: ...8 15 PORTSEL 0 7 PORTSEL 8 15 OCU2_FC MD0 RESSEL 0 7 FRT0_F CMD FRT1_F CMD FRT2_F CMD FRT3_F CMD FRT4_F CMD RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU2_FC MD1 RESSEL 0 7 FRT0_F CMD FRT1_F CMD FRT2_F CMD FRT3_F CMD FRT4_F CMD RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU2_MT SF0 RESSEL 0 7 FRT0_M TSF FRT1_M TSF FRT2_M TSF FRT3_M TSF FRT4_M TSF RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU2_MT SF1 RESSEL 0 7 FR...

Page 79: ...RT1_T 31 0 FRT2_T 31 0 FRT3_T 31 0 FRT4_T 31 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU2_T1 31 0 RESSEL 0 7 FRT0_T 31 0 FRT1_T 31 0 FRT2_T 31 0 FRT3_T 31 0 FRT4_T 31 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU2_ZT SF0 RESSEL 0 7 FRT0_Z TSF FRT1_Z TSF FRT2_Z TSF FRT3_Z TSF FRT4_Z TSF RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU2_ZT SF1 RESSEL 0 7 FRT0_Z TSF FRT1_Z TSF FRT2_Z TSF FRT3_Z TSF FRT4_Z TSF RE...

Page 80: ...Resource RESSEL 3 0 PORT SEL 3 0 Source for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RIC_RE SIN239 0x01DE OCU2_M OD0 RESSEL 0 7 set 1 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN240 0x01E0 OCU2_M OD1 RESSEL 0 7 set 1 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 ...

Page 81: ... FRT8 FRT9 FRT10 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU8_CK 1 RESSEL 0 7 FRT8 FRT9 FRT10 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU8_D OWNB0 RESSEL 0 7 FRT8_D OWNB FRT9_D OWNB FRT10_ DOWNB RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU8_D OWNB1 RESSEL 0 7 FRT8_D OWNB FRT9_D OWNB FRT10_ DOWNB RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU8_FC MD0 RESSEL 0 7 FRT8_F CMD FRT9_F CMD FRT10_ FCMD RESSEL 8 15 PORTSEL...

Page 82: ...CMD FRT10_ FCMD RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU8_MT SF0 RESSEL 0 7 FRT8_M TSF FRT9_M TSF FRT10_ MTSF RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU8_MT SF1 RESSEL 0 7 FRT8_M TSF FRT9_M TSF FRT10_ MTSF RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU8_T0 31 0 RESSEL 0 7 FRT8_T 31 0 FRT9_T 31 0 FRT10_ T 31 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU8_T1 31 0 RESSEL 0 7 FRT8_T 31 0 FRT9_T 31 0 FRT10_ T 31 ...

Page 83: ...0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RIC_RE SIN256 0x0200 OCU8_ZT SF0 RESSEL 0 7 FRT8_Z TSF FRT9_Z TSF FRT10_ ZTSF RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU8_ZT SF1 RESSEL 0 7 FRT8_Z TSF FRT9_Z TSF FRT10_ ZTSF RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN257 0x0202 OCU8_M OD0 RESSEL 0 7 set 1 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 ...

Page 84: ... for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RIC_RE SIN258 0x0204 OCU8_M OD1 RESSEL 0 7 set 1 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN259 0x0206 OCU9_CK 0 RESSEL 0 7 FRT8 FRT9 FRT10 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU9_CK 1 RESSEL 0 7 FRT8 FRT9 FRT10 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 ...

Page 85: ..._D OWNB FRT10_ DOWNB RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU9_D OWNB1 RESSEL 0 7 FRT8_D OWNB FRT9_D OWNB FRT10_ DOWNB RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU9_FC MD0 RESSEL 0 7 FRT8_F CMD FRT9_F CMD FRT10_ FCMD RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU9_FC MD1 RESSEL 0 7 FRT8_F CMD FRT9_F CMD FRT10_ FCMD RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU9_MT SF0 RESSEL 0 7 FRT8_M TSF FRT9_M TSF FRT10_ MTSF...

Page 86: ...TSF FRT10_ MTSF RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU9_T0 31 0 RESSEL 0 7 FRT8_T 31 0 FRT9_T 31 0 FRT10_ T 31 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU9_T1 31 0 RESSEL 0 7 FRT8_T 31 0 FRT9_T 31 0 FRT10_ T 31 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU9_ZT SF0 RESSEL 0 7 FRT8_Z TSF FRT9_Z TSF FRT10_ ZTSF RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU9_ZT SF1 RESSEL 0 7 FRT8_Z TSF FRT9_Z TSF FRT10_ ZTS...

Page 87: ...Resource RESSEL 3 0 PORT SEL 3 0 Source for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RIC_RE SIN260 0x0208 OCU9_M OD0 RESSEL 0 7 set 1 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN261 0x020A OCU9_M OD1 RESSEL 0 7 set 1 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 ...

Page 88: ... 15 RIC_RE SIN262 0x020C OCU10_C K0 RESSEL 0 7 FRT8 FRT9 FRT10 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU10_C K1 RESSEL 0 7 FRT8 FRT9 FRT10 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU10_D OWNB0 RESSEL 0 7 FRT8_D OWNB FRT9_D OWNB FRT10_ DOWNB RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU10_D OWNB1 RESSEL 0 7 FRT8_D OWNB FRT9_D OWNB FRT10_ DOWNB RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 ...

Page 89: ...L 3 0 PORT SEL 3 0 Source for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RIC_RE SIN262 0x020C OCU10_F CMD0 RESSEL 0 7 FRT8_F CMD FRT9_F CMD FRT10_ FCMD RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU10_F CMD1 RESSEL 0 7 FRT8_F CMD FRT9_F CMD FRT10_ FCMD RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 ...

Page 90: ...0C OCU10_M TSF0 RESSEL 0 7 FRT8_M TSF FRT9_M TSF FRT10_ MTSF RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU10_M TSF1 RESSEL 0 7 FRT8_M TSF FRT9_M TSF FRT10_ MTSF RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU10_T 0 31 0 RESSEL 0 7 FRT8_T 31 0 FRT9_T 31 0 FRT10_ T 31 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU10_T 1 31 0 RESSEL 0 7 FRT8_T 31 0 FRT9_T 31 0 FRT10_ T 31 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 ...

Page 91: ...L 3 0 PORT SEL 3 0 Source for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RIC_RE SIN262 0x020C OCU10_Z TSF0 RESSEL 0 7 FRT8_Z TSF FRT9_Z TSF FRT10_ ZTSF RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 OCU10_Z TSF1 RESSEL 0 7 FRT8_Z TSF FRT9_Z TSF FRT10_ ZTSF RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 ...

Page 92: ...x020E OCU10_M OD0 RESSEL 0 7 set 1 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN264 0x0210 OCU10_M OD1 RESSEL 0 7 set 1 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN280 0x0230 ICU0_IN0 RESSEL 0 7 PORT_ PIN MFS0_L SYN RESSEL 8 15 PORTSEL 0 7 P1_03 P3_08 PORTSEL 8 15 RIC_RE SIN281 0x0232 ICU0_IN1 RESSEL 0 7 PORT_ PIN MFS1_L SYN RESSEL 8 15 PORTSEL 0 7 P1_04 P3_09 PORTSEL 8 15 ...

Page 93: ... 0 FRT1_T 31 0 FRT2_T 31 0 FRT3_T 31 0 FRT4_T 31 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 ICU0_T1 31 0 RESSEL 0 7 FRT0_T 31 0 FRT1_T 31 0 FRT2_T 31 0 FRT3_T 31 0 FRT4_T 31 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN283 0x0236 ICU1_IN0 RESSEL 0 7 PORT_ PIN MFS2_L SYN RESSEL 8 15 PORTSEL 0 7 P1_05 P3_10 PORTSEL 8 15 RIC_RE SIN284 0x0238 ICU1_IN1 RESSEL 0 7 PORT_ PIN MFS3_L SYN RESSEL 8 15 PORTSE...

Page 94: ...0_T 31 0 FRT1_T 31 0 FRT2_T 31 0 FRT3_T 31 0 FRT4_T 31 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 ICU1_T1 31 0 RESSEL 0 7 FRT0_T 31 0 FRT1_T 31 0 FRT2_T 31 0 FRT3_T 31 0 FRT4_T 31 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN286 0x023C ICU2_IN0 RESSEL 0 7 PORT_ PIN MFS4_L SYN RESSEL 8 15 PORTSEL 0 7 P1_07 P3_12 PORTSEL 8 15 RIC_RE SIN287 0x023E ICU2_IN1 RESSEL 0 7 PORT_ PIN RESSEL 8 15 PORTSEL 0 7...

Page 95: ... 0 FRT1_T 31 0 FRT2_T 31 0 FRT3_T 31 0 FRT4_T 31 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 ICU2_T1 31 0 RESSEL 0 7 FRT0_T 31 0 FRT1_T 31 0 FRT2_T 31 0 FRT3_T 31 0 FRT4_T 31 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN304 0x0260 ICU8_IN0 RESSEL 0 7 PORT_ PIN MFS8_L SYN RESSEL 8 15 PORTSEL 0 7 P1_09 P3_14 PORTSEL 8 15 RIC_RE SIN305 0x0262 ICU8_IN1 RESSEL 0 7 PORT_ PIN MFS9_L SYN RESSEL 8 15 PORTSE...

Page 96: ... RESSEL 0 7 FRT8_T 31 0 FRT9_T 31 0 FRT10_ T 31 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 ICU8_T1 31 0 RESSEL 0 7 FRT8_T 31 0 FRT9_T 31 0 FRT10_ T 31 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN307 0x0266 ICU9_IN0 RESSEL 0 7 PORT_ PIN MFS10_ LSYN RESSEL 8 15 PORTSEL 0 7 P1_11 P3_16 PORTSEL 8 15 RIC_RE SIN308 0x0268 ICU9_IN1 RESSEL 0 7 PORT_ PIN MFS11_ LSYN RESSEL 8 15 PORTSEL 0 7 P1_12 P3_17 POR...

Page 97: ...31 0 RESSEL 0 7 FRT8_T 31 0 FRT9_T 31 0 FRT10_ T 31 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 ICU9_T1 31 0 RESSEL 0 7 FRT8_T 31 0 FRT9_T 31 0 FRT10_ T 31 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN310 0x026C ICU10_IN 0 RESSEL 0 7 PORT_ PIN MFS12_ LSYN RESSEL 8 15 PORTSEL 0 7 P1_14 P3_18 PORTSEL 8 15 RIC_RE SIN311 0x026E ICU10_IN 1 RESSEL 0 7 PORT_ PIN RESSEL 8 15 PORTSEL 0 7 P1_15 P3_19 PORTSEL...

Page 98: ...12 0x0270 ICU10_T0 31 0 RESSEL 0 7 FRT8_T 31 0 FRT9_T 31 0 FRT10_ T 31 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 ICU10_T1 31 0 RESSEL 0 7 FRT8_T 31 0 FRT9_T 31 0 FRT10_ T 31 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN352 0x02C0 AIN8 RESSEL 0 7 PORT_ PIN TOT0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN353 0x02C2 BIN8 RESSEL 0 7 PORT_ PIN TOT1 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 ...

Page 99: ...ESSEL 0 7 PORT_ PIN TOT16 PPG6_T OUT0 PPG6_T OUT2 PPG7_T OUT0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN355 0x02C6 AIN9 RESSEL 0 7 PORT_ PIN TOT16 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN356 0x02C8 BIN9 RESSEL 0 7 PORT_ PIN TOT17 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN357 0x02CA ZIN9 RESSEL 0 7 PORT_ PIN TOT0 PPG6_T OUT0 PPG6_T OUT2 PPG7_T OUT0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8...

Page 100: ...T0 RLT0_U FSET TOT0 RLT0_U FSET FRT0_M TSF OCU0_ OTD0 RESSEL 8 15 PORTSEL 0 7 P1_16 P3_04 PORTSEL 8 15 RIC_RE SIN377 0x02F2 PPG0_TI N2 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN378 0x02F4 PPG0_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN379 0x02F6 PPG1_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET TOT0 RLT0_U FSET FRT0_M TSF OCU0_ OTD0 RESSEL 8 15 PORT...

Page 101: ...ORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN381 0x02FA PPG1_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN382 0x02FC PPG2_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET TOT0 RLT0_U FSET FRT0_M TSF OCU0_ OTD0 RESSEL 8 15 PORTSEL 0 7 P1_16 P3_04 PORTSEL 8 15 RIC_RE SIN383 0x02FE PPG2_TI N2 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN384 0x0300 PPG2_TI N3 RESSEL 0 7 set...

Page 102: ...OCU0_ OTD0 RESSEL 8 15 PORTSEL 0 7 P1_16 P3_04 PORTSEL 8 15 RIC_RE SIN386 0x0304 PPG3_TI N2 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN387 0x0306 PPG3_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN388 0x0308 PPG4_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET TOT1 RLT1_U FSET FRT0_M TSF OCU0_ OTD0 RESSEL 8 15 PORTSEL 0 7 P1_16 P3_04 PORTSEL 8 15 RIC_RE SIN...

Page 103: ... 0x030E PPG5_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET TOT1 RLT1_U FSET FRT0_M TSF OCU0_ OTD0 RESSEL 8 15 PORTSEL 0 7 P1_16 P3_04 PORTSEL 8 15 RIC_RE SIN392 0x0310 PPG5_TI N2 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN393 0x0312 PPG5_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN394 0x0314 PPG6_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET TOT16 RLT16_ ...

Page 104: ...RTSEL 0 7 PORTSEL 8 15 RIC_RE SIN396 0x0318 PPG6_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN397 0x031A PPG7_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET TOT16 RLT16_ UFSET FRT8_M TSF OCU8_ OTD0 RESSEL 8 15 PORTSEL 0 7 P1_29 P3_20 PORTSEL 8 15 RIC_RE SIN398 0x031C PPG7_TI N2 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN399 0x031E PPG7_TI N3 RESSEL 0 7 se...

Page 105: ...OCU8_ OTD0 RESSEL 8 15 PORTSEL 0 7 P1_29 P3_20 PORTSEL 8 15 RIC_RE SIN401 0x0322 PPG8_TI N2 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN402 0x0324 PPG8_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN403 0x0326 PPG9_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET TOT17 RLT17_ UFSET FRT8_M TSF OCU8_ OTD0 RESSEL 8 15 PORTSEL 0 7 P1_29 P3_20 PORTSEL 8 15 RIC_RE S...

Page 106: ...032C PPG10_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET TOT17 RLT17_ UFSET FRT8_M TSF OCU8_ OTD0 RESSEL 8 15 PORTSEL 0 7 P1_29 P3_20 PORTSEL 8 15 RIC_RE SIN407 0x032E PPG10_TI N2 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN408 0x0330 PPG10_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN409 0x0332 PPG11_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET TOT17 RLT1...

Page 107: ...et 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN411 0x0336 PPG11_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN430 0x035C PPG12_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET RESSEL 8 15 PORTSEL 0 7 P2_06 P3_31 PORTSEL 8 15 RIC_RE SIN431 0x035E PPG12_TI N2 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN432 0x0360 PPG12_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PO...

Page 108: ...T0_U FSET RESSEL 8 15 PORTSEL 0 7 P2_06 P3_31 PORTSEL 8 15 RIC_RE SIN434 0x0364 PPG13_TI N2 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN435 0x0366 PPG13_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN436 0x0368 PPG14_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET RESSEL 8 15 PORTSEL 0 7 P2_06 P3_31 PORTSEL 8 15 RIC_RE SIN437 0x036A PPG14_TI N2 RESSEL 0 7 set...

Page 109: ...L 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN439 0x036E PPG15_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET RESSEL 8 15 PORTSEL 0 7 P2_06 P3_31 PORTSEL 8 15 RIC_RE SIN440 0x0370 PPG15_TI N2 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN441 0x0372 PPG15_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN442 0x0374 PPG16_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET RES...

Page 110: ... 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN444 0x0378 PPG16_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN445 0x037A PPG17_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN446 0x037C PPG17_TI N2 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN447 0x037E PPG17_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL ...

Page 111: ... PIN TOT0 RLT0_U FSET RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN449 0x0382 PPG18_TI N2 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN450 0x0384 PPG18_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN451 0x0386 PPG19_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN452 0x0388 PPG19_TI N2 RESSEL 0 7 set 0 RESSEL 8 ...

Page 112: ... RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN454 0x038C PPG20_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN455 0x038E PPG20_TI N2 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN456 0x0390 PPG20_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN457 0x0392 PPG21_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET RESSEL 8 ...

Page 113: ... 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN459 0x0396 PPG21_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN460 0x0398 PPG22_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN461 0x039A PPG22_TI N2 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN462 0x039C PPG22_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL ...

Page 114: ... PIN TOT0 RLT0_U FSET RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN464 0x03A0 PPG23_TI N2 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN465 0x03A2 PPG23_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN466 0x03A4 PPG24_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN467 0x03A6 PPG24_TI N2 RESSEL 0 7 set 0 RESSEL 8 ...

Page 115: ... RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN469 0x03AA PPG25_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN470 0x03AC PPG25_TI N2 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN471 0x03AE PPG25_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN472 0x03B0 PPG26_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET RESSEL 8 ...

Page 116: ... 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN474 0x03B4 PPG26_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN475 0x03B6 PPG27_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN476 0x03B8 PPG27_TI N2 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN477 0x03BA PPG27_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL ...

Page 117: ... PIN TOT0 RLT0_U FSET RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN479 0x03BE PPG28_TI N2 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN480 0x03C0 PPG28_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN481 0x03C2 PPG29_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN482 0x03C4 PPG29_TI N2 RESSEL 0 7 set 0 RESSEL 8 ...

Page 118: ... RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN484 0x03C8 PPG30_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN485 0x03CA PPG30_TI N2 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN486 0x03CC PPG30_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN487 0x03CE PPG31_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET RESSEL 8 ...

Page 119: ...fset Resource RESSEL 3 0 PORT SEL 3 0 Source for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RIC_RE SIN488 0x03D0 PPG31_TI N2 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN489 0x03D2 PPG31_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 ...

Page 120: ...ET OCU1_ OTD0 OCU2_ OTD0 PPG0_T OUT2 PPG2_T OUT0 PPG4_T OUT0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN492 0x03D8 ADC12B0 _HWTRG 2 RESSEL 0 7 PORT_ PIN RLT16_ UFSET RLT17_ UFSET OCU2_ OTD0 OCU8_ OTD0 PPG1_T OUT0 PPG2_T OUT2 PPG4_T OUT2 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN493 0x03DA ADC12B0 _HWTRG 3 RESSEL 0 7 PORT_ PIN RLT17_ UFSET RLT0_U FSET OCU8_ OTD0 OCU9_ OTD0 PPG1_T OUT2 PPG3...

Page 121: ...FSET OCU0_ OTD0 OCU2_ OTD0 PPG3_T OUT0 PPG4_T OUT2 PPG6_T OUT2 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN497 0x03E2 ADC12B0 _HWTRG 7 RESSEL 0 7 PORT_ PIN RLT17_ UFSET RLT1_U FSET OCU1_ OTD0 OCU8_ OTD0 PPG3_T OUT2 PPG5_T OUT0 PPG7_T OUT0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN498 0x03E4 ADC12B0 _HWTRG 8 RESSEL 0 7 PORT_ PIN RLT0_U FSET RLT17_ UFSET OCU2_ OTD0 OCU9_ OTD0 PPG4_T OUT0 PPG...

Page 122: ...ET OCU10_ OTD0 OCU1_ OTD0 PPG5_T OUT2 PPG7_T OUT0 PPG9_T OUT0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN502 0x03EC ADC12B0 _HWTRG 12 RESSEL 0 7 PORT_ PIN RLT0_U FSET RLT1_U FSET OCU0_ OTD0 OCU8_ OTD0 PPG6_T OUT0 PPG7_T OUT2 PPG9_T OUT2 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN503 0x03EE ADC12B0 _HWTRG 13 RESSEL 0 7 PORT_ PIN RLT1_U FSET RLT16_ UFSET OCU1_ OTD0 OCU9_ OTD0 PPG6_T OUT2 PPG...

Page 123: ...OCU9_ OTD0 OCU1_ OTD0 PPG8_T OUT0 PPG9_T OUT2 PPG11_ TOUT2 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN507 0x03F6 ADC12B0 _HWTRG 17 RESSEL 0 7 PORT_ PIN RLT1_U FSET RLT17_ UFSET OCU10_ OTD0 OCU2_ OTD0 PPG8_T OUT2 PPG10_ TOUT0 PPG12_ TOUT0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN508 0x03F8 ADC12B0 _HWTRG 18 RESSEL 0 7 PORT_ PIN RLT16_ UFSET RLT0_U FSET OCU0_ OTD0 OCU9_ OTD0 PPG9_T OUT0 PP...

Page 124: ...U8_ OTD0 OCU1_ OTD0 PPG10_ TOUT2 PPG12_ TOUT0 PPG14_ TOUT0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN512 0x0400 ADC12B0 _HWTRG 22 RESSEL 0 7 PORT_ PIN RLT16_ UFSET RLT1_U FSET OCU9_ OTD0 OCU2_ OTD0 PPG11_ TOUT0 PPG12_ TOUT2 PPG14_ TOUT2 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN513 0x0402 ADC12B0 _HWTRG 23 RESSEL 0 7 PORT_ PIN RLT17_ UFSET RLT16_ UFSET OCU10_ OTD0 OCU8_ OTD0 PPG11_ TOUT2...

Page 125: ...OCU2_ OTD0 OCU1_ OTD0 PPG13_ TOUT0 PPG14_ TOUT2 PPG16_ TOUT2 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN517 0x040A ADC12B0 _HWTRG 27 RESSEL 0 7 PORT_ PIN RLT17_ UFSET RLT0_U FSET OCU8_ OTD0 OCU2_ OTD0 PPG13_ TOUT2 PPG15_ TOUT0 PPG17_ TOUT0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN518 0x040C ADC12B0 _HWTRG 28 RESSEL 0 7 PORT_ PIN RLT0_U FSET RLT16_ UFSET OCU9_ OTD0 OCU8_ OTD0 PPG14_ TOUT0...

Page 126: ...OCU1_ OTD0 OCU2_ OTD0 PPG15_ TOUT2 PPG17_ TOUT0 PPG19_ TOUT0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN586 0x0494 ADC12B1 _HWTRG 32 RESSEL 0 7 PORT_ PIN RLT0_U FSET RLT17_ UFSET OCU2_ OTD0 OCU8_ OTD0 PPG16_ TOUT0 PPG17_ TOUT2 PPG19_ TOUT2 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN587 0x0496 ADC12B1 _HWTRG 33 RESSEL 0 7 PORT_ PIN RLT1_U FSET RLT0_U FSET OCU8_ OTD0 OCU9_ OTD0 PPG16_ TOUT2 ...

Page 127: ...CU0_ OTD0 OCU2_ OTD0 PPG18_ TOUT0 PPG19_ TOUT2 PPG21_ TOUT2 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN591 0x049E ADC12B1 _HWTRG 37 RESSEL 0 7 PORT_ PIN RLT1_U FSET RLT16_ UFSET OCU1_ OTD0 OCU8_ OTD0 PPG18_ TOUT2 PPG20_ TOUT0 PPG22_ TOUT0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN592 0x04A0 ADC12B1 _HWTRG 38 RESSEL 0 7 PORT_ PIN RLT16_ UFSET RLT17_ UFSET OCU2_ OTD0 OCU9_ OTD0 PPG19_ TOUT0...

Page 128: ...CU10_ OTD0 OCU1_ OTD0 PPG20_ TOUT2 PPG22_ TOUT0 PPG24_ TOUT0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN596 0x04A8 ADC12B1 _HWTRG 42 RESSEL 0 7 PORT_ PIN RLT16_ UFSET RLT0_U FSET OCU0_ OTD0 OCU8_ OTD0 PPG21_ TOUT0 PPG22_ TOUT2 PPG24_ TOUT2 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN597 0x04AA ADC12B1 _HWTRG 43 RESSEL 0 7 PORT_ PIN RLT17_ UFSET RLT1_U FSET OCU1_ OTD0 OCU9_ OTD0 PPG21_ TOUT2...

Page 129: ...U9_ OTD0 OCU1_ OTD0 PPG23_ TOUT0 PPG24_ TOUT2 PPG26_ TOUT2 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN601 0x04B2 ADC12B1 _HWTRG 47 RESSEL 0 7 PORT_ PIN RLT17_ UFSET RLT16_ UFSET OCU10_ OTD0 OCU2_ OTD0 PPG23_ TOUT2 PPG25_ TOUT0 PPG27_ TOUT0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN602 0x04B4 ADC12B1 _HWTRG 48 RESSEL 0 7 PORT_ PIN RLT0_U FSET RLT1_U FSET OCU0_ OTD0 OCU9_ OTD0 PPG24_ TOUT0 ...

Page 130: ...CU8_ OTD0 OCU1_ OTD0 PPG25_ TOUT2 PPG27_ TOUT0 PPG29_ TOUT0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN606 0x04BC ADC12B1 _HWTRG 52 RESSEL 0 7 PORT_ PIN RLT0_U FSET RLT16_ UFSET OCU9_ OTD0 OCU2_ OTD0 PPG26_ TOUT0 PPG27_ TOUT2 PPG29_ TOUT2 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN607 0x04BE ADC12B1 _HWTRG 53 RESSEL 0 7 PORT_ PIN RLT1_U FSET RLT17_ UFSET OCU10_ OTD0 OCU8_ OTD0 PPG26_ TOUT2...

Page 131: ... OCU2_ OTD0 OCU1_ OTD0 PPG28_ TOUT0 PPG29_ TOUT2 PPG31_ TOUT2 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN611 0x04C6 ADC12B1 _HWTRG 57 RESSEL 0 7 PORT_ PIN RLT1_U FSET RLT0_U FSET OCU8_ OTD0 OCU2_ OTD0 PPG28_ TOUT2 PPG30_ TOUT0 PPG0_T OUT0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN612 0x04C8 ADC12B1 _HWTRG 58 RESSEL 0 7 PORT_ PIN RLT16_ UFSET RLT1_U FSET OCU9_ OTD0 OCU8_ OTD0 PPG29_ TOUT0 ...

Page 132: ...EL 8 15 RIC_RE SIN615 0x04CE ADC12B1 _HWTRG 61 RESSEL 0 7 PORT_ PIN RLT1_U FSET RLT16_ UFSET OCU1_ OTD0 OCU2_ OTD0 PPG30_ TOUT2 PPG0_T OUT0 PPG2_T OUT0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN616 0x04D0 ADC12B1 _HWTRG 62 RESSEL 0 7 PORT_ PIN RLT16_ UFSET RLT17_ UFSET OCU2_ OTD0 OCU8_ OTD0 PPG31_ TOUT0 PPG0_T OUT2 PPG2_T OUT2 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN617 0x04D2 ADC12B1 ...

Page 133: ...MSTA RT RESSEL 0 7 TOT0 TOT16 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN629 0x04EA MDIO RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P0_31 P3_06 PORTSEL 8 15 RIC_RE SIN630 0x04EC CRS RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P1_02 P0_20 PORTSEL 8 15 RIC_RE SIN631 0x04EE RXD0 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P0_27 P3_04 PORTSEL 8 15 RIC_RE SIN632 0x04F0 RXD1 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P0_28 P4_06 POR...

Page 134: ... RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P0_29 P4_07 PORTSEL 8 15 RIC_RE SIN634 0x04F4 RXD3 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P0_30 P3_05 PORTSEL 8 15 RIC_RE SIN635 0x04F6 COL RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P1_01 P0_19 PORTSEL 8 15 RIC_RE SIN636 0x04F8 RXDV RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P0_19 P4_02 PORTSEL 8 15 RIC_RE SIN637 0x04FA RXER RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P0_18 P4_01 PORTSEL 8...

Page 135: ...PORTSEL 0 7 P1_16 P2_10 PORTSEL 8 15 RIC_RE SIN686 0x055C ADTRG1 RESSEL 0 7 RESSEL 8 15 PORTSEL 0 7 P4_22 P1_08 P2_11 PORTSEL 8 15 Notes When both GPIO_PORTEN GPORTEN and PPC_PCFGR PIE are configured as 0 the input signal is disconnected and external interrupt cannot be detected During disconnecting I O internally outputs low to internal logic and if ELVR is configured as low level detection falli...

Page 136: ... 02 SCK1_0 SCL1 MAD3 PPC_PCF GR003 0x0006 P0_03 GPIO_PO DR0 POD 03 SOT1_0 SDA1 MAD4 PPC_PCF GR004 0x0008 P0_04 GPIO_PO DR0 POD 04 SCS10_0 MAD5 PPC_PCF GR005 0x000A P0_05 GPIO_PO DR0 POD 05 SCS11_0 SOT0_1 MAD6 PPC_PCF GR006 0x000C P0_06 GPIO_PO DR0 POD 06 SCS12_0 SCK0_1 PPG0_TO UT0_1 MAD7 PPC_PCF GR007 0x000E P0_07 GPIO_PO DR0 POD 07 SCS13_0 SCS00_1 PPG0_TO UT2_1 MAD8 PPC_PCF GR008 0x0010 P0_08 GPI...

Page 137: ...R0 POD 19 MCSX3 PPC_PCF GR020 0x0028 P0_20 GPIO_PO DR0 POD 20 PPC_PCF GR021 0x002A P0_21 GPIO_PO DR0 POD 21 M_SDATA 0_0 TXEN_0 M_DQ3 PPC_PCF GR022 0x002C P0_22 GPIO_PO DR0 POD 22 SCK2_0 M_SDATA 0_2 TXD0_0 M_DQ2 SOT9_2 PPC_PCF GR023 0x002E P0_23 GPIO_PO DR0 POD 23 SOT2_0 M_SDATA 0_1 TXD1_0 M_DQ1 SCK9_2 PPC_PCF GR024 0x0030 P0_24 GPIO_PO DR0 POD 24 SCS20_0 M_SSEL0 TXD2_0 M_DQ0 SCS90_2 PPC_PCF GR025 ...

Page 138: ...1_03 GPIO_PO DR1 POD 03 OCU0_O TD0_0 PPG0_TO UT0_0 PPC_PCF GR104 0x0048 P1_04 GPIO_PO DR1 POD 04 SCK0_0 SCL0 OCU0_O TD1_0 TOT0_0 PPG0_TO UT2_0 PPC_PCF GR105 0x004A P1_05 GPIO_PO DR1 POD 05 SOT0_0 SDA0 TRACE0_ 0 PPG1_TO UT0_0 PPC_PCF GR106 0x004C P1_06 GPIO_PO DR1 POD 06 SCS00_0 TX0_0 TRACE1_ 0 TOT1_0 PPG1_TO UT2_0 PPC_PCF GR107 0x004E P1_07 GPIO_PO DR1 POD 07 TRACE2_ 0 OCU1_O TD0_0 PPG2_TO UT0_0 P...

Page 139: ...D 16 SOT17_0 SDA17 OCU10_O TD1_0 TOT49_0 SYSC0_C LK_0 WOT PPC_PCF GR117 0x0062 P1_17 GPIO_PO DR1 POD 17 SCS170_ 0 PPG6_TO UT0_0 PPC_PCF GR118 0x0064 P1_18 GPIO_PO DR1 POD 18 SCS171_ 0 PPG6_TO UT2_0 TX5_0 PPC_PCF GR119 0x0066 P1_19 GPIO_PO DR1 POD 19 PPG7_TO UT0_0 PPC_PCF GR120 0x0068 P1_20 GPIO_PO DR1 POD 20 SCK8_0 SCL8 PPG7_TO UT2_0 PPC_PCF GR121 0x006A P1_21 GPIO_PO DR1 POD 21 SOT8_0 SDA8 PPG8_T...

Page 140: ...0 PPG12_T OUT2_0 PPC_PCF GR200 0x0080 P2_00 GPIO_PO DR2 POD 00 PPG13_T OUT0_0 PPC_PCF GR201 0x0082 P2_01 GPIO_PO DR2 POD 01 SCK11_0 SCL11 PPG13_T OUT2_0 PPC_PCF GR202 0x0084 P2_02 GPIO_PO DR2 POD 02 SOT11_0 SDA11 PPG14_T OUT0_0 PPC_PCF GR203 0x0086 P2_03 GPIO_PO DR2 POD 03 SCS110_ 0 PPG14_T OUT2_0 PPC_PCF GR204 0x0088 P2_04 GPIO_PO DR2 POD 04 SCS111_0 PPG15_T OUT0_0 PPC_PCF GR205 0x008A P2_05 GPIO...

Page 141: ...5 0x009E P2_15 GPIO_PO DR2 POD 15 SOT4_0 SDA4 MDATA4 PPC_PCF GR216 0x00A0 P2_16 GPIO_PO DR2 POD 16 SCS40_0 MDATA5 PPC_PCF GR217 0x00A2 P2_17 GPIO_PO DR2 POD 17 SCS41_0 MDATA6 PPC_PCF GR218 0x00A4 P2_18 GPIO_PO DR2 POD 18 SCS42_0 MDATA7 PPC_PCF GR219 0x00A6 P2_19 GPIO_PO DR2 POD 19 SCS43_0 TX7_1 MAD0 PPC_PCF GR300 0x00C0 P3_00 GPIO_PO DR3 POD 00 TXD1_1 PPG4_TO UT0_1 MAD15 PPC_PCF GR301 0x00C2 P3_01...

Page 142: ...2_T OUT2_0 TX0_1 PPC_PCF GR311 0x00D6 P3_11 GPIO_PO DR3 POD 11 SCS80_1 PPG7_TO UT2_1 OCU1_O TD1_1 TOT1_1 TRACE1_ 1 PPC_PCF GR312 0x00D8 P3_12 GPIO_PO DR3 POD 12 PPG8_TO UT0_1 OCU2_O TD0_1 TRACE2_ 1 TX1_1 PPC_PCF GR313 0x00DA P3_13 GPIO_PO DR3 POD 13 SCK10_1 PPG8_TO UT2_1 OCU2_O TD1_1 TOT16_1 TRACE3_ 1 PPC_PCF GR314 0x00DC P3_14 GPIO_PO DR3 POD 14 SOT10_1 PPG9_TO UT0_1 OCU8_O TD0_1 TRACE_C TL_1 PPC...

Page 143: ...0x00F2 P3_25 GPIO_PO DR3 POD 25 SCS20_1 PPG12_T OUT2_1 MDATA9 PPC_PCF GR326 0x00F4 P3_26 GPIO_PO DR3 POD 26 SCS21_1 PPG13_T OUT0_1 MDATA10 PPC_PCF GR327 0x00F6 P3_27 GPIO_PO DR3 POD 27 SCS22_1 PPG13_T OUT2_1 MDATA11 PPC_PCF GR328 0x00F8 P3_28 GPIO_PO DR3 POD 28 PPG14_T OUT2_1 MDATA12 PPC_PCF GR329 0x00FA P3_29 GPIO_PO DR3 POD 29 SCK3_1 PPG15_T OUT0_1 MDATA13 PPC_PCF GR330 0x00FC P3_30 GPIO_PO DR3 ...

Page 144: ... 0x010E P4_07 GPIO_PO DR4 POD 07 PPG19_T OUT2_0 PPC_PCF GR408 0x0110 P4_08 GPIO_PO DR4 POD 08 PPG20_T OUT0_0 PPC_PCF GR409 0x0112 P4_09 GPIO_PO DR4 POD 09 PPG20_T OUT2_0 PPC_PCF GR410 0x0114 P4_10 GPIO_PO DR4 POD 10 PPG21_T OUT0_0 PPC_PCF GR411 0x0116 P4_11 GPIO_PO DR4 POD 11 PPG21_T OUT2_0 PPC_PCF GR412 0x0118 P4_12 GPIO_PO DR4 POD 12 PPG23_T OUT0_0 PPC_PCF GR413 0x011A P4_13 GPIO_PO DR4 POD 13 P...

Page 145: ... OUT2_0 PPC_PCF GR422 0x012C P4_22 GPIO_PO DR4 POD 22 SCS161_ 1 PPC_PCF GR423 0x012E P4_23 GPIO_PO DR4 POD 23 SCS160_ 1 PPG28_T OUT0_0 TX7_0 PPC_PCF GR424 0x0130 P4_24 GPIO_PO DR4 POD 24 PPG28_T OUT2_0 PPC_PCF GR425 0x0132 P4_25 GPIO_PO DR4 POD 25 PPG29_T OUT0_0 PPC_PCF GR426 0x0134 P4_26 GPIO_PO DR4 POD 26 PPG29_T OUT2_0 PPC_PCF GR427 0x0136 P4_27 GPIO_PO DR4 POD 27 PPG30_T OUT0_0 PPC_PCF GR428 0...

Page 146: ...ates that setting is prohibited If setting the port will be operated as input independent on the register value of the GPIO_DDR The register for P0_20 for POF exists though the port only supports input not supports output The configuration of POF 0 for the port does not affect anything ...

Page 147: ...ng conditions Operation outside these ranges may adversely affect reliability and could result in device failure No warranty is made with respect to uses operating conditions or combinations not represented on the data sheet Users considering application outside the listed conditions are advised to contact their sales representative beforehand Processing and Protection of Pins These precautions mu...

Page 148: ...d array BGA packages with Sn Ag Cu balls are mounted using Sn Pb eutectic soldering junction strength may be reduced under some conditions of use Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins exposure to natural environmental conditions will cause absorption of moisture During mounting the application of heat to a package that has absorbed moisture c...

Page 149: ...rmal operation In such cases use anti static measures or processing to prevent discharges 3 Corrosive Gases Dust or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device If you use devices in such conditions consider ways to prevent such exposure or to protect the devices 4 Radiation Including Cosmic Radiation Most devices ...

Page 150: ... and then open them or set them to the input state and handle them in the same way as input pins About Power Supply Pins If the device has multiple VCC and VSS pins the device is designed in such a way that the pins that should be at the same potential are connected to each other inside the device to prevent malfunctions such as latch up However to reduce unwanted emissions prevent malfunctions of...

Page 151: ... Switch Off VCC12 during Power Off Sequence During power off sequence it is necessary to switch off VCC12 by driving PSC1 pin low by entering PSS mode power domain 2 off If VCC12 needs to be switched off by other means RSTX needs to be asserted before switching off VCC12 to inactivate the operation of VCC12 supplied domain below the operation assurance range About C Pin Processing This device has ...

Page 152: ... 1 VO1 VSS 0 3 VCC5 0 3 V 5 V pins VO2 VSS 0 3 DVCC 0 3 V 5 V 3 V DVCC pins VO3 VSS 0 3 VCC3 0 3 V 3 V pins VO4 VSS 0 3 VCC53 0 3 V 5 V 3 V pins Maximum clamp current ICLAMP 4 mA 13 A Total maximum clamp current Σ ICLAMP 20 mA 13 A Total maximum clamp current Σ ICLAMP 90 mA B Total maximum clamp current Σ ICLAMP 65 mA C L level maximum output current 3 IOL1 3 5 mA When setting is 1 mA 6 7 8 IOL2 7...

Page 153: ...40o C TA 105o C 1100 mW 40o C TA 125o C Operating temperature TA 40 105 o C PD 2000 mW 40 125 o C PD 1100 mW System Thermal Resistance Theta j a1 17 o C W TEQFP 208 The minimum value depends on the system specification of heat radiation The described value is estimated under the condition which is specified at 9 1 2 Recommended operating condition Theta j a2 19 o C W TEQFP 176 Theta j a3 20 o C W ...

Page 154: ...controller The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed rated values at any time regardless of instantaneously or constantly when the B signal is input Note that when the microcontroller drive current is low such as in the low power consumption modes the B input potential can increase the potential at the VCC pin via a protec...

Page 155: ...The B signal should always be applied by connecting a limiting resistor between the B signal and the microcontroller The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed rated values at any time regardless of instantaneously or constantly when the B signal is input Do not leave B input pins open Example of a recommended circuit WARNI...

Page 156: ..._total 50 pins x 1 3 mA x 0 7 V 46 mW I_total and P_total are within allowed limits of extended specification The B signal should always be applied by connecting a limiting resistor between the B signal and the microcontroller The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed rated values at any time regardless of instantaneously ...

Page 157: ...acitor CS C 4 7 µF Tolerance of up to 40 Operating temperature TA 40 105 o C PD 2000 mW TA 40 125 o C PD 1100 mW 1 For S6J335xxSx or S6J335xxUx or S6J335xxTx or S6J335xxVx option 2 For S6J335xxBx or S6J335xxDx or S6J335xxFx or S6J335xxHx option 3 For S6J335xxAx or S6J335xxCx or S6J335xxEx or S6J335xxGx option 4 Corresponding functions for Low voltage monitoring of supply voltage are described in C...

Page 158: ...EUR Register cannot be guaranteed so these flags should not be used by software processing For the connections of smoothing capacitor CS see the following diagram C Pin Connection Diagram CS C VSS AVSS DVSS Notes The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device All of the electrical characteristics of the device are warranted whe...

Page 159: ...andard 3 One layer of middle layers at least should be used for dedicated layer to radiate heat with residual copper rate 90 or more The layer can be used for system ground 4 35 or more of the die stage area which is exposed at back surface of package should be soldered to a part of 1st layer 5 The part of 1st layer should be connected to the dedicated heat radiation layer with more than 10 therma...

Page 160: ...2 0 VCC53 0 3 V VIH4 P1_03 to P1_16 P3_08 to P3_23 P4_08 to P4_23 CMOS hysteresis input level is selected 0 7 VCC5 VCC5 0 3 V VIH5 Automotive input level is selected 0 8 VCC5 VCC5 0 3 V VIH6 P1_09 P1_10 P1_15 P1_16 TTL input level is selected 2 0 VCC5 0 3 V VIH7 P1_17 to P1_31 P2_00 to P2_08 P4_24 to P4_31 CMOS hysteresis input level is selected 0 7 DVCC DVCC 0 3 V VIH8 Automotive input level is s...

Page 161: ...C5 V VIL10 MD Vss 0 3 0 3 VCC5 V VIL11 JTAG_NTRST JTAG_TCK JTAG_TDI JTAG_TMS Vss 0 3 0 8 V VIL12 P0_21 to P0_31 P1_00 to P1_02 CMOS hysteresis input level is selected Vss 0 3 0 3 VCC3 V VIL13 P0_21 to P0_31 TTL input level is selected Vss 0 3 0 8 V Hysteresis voltage VHYS1 P0_00 to P0_20 P2_09 to P2_19 P3_00 to P3_07 P3_24 to P3_31 P4_00 to P4_07 CMOS hysteresis input level is selected 0 05 VC C53...

Page 162: ... 0 V IOH 2 0 mA VOH4 P1_03 to P1_16 P3_08 to P3_23 P4_08 to P4_23 VCC5 4 5 V IOH 1 0 mA VCC5 0 5 VCC5 V VOH5 VCC5 4 5 V IOH 2 0 mA VCC5 0 5 VCC5 V VOH6 VCC5 4 5 V IOH 5 0 mA VCC5 0 5 VCC5 V VOH7 PSC_1 VCC5 4 5 V IOH 2 0 mA VCC5 0 5 VCC5 V VOH8 JTAG_TDO VCC5 4 5 V IOH 5 0 mA VCC5 0 5 VCC5 V VOH10 P1_17 to P1_31 P2_00 to P2_08 P4_24 to P4_31 DVCC 4 5 V IOH 1 0 mA DVCC 0 5 DVCC V VOH11 DVCC 4 5 V IOH...

Page 163: ...tions Value Unit Remarks Min Typ Max H level output voltage VOH19 P2_12 VCC53 4 5 V IOH 1 0 mA VCC53 0 5 VCC53 V ODR 1 0 2b00 VOH20 VCC53 3 0 V IOH 0 5 mA VOH21 VCC53 4 5 V IOH 2 0 mA VCC53 0 5 VCC53 V ODR 1 0 2b01 VOH22 VCC53 3 0 V IOH 1 0 mA VOH23 VCC53 4 5 V IOH 5 0 mA VCC53 0 5 VCC53 V ODR 1 0 2b10 VOH24 VCC53 3 0 V IOH 2 0 mA VOH26 VCC53 3 0 V IOH 15 0 mA VCC53 0 5 Vcc53 V ODR 1 0 2b11 ...

Page 164: ...10 VCC53 3 0 V IOL 2 0 mA VOL4 P1_03 to P1_16 P3_08 to P3_23 P4_08 to P4_23 VCC5 4 5 V IOL 1 0 mA 0 0 4 V VOL5 VCC5 4 5 V IOL 2 0 mA 0 0 4 V VOL6 VCC5 4 5 V IOL 5 0 mA 0 0 4 V VOL7 PSC_1 VCC5 4 5 V IOL 2 0 mA 0 0 4 V VOL8 JTAG_TDO VCC5 4 5 V IOL 5 0 mA 0 0 4 V VOL9 P1_09 P1_10 P1_15 P1_16 VCC5 4 5 V IOL 3 0 mA 0 0 4 V I2 C VOL10 P1_17 to P1_31 P2_00 to P2_08 P4_24 to P4_31 DVCC 4 5 V IOL 1 0 mA 0 ...

Page 165: ...ymbol Pin Name Conditions Value Unit Remarks Min Typ Max L level output voltage VOL19 P2_12 VCC53 4 5 V IOL 1 0 mA 0 0 4 V ODR 1 0 2b00 VOL20 VCC53 3 0 V IOL 0 5 mA VOL21 VCC53 4 5 V IOL 2 0 mA 0 0 4 V ODR 1 0 2b01 VOL22 VCC53 3 0 V IOL 1 0 mA VOL23 VCC53 4 5 V IOL 5 0 mA 0 0 4 V ODR 1 0 2b10 VOL24 VCC53 3 0 V IOL 2 0 mA VOL26 VCC53 3 0 V IOL 15 0 mA 0 0 4 V ODR 1 0 2b11 ...

Page 166: ...0 P1_03 to P1_31 P2_00 to P2_19 P3_00 to P3_31 P4_00 to P4_31 Pull up resistor selected 25 50 100 kΩ 5 V pins 5 V 3 V pins RUP3 P0_21 to P0_31 P1_00 to P1_02 Pull up resistor selected 17 50 66 kΩ 3 V pins RUP4 JTAG_TDI JTAG_TMS JTAG_TCK 25 50 100 kΩ Pull down resistor Rdown1 P0_00 to P0_20 P1_03 to P1_31 P2_00 to P2_19 P3_00 to P3_31 P4_00 to P4_31 Pull down resistor selected 25 50 100 kΩ 5 V pins...

Page 167: ...2 Timer Stop Mode 420 mA ICC5 VCC5 Normal operation 25 45 mA Flash write erase 60 mA ICCT5 Timer mode 370 810 µA TA 25 C 4 MHz crystal for main oscillator PD1 ON PD4_0 ON PD4_1 ON 360 780 µA TA 25 C 4 MHz crystal for main oscillator PD1 ON PD4_0 ON or PD4_1 ON 350 750 µA TA 25 C 4 MHz crystal for main oscillator PD1 ON 450 890 µA TA 25 C 8 MHz crystal for main oscillator PD1 ON PD4_0 ON PD4_1 ON 4...

Page 168: ...5 VCC53 DVCC 5 0 V 10 VCC3 3 3 V 0 3 V VCC12 1 15 V 0 06 V VSS DVSS AVSS 0 0 V Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Power supply current ICCH5 VCC5 Stop mode 100 400 µA TA 25 C PD1 ON PD4_0 ON PD4_1 ON 90 370 µA TA 25 C PD1 ON PD4_0 ON or PD4_1 ON 80 340 µA TA 25 C PD1 ON ...

Page 169: ...0 µA TA 25 C 4 MHz crystal for main oscillator PD1 ON 420 705 µA TA 25 C 8 MHz crystal for main oscillator PD1 ON PD4_0 ON PD4_1 ON 415 700 µA TA 25 C 8 MHz crystal for main oscillator PD1 ON PD4_0 ON or PD4_1 ON 410 695 µA TA 25 C 8 MHz crystal for main oscillator PD1 ON 80 135 µA TA 25 C 32 kHz crystal for sub oscillator PD1 ON PD4_0 ON PD4_1 ON 75 130 µA TA 25 C 32 kHz crystal for sub oscillato...

Page 170: ...pacity Phase to phase deviation1 Delta VOH13 P1_17 to P1_31 P2_00 to P2_08 DVCC 4 5V IOH 30 0mA Maximum deviation of VOH13 90 mV High current output drive capacity Phase to phase deviation2 Delta VOL13 DVCC 4 5V IOL 30 0mA Maximum deviation of VOL13 90 mV If P1_17 to P1_20 is turned on simultaneously the maximum deviation of VOH13 VOL13 for each pin is defined Same for other channels of P1_21 to P...

Page 171: ...cked tPJ 10 10 ns Internal Slow CR oscillation frequency FCRS 50 100 150 kHz Internal Fast CR oscillation frequency FCRF 2 40 4 00 5 61 MHz Before trim 3 20 4 00 4 81 MHz After trim Notes The maximum minimum values have been standardized with the main clock and PLL clock in use Jitter of source oscillator must be smaller than 300ppm Enough evaluation and adjustment are recommended using oscillator...

Page 172: ...TA Recommended operating conditions Vcc5 5 0 V 10 VSS DVSS AVSS 0 0 V Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Source oscillation clock frequency FCL X0A X1A 32 768 kHz Source oscillation clock cycle time tLCYL X0A X1A 30 52 µs X0A and X1A clock timing X0A tLCYL ...

Page 173: ...0 240 200 180 MHz FCLK_SHE 240 200 180 MHz FCLK_FCLK 80 66 7 90 MHz FCLK_ATB 120 100 90 MHz FCLK_DBG 120 100 90 MHz FCLK_HPM 120 200 180 MHz FCLK_HPM2 60 100 90 MHz FCLK_DMA 120 200 180 MHz FCLK_MEMC 120 200 180 MHz FCLK_EXTBUS 40 40 30 MHz FCLK_SYSC1 40 40 60 MHz FCLK_HAPP0A0 40 40 30 MHz Unused FCLK_HAPP0A1 40 40 30 MHz Unused FCLK_HAPP1B0 80 50 60 MHz FCLK_HAPP1B1 40 50 30 MHz Unused FCLK_LLPBM...

Page 174: ... 7 60 MHz FCLK_SYSC0P 80 66 7 60 MHz FCLK_COMP 80 66 7 60 MHz Notes 1 Target maximum clock frequencies when CPU clock 240 MHz 2 Target maximum clock frequencies when CPU clock 200 MHz 3 Target maximum clock frequencies when CPU clock 180 MHz 4 The PLLx SSCGx cannot set under 200 MHz Note that Ta 125 condition is not supported in 1 and 2 use case Please set to 3 when device Ta 125 When using SSCG_P...

Page 175: ...ote CPU will be reset when the power supply voltage is equal to or less than LVD setting voltage 5 5 4 5 3 5 2 4 Maximum frequency of each clock Frequency MHz Power supply V CC 5 V 1 21 1 09 2 4 Maximum frequency of each clock Frequency MHz Power supply V CC 12 V Recommended guaranteed operation range Guaranteed operation range PLL guaranteed operation range ...

Page 176: ...60 120 160 240 8 4 8 16 120 240 16 8 16 32 240 Oscillation circuit example Note For the configuration of an oscillation circuit request the oscillator manufacturer to perform a circuit matching evaluation before starting design AC characteristics are specified by the following measurement reference voltage values Input signal waveform Output signal waveform Hysteresis input pin Automotive 0 5VCC5 ...

Page 177: ...6J3350 Series 9 1 4 4 Reset Input TA Recommended operating conditions Vcc5 5 0 V 10 VSS 0 0 V Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Reset input time tRSTL RSTX 10 µs Width for reset input removal 1 µs RSTX 0 2Vcc 0 2Vcc tRSTL ...

Page 178: ...be held below 1 5V for a minimum period of tOFF 3 Power ramp rate must be 1V us or less from 1 5V to 2 6V Power on can detect by satisfying power ramp rate when power off time is satisfied 4 This specification is specified the power supply fluctuation after power on detection When VCC5 voltage is between 2 4V and 4 5V the power supply fluctuation is below 50mV us the detection of power on is suppr...

Page 179: ...S 0 0 V VCC12 1 15 V 0 06 V Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Serial clock L pulse width tSLSH SCK0 to SCK4 SCK8 to SCK12 2tCLK_LCPnA 1 10 ns SCK16 to SCK17 2tCLK_COMP 10 ns Serial clock H pulse width tSHSL SCK0 to SCK4 SCK8 to SCK12 2tCLK_LCPnA 1 10 ns SCK16 to SCK17 2tCLK_COMP 10 ns SCK falling time tF SCK0 to SCK4 SCK8 to SCK12 SCK16 to SCK17 5 ns SCK rising time t...

Page 180: ... CL 20pF IOL 5mA IOH 5mA 8tCLK_LCPnA 1 ns SCK16 to SCK17 8tCLK_COMP ns SCK SOT delay time tSLOVI SCK0 SCK1 SCK2_1 SCK3_1 SCK4 SCK8 to SCK12 SCK16 to SCK17 SOT0 SOT1 SOT2_1 SOT3_1 SOT4 SOT8 to SOT12 SOT16 to SOT17 30 30 ns Valid SIN SCK setup time tIVSHI SCK0 SCK1 SCK2_1 SCK3_1 SCK4 SCK8 to SCK12 SCK16 to SCK17 SIN0 SIN1 SIN2_1 SIN3_1 SIN4 SIN8 to SIN12 SIN16 to SIN17 40 ns SCK Valid SIN hold time ...

Page 181: ...OT8 to SOT12 SOT16 to SOT17 40 ns Valid SIN SCK setup time tIVSHE SCK0 to SCK4 SCK8 to SCK12 SCK16 to SCK17 SIN0 to SIN4 SIN8 to SIN12 SIN16 to SIN17 10 ns SCK Valid SIN hold time tSHIXE 10 ns SCK falling time tF SCK0 to SCK4 SCK8 to SCK12 SCK16 to SCK17 5 ns SCK rising time tR SCK0 to SCK4 SCK8 to SCK12 SCK16 to SCK17 5 ns 1 n 0 ch 0 to ch 4 n 1 ch 8 to ch 12 Notes This table provides the alterna...

Page 182: ... Rev J Page 181 of 307 S6J3350 Series Master mode tSCYC VOL tSLOVI tIVSHI tSHIXI VIH VIL VOH VOL SCK SOT SIN VIH VIL VOH Slave mode tSLSH VIL tSLOVE tIVSHE tSHIXE VIH VIL VOH VOL SCK SOT SIN VIH VIL tF VIH VIL VIH tSHSL tR VIH ...

Page 183: ...nditions Value Unit Remarks Min Max Serial clock cycle time tSCYC SCK0 SCK1 SCK2_1 SCK3_1 SCK4 SCK8 to SCK12 Master Mode CL 20pF IOL 5mA IOH 5mA 8tCLK_LCPnA 1 ns SCK16 to SCK17 8tCLK_COMP ns SCK SOT delay time tSHOVI SCK0 SCK1 SCK2_1 SCK3_1 SCK4 SCK8 to SCK12 SCK16 to SCK17 SOT0 SOT1 SOT2_1 SOT3_1 SOT4 SOT8 to SOT12 SOT16 to SOT17 30 30 ns Valid SIN SCK setup time tIVSLI SCK0 SCK1 SCK2_1 SCK3_1 SC...

Page 184: ...CK12 4tCLK_LCPnA 1 ns SCK16 to SCK17 4tCLK_COMP ns SCK SOT delay time tSHOVE SCK0 to SCK4 SCK8 to SCK12 SCK16 to SCK17 SOT0 to SOT4 SOT8 to SOT12 SOT16 to SOT17 40 ns Valid SIN SCK setup time tIVSLE SCK0 to SCK4 SCK8 to SCK12 SCK16 to SCK17 SIN0 to SIN4 SIN8 to SIN12 SIN16 to SIN17 10 ns SCK Valid SIN hold time tSLIXE 10 ns SCK falling time tF SCK0 to SCK4 SCK8 to SCK12 SCK16 to SCK17 5 ns SCK ris...

Page 185: ... Rev J Page 184 of 307 S6J3350 Series Master mode tSCYC VOH tSHOVI tIVSLI tSLIXI VIH VIL VOH VOL SCK SOT SIN VIH VIL VOL Slave mode tSHSL VIL tSHOVE tIVSLE tSLIXE VIH VIL VOH VOL SCK SOT SIN VIH VIL tR VIH VIL VIH tSLSH tF VIL ...

Page 186: ...1 SOT2_1 SOT3_1 SOT4 SOT8 to SOT12 SOT16 to SOT17 30 30 ns Valid SIN SCK setup time tIVSLI SCK0 SCK1 SCK2_1 SCK3_1 SCK4 SCK8 to SCK12 SCK16 to SCK17 SIN0 SIN1 SIN2_1 SIN3_1 SIN4 SIN8 to SIN12 SIN16 to SIN17 40 ns SCK Valid SIN hold time tSLIXI 0 ns SOT SCK delay time tSOVLI SCK0 SCK1 SCK2_1 SCK3_1 SCK4 SCK8 to SCK12 SCK16 to SCK17 SOT0 SOT1 SOT2_1 SOT3_1 SOT4 SOT8 to SOT12 SOT16 to SOT17 4tCLK_LCP...

Page 187: ...etup time tIVSLE SCK0 to SCK4 SCK8 to SCK12 SCK16 to SCK17 SIN0 to SIN4 SIN8 to SIN12 SIN16 to SIN17 10 ns SCK Valid SIN hold time tSLIXE 10 ns SCK falling time tF SCK0 to SCK4 SCK8 to SCK12 SCK16 to SCK17 5 ns SCK rising time tR SCK0 to SCK4 SCK8 to SCK12 SCK16 to SCK17 5 ns 1 n 0 ch 0 to ch 4 n 1 ch 8 to ch 12 Notes This table provides the alternate current standard for CLK synchronous mode CL i...

Page 188: ...umber 002 10634 Rev J Page 187 of 307 S6J3350 Series Slave mode tSLSH VIL tF tSLIXE VIH VIL VOH VOL SCK SOT SIN VIH VIL VIH VOH VOL tIVSLE tSHOVE VIL VIH VIH VIL tSHSL tR Changes when writing to the TDR register ...

Page 189: ...T1 SOT2_1 SOT3_1 SOT4 SOT8 to SOT12 SOT16 to SOT17 30 30 ns Valid SIN SCK setup time tIVSHI SCK0 SCK1 SCK2_1 SCK3_1 SCK4 SCK8 to SCK12 SCK16 to SCK17 SIN0 SIN1 SIN2_1 SIN3_1 SIN4 SIN8 to SIN12 SIN16 to SIN17 40 ns SCK Valid SIN hold time tSHIXI 0 ns SOT SCK delay time tSOVHI SCK0 SCK1 SCK2_1 SCK3_1 SCK4 SCK8 to SCK12 SCK16 to SCK17 SOT0 SOT1 SOT2_1 SOT3_1 SOT4 SOT8 to SOT12 SOT16 to SOT17 4tCLK_LC...

Page 190: ...up time tIVSHE SCK0 to SCK4 SCK8 to SCK12 SCK16 to SCK17 SIN0 to SIN4 SIN8 to SIN12 SIN16 to SIN17 10 ns SCK Valid SIN hold time tSHIXE 10 ns SCK falling time tF SCK0 to SCK4 SCK8 to SCK12 SCK16 to SCK17 5 ns SCK rising time tR SCK0 to SCK4 SCK8 to SCK12 SCK16 to SCK17 5 ns 1 n 0 ch 0 to ch 4 n 1 ch 8 to ch 12 Notes This table provides the alternate current standard for CLK synchronous mode CL is ...

Page 191: ...umber 002 10634 Rev J Page 190 of 307 S6J3350 Series Slave mode tSHSL VIL tR tSHIXE VIH VIL VOH VOL SCK SOT SIN VIH VIL VIH VOH VOL tIVSHE tSLOV E VIL VIH VIH VIL tSLSH tF Changes when writing to the TDR register ...

Page 192: ...x SCS1x SCS2x_1 SCS3x_1 SCS4 SCS8x to SCS12x tCSDS 3 15 5tCLK_LCPnA 4 ns SCS16x to SCS17x tCSDS 3 15 5tCLK_COMP ns SCS SCK setup time tCSSI SCK2_0 SCK3_0 SCS2x_0 SCS3x_0 Master Mode CL 20pF IOL 10mA IOH 10mA tCSSU 1 10 ns SCK SCS hold time tCSHI tCSHD 2 0 ns SCS deselect time tCSDI SCS2x_0 SCS3x_0 tCSDS 3 10 5tCLK_LCPnA 4 ns SCS SCK setup time tCSSE SCK0 to SCK4 SCK8 to SCK12 SCS0x to SCS4x SCS8x ...

Page 193: ...4 10 ns 1 tCSSU SCSTR CSSU 7 0 x serial chip select timing operating clock 2 tCSHD SCSTR CSHD 7 0 x serial chip select timing operating clock 3 tCSDS SCSTR CSDS 15 0 x serial chip select timing operating clock For details on 1 2 and 3 above see the Traveo Platform Hardware Manual 4 tCLK_LCPnA n 0 ch 0 to ch 4 n 1 ch 8 to ch 12 Notes This is the AC characteristic in CLK synchronized mode CL is the ...

Page 194: ...CK input SOT Normal synchronous transfer SOT SPI compatible tCSSE SCS input tCSHE tCSDE tDSE tDEE VIL VIL VIH VIH VIL VIH VOL VOL VOH Clock switching example by master mode round operation x y 0 1 2 3 x and y are different value SCSy output SCK output SCSx output tSCC VOL VOL ...

Page 195: ...0x SCS1x SCS2x_1 SCS3x_1 SCS4 SCS8x to SCS12x tCSDS 3 15 5tCLK_LCPnA 4 ns SCS16x to SCS17x tCSDS 3 15 5tCLK_COMP ns SCS SCK setup time tCSSI SCK2_0 SCK3_0 SCS2x_0 SCS3x_0 Master Mode CL 20pF IOL 10mA IOH 10mA tCSSU 1 10 ns SCK SCS hold time tCSHI tCSHD 2 0 ns SCS deselect time tCSDI SCS2x_0 SCS3x_0 tCSDS 3 10 5tCLK_LCPnA 4 ns SCS SCK setup time tCSSE SCK0 to SCK4 SCK8 to SCK12 SCS0x to SCS4x SCS8x...

Page 196: ...4 10 ns 1 tCSSU SCSTR CSSU 7 0 x serial chip select timing operating clock 2 tCSHD SCSTR CSHD 7 0 x serial chip select timing operating clock 3 tCSDS SCSTR CSDS 15 0 x serial chip select timing operating clock For details on 1 2 and 3 above see the Traveo Platform Hardware Manual 4 tCLK_LCPnA n 0 ch 0 to ch 4 n 1 ch 8 to ch 12 Notes This is the AC characteristic in CLK synchronized mode CL is the ...

Page 197: ...CK input SOT Normal synchronous transfer SOT SPI compatible tCSSE SCS input tCSHE tCSDE tDSE tDEE VIL VIL VIH VIH VIH VIL VOL VOL VOH Clock switching example by master mode round operation x y 0 1 2 3 x and y are different value SCSy output SCK output SCSx output tSCC VOL VOH ...

Page 198: ...S0x SCS1x SCS2x_1 SCS3x_1 SCS4 SCS8x to SCS12x tCSDS 3 15 5tCLK_LCPnA 4 ns SCS16x to SCS17x tCSDS 3 15 5tCLK_COMP ns SCS SCK setup time tCSSI SCK2_0 SCK3_0 SCS2x_0 SCS3x_0 Master Mode CL 20pF IOL 10mA IOH 10mA tCSSU 1 10 ns SCK SCS hold time tCSHI tCSHD 2 0 ns SCS deselect time tCSDI SCS2x_0 SCS3x_0 tCSDS 3 10 5tCLK_LCPnA 4 ns SCS SCK setup time tCSSE SCK0 to SCK4 SCK8 to SCK12 SCS0x to SCS4x SCS8...

Page 199: ...A 4 10 ns 1 tCSSU SCSTR CSSU 7 0 x serial chip select timing operating clock 2 tCSHD SCSTR CSHD 7 0 x serial chip select timing operating clock 3 tCSDS SCSTR CSDS 15 0 x serial chip select timing operating clock For details on 1 2 and 3 above see the Traveo Platform Hardware Manual 4 tCLK_LCPnA n 0 ch 0 to ch 4 n 1 ch 8 to ch 12 Notes This is the AC characteristic in CLK synchronized mode CL is th...

Page 200: ... SCK input SOT Normal synchronous transfer SOT SPI compatible tCSSE SCS input tCSHE tCSDE tDSE tDEE VIH VIH VIL VIH VIL Clock switching example by master mode round operation x y 0 1 2 3 x and y are different value SCSy output SCK output SCSx output tSCC VOL VOH VOL VOL VOH ...

Page 201: ...x SCS1x SCS2x_1 SCS3x_1 SCS4 SCS8x to SCS12x tCSDS 3 15 5tCLK_LCPnA 4 ns SCS16x to SCS17x tCSDS 3 15 5tCLK_COMP ns SCS SCK setup time tCSSI SCK2_0 SCK3_0 SCS2x_0 SCS3x_0 Master Mode CL 20pF IOL 10mA IOH 10mA tCSSU 1 10 ns SCK SCS hold time tCSHI tCSHD 2 0 ns SCS deselect time tCSDI SCS2x_0 SCS3x_0 tCSDS 3 10 5tCLK_LCPnA 4 ns SCS SCK setup time tCSSE SCK0 to SCK4 SCK8 to SCK12 SCS0x to SCS4x SCS8x ...

Page 202: ...peration CL 20pF IOL 10mA IOH 10mA 4tCLK_LCPnA 4 0 4tCLK_LCPnA 4 10 ns 1 tCSSU SCSTR CSSU 7 0 x serial chip select timing operating clock 2 tCSHD SCSTR CSHD 7 0 x serial chip select timing operating clock 3 tCSDS SCSTR CSDS 15 0 x serial chip select timing operating clock For details on 1 2 and 3 above see the Traveo Platform Hardware Manual 4 tCLK_LCPnA n 0 ch 0 to ch 4 n 1 ch 8 to ch 12 Notes Th...

Page 203: ...ible tCSSI SCS output tCSHI tCSDI VOH VOH VOL VOL VOH VIH Slave mode SCK input SOT Normal synchronous transfer SOT SPI compatible tCSSE SCS input tCSHE tCSDE tDSE tDEE VIH VIL VIL VOL VOL VOH Clock switching example by master mode round operation x y 0 1 2 3 x and y are different value SCSy output SCK output SCSx output tSCC VOH VOH ...

Page 204: ...0 V VCC12 1 15 V 0 06 V Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Serial clock L pulse width tSLSH SCK0 to SCK4 SCK8 to SCK12 tCLK_LCPnA 1 10 ns SCK16 to SCK17 tCLK_COMP 10 ns Serial clock H pulse width tSHSL SCK0 to SCK4 SCK8 to SCK12 tCLK_LCPnA 1 10 ns SCK16 to SCK17 tCLK_COMP 10 ns SCK falling time tF SCK0 to SCK4 SCK8 to SCK12 SCK16 to SCK17 5 ns SCK rising time tR 5 ns 1...

Page 205: ...time SCL SDA tHDDAT 0 3 45 2 0 0 9 3 µs Data setup time SDA SCL tSUDAT 250 100 ns Stop condition setup time SCL SDA tSUSTO 4 0 0 6 µs Bus free time between stop condition and start condition tBUF 4 7 1 3 µs Noise filter tSP tNFT 4 tNFT 4 ns Notes Only ch 16 and ch 17 are standard mode high speed mode correspondence In ch 0 ch 1 ch 4 and ch 8 to ch 12 only a standard mode is correspondence 1 R and ...

Page 206: ...Document Number 002 10634 Rev J Page 205 of 307 S6J3350 Series SDA SCL tHDSTA tLOW tHDDAT tSUDAT tHIGH tSUSTA tHDSTA tSP tBUF tSUSTO ...

Page 207: ...CU0_IN1 to ICU2_IN1 ICU8_IN1 to ICU10_IN1 4tCLK_LCPnA 2 ns 4tCLK_LCPnA 2 100 ns 100 4tCLK_LCPnA 2 100 ns FRT0_TEXT to FRT4_TEXT FRT8_TEXT to FRT10_TEXT 4tCLK_LCPnA 3 ns 4tCLK_LCPnA 3 100 ns 100 4tCLK_LCPnA 3 100 ns TIN0 to TIN1 TIN16 to TIN17 4tCLK_LCPnA 4 ns 4tCLK_LCPnA 4 100 ns 100 4tCLK_LCPnA 4 100 ns TIN48 to TIN49 4tCLK_COMP ns 4tCLK_COMP 100 ns 100 4tCLK_COMP 100 ns 1 n 0 unit 0 to unit 5 un...

Page 208: ...pin L level to BIN fall tADBD AIN8 to AIN9 BIN8 to BIN9 PC_Mode2 or PC_Mode3 Time from BIN pin L level to AIN rise tBDAU AIN8 to AIN9 BIN8 to BIN9 PC_Mode2 or PC_Mode3 Time from BIN pin H level to AIN rise tBUAU AIN8 to AIN9 BIN8 to BIN9 PC_Mode2 or PC_Mode3 Time from AIN pin H level to BIN fall tAUBD AIN8 to AIN9 BIN8 to BIN9 PC_Mode2 or PC_Mode3 Time from BIN pin L level to AIN fall tBDAD AIN8 t...

Page 209: ...Document Number 002 10634 Rev J Page 208 of 307 S6J3350 Series AIN BIN tAUBU tBUAD tADBD tBDAU tAHL tALL tBHL tBLL BIN tBUAU tAUBD tBDAD tADBU tBHL tBLL tAHL tALL AIN ...

Page 210: ...Document Number 002 10634 Rev J Page 209 of 307 S6J3350 Series ZIN AIN BIN ZIN ...

Page 211: ...0 V 10 Vcc53 5 0 V 10 3 3 V 0 3 V VSS DVSS 0 0 V VCC12 1 15V 0 06 V Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input pulse width tTRGH tTRGL EINT0 to EINT23 100 ns ADTRG0 to ADTRG1 5tCLK_LCP1A ns 5tCLK_LCP1A 100 ns 100 5tCLK_LCP1A 100 ns EINT0 to EINT23 1 µs Stop mode Trigger input timing VIH VIL EINTx tTRGL tTRGH VIH VIL ADTRGx ...

Page 212: ...f 307 S6J3350 Series 9 1 4 10 NMI Input TA Recommended operating conditions Vcc5 5 0 V 10 VSS 0 0 V Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input pulse width tNMIL NMIX 300 ns NMIX input timing VIH NMIX tNMIL VIH VIL VIL ...

Page 213: ...supply voltage has exceeded the detection voltage range 2 Please suppress the change of the power supply within the range of the power supply voltage regulation to do a low voltage detection by detecting voltage VDL 3 For S6J335xxSx or S6J335xxUx or S6J335xxTx or S6J335xxVx option 4 For S6J335xxAx or S6J335xxBx or S6J335xxCx or S6J335xxDx or S6J335xxEx or S6J335xxFx or S6J335xxGx or S6J335xxHx opt...

Page 214: ...ly voltage rises Low voltage detection time TRd 30 μs 1 If the power fluctuation time is less than the low voltage detection time TRd and has passed the detection voltage range the detection may occur or be canceled after the supply voltage has passed the detection voltage range 2 These LVD settings cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operat...

Page 215: ...L0 channel is potentially below supply range defined in 9 1 2 Recommended operating condition Low voltage detection internal low voltage detection for LVDL1 TA Recommended operating conditions VSS AVSS 0 0 V Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Supply voltage range VRDP5 1 05 1 21 V Detection voltage before trimming VRDLBT 1 2 0 775 0 875 0 975 V When power supply vo...

Page 216: ...ded operating conditions VCC5 VCC53 DVCC 5 0 V 10 VCC3 3 3 V 0 3 V VCC12 1 15 V 0 06 V VSS DVSS AVSS 0 0 V Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Output rise fall time tR2 tF2 P1_17 to P1_31 P2_00 to P2_08 15 100 ns Load capacitance 85pF VH VOL8 0 9 x VOH8 VOL8 VL VOL8 0 1 x VOH8 VOL8 ...

Page 217: ...ise dH is calculated as the following dH The number rounding division ratio x 0 5 down to the nearest integer division ratio division ratio is multiplication value among SYSDIV bit HPMDIV bit and EXTBUSDIV bit setting ex Setting SYSDIV to 1 division HPMDIV to 7 division EXTBUSDIV to 1 division dH is calculated as 0 429 2 If division ratio is even value dL is equivalent to 0 5 Otherwise dL is calcu...

Page 218: ...without MRDY tCYC MCLK 2mA is selected in ODR bit in PPC_PCFGR register 62 5 ns Cycle time with MRDY tCYC MCLK 62 5 ns If using MRDY set MCLK to 20 MHz or less CS delay time tCSO MCLK MCSX0 to MCSX3 0 5 18 ns Address delay time tAO MCLK MAD00 to MAD23 0 5 18 ns RDY setup time tRDYS MCLK MRDY CMOS Schmitt input and Disable noise filter are selected in PPC_PCFGR register 21 ns RDY hold time tRDYH MC...

Page 219: ...ymbol Pin Name Conditions Value Unit Remarks Min Max Data setup time tDSR MOEX MDATA00 to MDATA15 CMOS Schmitt input and Disable noise filter are selected in PPC_PCFGR register 21 tcyc ns Data hold time tDHR MOEX MDATA00 to MDATA15 0 ns MOEX delay time tRDO MCLK MOEX 2mA is selected in ODR bit in PPC_PCFGR register 0 5 18 ns Notes This is Target Spec External bus I F read timing ...

Page 220: ...ter Symbol Pin Name Conditions Value Unit Remarks Min Max MWEX delay time tWEO MCLK MWEX 2mA is selected in ODR bit in PPC_PCFGR register 0 5 18 ns Byte mask delay time tWRO MCLK MDQM0 to MDQM1 0 5 18 ns Data delay time tDO MCLK MDATA00 to MDATA15 0 5 18 ns Data delay time Hi Z output tDOZ MCLK MDATA00 to MDATA15 18 ns Notes This is Target Spec External bus I F write timing ...

Page 221: ... 31 5 ns M_SDATA M_SLCK Input setup time tisdata M_SDATA0_0 3 M_SDATA1_0 3 1 ns M_SCLK M_SDATA Input hold time tihdata M_SDATA0_0 3 M_SDATA1_0 3 1 ns M_SCLK M_SDATA Output delay time toddata M_SDATA0_0 3 M_SDATA1_0 3 tcyc 2 2 ns M_SCLK M_SDATA Output hold time tohdata M_SDATA0_0 3 M_SDATA1_0 3 tcyc 2 3 ns M_SCLK M_SSEL Output delay time todsel M_SSEL0 1 12 00 SS2 CD 0 5 tcyc ns M_SCLK M_SSEL Outpu...

Page 222: ...SDATA1_0 3 input timing VOH VOH VIH VIL valid tisdata delayed sample clock tihdata VOH tspcnt VOH VOL G_SDATA0_0 3 G_SDATA1_0 3 output timing VOH VOL valid toddata tohdata VOH VOL GSSEL0 1 output timing VOH VOL valid todsel tohsel M_SDATA0_0 3 M_SDATA1_0 3 M_SDATA0_0 3 M_SDATA1_0 3 M_SCLK0 M_SSEL0 1 ...

Page 223: ...put setup time tisdata M_SDATA0_0 3 M_SDATA1_0 3 1 ns M_SLCK M_SDATA Input hold time tihdata M_SDATA0_0 3 M_SDATA1_0 3 1 ns M_SCLK M_SDATA Output delay time toddata M_SDATA0_0 3 M_SDATA1_0 3 tcyc 4 1 5 ns M_SCLK M_SDATA Output hold time tohdata M_SDATA0_0 3 M_SDATA1_0 3 Tcyc 4 1 0 ns M_SCLK M_SSEL Output delay time todsel M_SSEL0 1 15 75 SS2CD 0 5 tcyc ns M_SCLK M_SSEL Output hold time tohsel M_SS...

Page 224: ...LK0 G_SDATA0_0 3 G_SDATA1_0 3 input timing VOH VOH VIH VIL valid tisdata delayed sample clock tihdata VOH tspcnt G_SDATA0_0 3 G_SDATA1_0 3 output timing valid toddata GSSEL0 1 output timing valid todsel tohsel valid VOL tohdata toddata tohdata M_SDATA0_0 3 M_SDATA1_0 3 M_SDATA0_0 3 M_SDATA1_0 3 M_SCLK0 M_SSEL0 1 ...

Page 225: ...cle tCKCYC M_CK CL 20pF IOL 10mA IOH 10mA 10 0 ns CS CK Chip Select setup time tCSS M_CS _1 2 tCKCYC 2 0 ns DQ CK Input setup time tIS M_DQ7 0 1 25 ns CK DQ Input hold time tIH M_DQ7 0 1 25 ns CK CS Chip select hold time tCSH M_CS _1 2 tCKCYC 2 ns Notes This is Target Spec VIH VOH tCSS VOL VIL CA0 47 40 CA0 39 32 CA1 31 24 CA1 23 16 CA2 15 8 CA2 7 0 Dn 15 8 Dn 7 0 VOL tDSV tCSHI tIS tDSZ VOH tCSS ...

Page 226: ... 2 0 ns DQ CK Input setup time tIS M_DQ7 0 1 25 ns CK DQ Input hold time tIH M_DQ7 0 1 25 ns CK CS Chip select hold time tCSH M_CS _1 2 tCKCYC 2 ns RWDS CK Data Mask Valid tDMV M_RWDS 1 ns CK RWDS Refresh Indicator Valid tRIV M_RWDS 6 ns CK RWDS Hi z Refresh Indicator Hold tRIH M_RWDS 0 ns Notes This is Target Spec VIH VOH tCSS VIL VIL CA0 47 40 CA0 39 32 CA1 31 24 CA1 23 16 CA2 15 8 CA2 7 0 Dn 15...

Page 227: ...time tCSS M_CS _1 2 tRDSCYC 2 0 ns DQ CK Setup time tIS M_DQ7 0 1 25 ns CK DQ Hold time tIH M_DQ7 0 1 25 ns CK CS Chip select hold time tCSH M_CS _1 2 tRDSCYC 2 ns RDS DQ Setup time tDSS M_DQ7 0 0 8 ns RDS DQ Hold time tDSH M_DQ7 0 0 8 ns Notes This is Target Spec VIH G_CK M_CK VOH tCSS VOL VIL G_RWDS M_RWDS G_DQ7 0 M_DQ7 0 CA0 47 40 CA0 39 32 CA1 31 24 CA1 23 16 CA2 15 8 CA2 7 0 Dn 15 8 Dn 7 0 VO...

Page 228: ...5 ns CK DQ Hold time tIH M_DQ7 0 1 25 ns CK CS Chip select hold time tCSH M_CS _1 2 tRDSCYC 2 ns RWDS DQ valid Setup time tDSS M_DQ7 0 0 8 ns RWDS DQ invalid Hold time tDSH M_DQ7 0 0 8 ns CK RWDS Refresh Indicator Valid tRIV M_RWDS 6 ns CK RWDS Hi z Refresh Indicator Hold tRIH M_RWDS 0 ns Notes This is Target Spec VIH VOH tCSS VOL VIL CA0 47 40 CA0 39 32 CA1 31 24 CA1 23 16 CA2 15 8 CA2 7 0 Dn 15 ...

Page 229: ...g conditions Vcc53 Vcc3 3 3 V 0 3 V VSS DVSS AVSS 0 0 V Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max RXCLK cycle tRXCYC RXCLK 40 0 ns RX setup time tRXS RXER RXDV RXD0 3 10 0 ns tRXCYC 30ns RX hold time tRXH RXER RXDV RXD0 3 0 ns Notes This is Target Spec tRXCYC RXCLK VIH VIH valid VIH VIL tRXS tRXH RXER RXDV RXD0 3 ...

Page 230: ...ymbol Pin Name Conditions Value Unit Remarks Min Max TXCLK cycle tTXCYC TXCLK CL 20pF IOL 5mA IOH 5mA 40 0 ns COL CRS input setup time tCRXS COL CRS 12 0 ns COL CRS input hold time tCRXH COL CRS 0 5 ns Tx delay time tTXD TXER TXEN TXD0 3 0 5 25 ns Notes This is Target Spec tTXCYC TXCLK valid tCRXS tCRXH COL CRS valid VOH VOL TXER TXDV TXD0 3 tTXD tTXD VIH VIH VIH VIH VIH VIL TXEN ...

Page 231: ...er Symbol Pin Name Conditions Value Unit Remarks Min Max MDC cycle tMDCYC MDC CL 20pF IOL 5mA IOH 5mA 400 0 ns MDIO input setup time tMDIS MDIO 100 0 ns MDIO input hold time tMDIH MDIO 0 0 ns MDIO output delay time tMDOD MDIO 10 0 190 0 ns Notes This is Target Spec tMDCYC MDC VOH VOH VOH VOL valid VIH VIL tMDIS tMDIH MDIO in valid VOH VOL tMDOD tMDOD MDIO out VOH ...

Page 232: ...se Filter TA Recommended operating conditions VCC5 VCC53 DVCC5 5 0 V 10 VSS DVSS AVSS 0 0 V Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Width for input removal ALL GPIO 17 ns Input pulse width less than at least 17nm is removed when Port noise filter is enabled ...

Page 233: ...er on tRV12 VCC12 14 2 ms Note VDLAT VRDLAT VRDLBT and VRHYS are referred to 9 1 4 11 Low Voltage Detection External Voltage VOH7 is referred to 9 1 3 DC Characteristics LVDH1 reset need to be always enable For details see the Traveo Platform Hardware Manual The above sequence needs not to be applied in the following cases the application enters PSS mode VCC12 is controlled by PSC_1 at entry and e...

Page 234: ...12RST and tRV12RST are referred to 9 1 4 19 Power and Reset Sequence 1 Battery Disconnect All supplies fall together 2 VCC12 can be fully depleted or not full depleted 3 DVCC VCC53 and VCC3 can start before or after VCC12 4 VCC5 is higher than level detection voltage VDLAT VHYS VCC5 is lower than level detection voltage VDLBT VHYS VDLAT VDLBT and VHYS are referred to 9 1 4 11 Low Voltage Detection...

Page 235: ...50 Series Note VCC12 controlled by PSC_1 VCC12 can be fully deplete Case2 1 PSC_1 H L H transition by User Program VCC12 RSTX VCC5 PSC_1 No timing specification of VCC12 and RSTX VCC5 VDLAT VRDLAT VRHYS VRDLAT Transition PSC_1 L VCC12 OFF VCC12 ON PSC_1 H ...

Page 236: ... 307 S6J3350 Series Note VCC12 and AVCC5 controlled by PSC_1 VCC53 VCC3 AVCC3_DAC and DVCC controlled by PSC_1 Can be controlled by VCC5 GPIO also 1 VCC12 can be fully depleted or not full depleted Case2 2 PSC_1 H L H transition by User Program ...

Page 237: ... Note If the sequence given in VCC5 and VCC12 sequence cannot be applied this sequence can be applied VDLAT VRDLAT VRDLAT and VRHYS are referred to 9 1 4 11 Low Voltage Detection External Voltage VIL9 and VIH9 is referred to 9 1 3 DC Characteristics This sequence is applied in case of VCC12 power on off and assertion of RSTX is controlled by application This sequence is applied under the condition...

Page 238: ...equence cannot be applied this sequence can be applied Connect RSTX signal and MODE signal outside of the MCU and shorten the trace length between MCU and these two signal lines The following assumptions are made with regard to the workaround described above 1 After the reset the MCU state is equivalent to the cold start state usually reached by power on reset 2 Debugger interface and PC writer in...

Page 239: ...ut current IAIN AN0 to AN30 AN32 to AN38 1 0 1 0 µA AVSS VAIN AVCC5 AN31 AN39 to AN63 2 0 2 0 µA Analog input voltage VAIN AN0 to AN63 AVRL AVRH V Reference voltage AVRH AVRH5 4 5 6 5 5 6 V AVcc5 AVRH 3 0 7 3 6 7 AVRL AVRL5 AVSS 0 0 V Power supply current IA AVCC5 500 900 Target µA 1unit IAH 1 0 200 Target µA 2 IR AVRH5 1 0 3 5 Target 6 mA 1unit 1 0 2 5 Target 7 mA 1unit IRH 9 0 Target µA 2 Variat...

Page 240: ... the external impedance is too high the analog voltage sampling time may become insufficient In this case we recommend attaching a capacitor about 0 1 µF to an analog input pin Analog input circuit model R C 12 bit A D 3 9 kiloohms max 11 0 pF max 4 5 V AVCC5 5 5 V Note Use the numerical values provided here simply as a guide R C Sampling ON Comparator Analog input ...

Page 241: ...Deviation from the ideal value of the input voltage required for changing the output code by 1 LSB Total error Difference between the actual value and the theoretical value The total error Total error Total error of digital output N VNT 1 LSB N 1 0 5LSB LSB 1LSB 1LSB Ideal value AVRH AVRL V 4096 N A D converter digital output value VZT Ideal value AVRL 0 5LSB V VFST Ideal value AVRH 1 5LSB V VNT V...

Page 242: ...t changes from 0x000 to 0x001 VFST Voltage for which digital output changes from 0xFFE to 0xFFF FFF FFE FFD 004 003 002 001 AVRL AVRH AVRH Actual conversion characteristics 1 LSB N 1 VZT N 1 AVRL N 2 N N 1 VFST VNT VZT V N 1 T VNT Ideal characteristics Actual conversion characteristics Actual conversion characteristics Actual conversion characteristics Ideal characteristics Digital output measured...

Page 243: ...vel overhead time excluded 2 Erase count Data retention time Program 1 000 20 years Temperature at write erase time Average temperature TA 85 degrees Celsius Erase count Data retention time Work 1 000 20 years 10 000 10 years 100 000 5 years Temperature at write erase time Average temperature TA 85 degrees Celsius 1 Guaranteed value for up to 1 000 erases 2 Guaranteed value for up to 100 000 erase...

Page 244: ... Inter processor communication unit IRC Interrupt controller IRQ Interrupt request ISR Interrupt service routine JTAG Joint test action group Acronym Description LLPP Low latency peripheral port LVD Low voltage detector MCU Microcontroller unit MFS Multi function serial interface NF Noise filter NMI Non maskable interrupt OCU Output compare unit OSC Oscillator PCM Pulse coded module PLL Phase lock...

Page 245: ...2 10634 Rev J Page 244 of 307 S6J3350 Series 11 Ordering Information Part Number 1 Package S6J335EKSCSE2000A 208 pin plastic TEQFP LEW208 S6J335EKSESE20000 S6J335EKBESE20000 S6J335EJBESE20000 176 pin plastic TEQFP LEV176 ...

Page 246: ...n a transmission request for sending a message and the coincidence of noise in the 3rd bit of intermission field which is treated as the start of new message transmission SoF Trigger Condition Under the following conditions a message with wrong ID format and DLC is transmitted M_CAN is in state Receiver PSR ACT 10 no pending transmission A new transmission is requested after sample point of 2nd bi...

Page 247: ... data field of the message to be transmitted to detect frames transmitted with wrong arbitration and control fields Workaround 2 This workaround ensures that always at least one pending Tx request exists If that is the case the application may launch its Tx requests at any time without suffering from the limitation Define a low priority message with DLC 0 that can be sent without harm E g loses ar...

Page 248: ...mber 002 10634 Rev J Page 247 of 307 S6J3350 Series 13 Appendix 13 1 Application 1 JTAG Tool Connection This is an application example of JTAG tool connection See the relevant application note 002 03898 in detail ...

Page 249: ...ge of 3 6 16 MHz is available for main oscillator 13 3 Product Description 3 2 Product description Added Note of a function as below Multi Functional Serial MFS Correct CTS RTS is not mounted hardware flow control is not supported for this series 16 30 32 38 4 1 Pin Assignment 4 1 2 TEQFP 176 Pin Assignment P32 P38 6 Port Description 6 1 Port description list Deleted 176Pin Function as below Error...

Page 250: ...DVCC VCC5 Correct Power supply voltage DVCC Remarks 165 8 2Handling Devices Added Note of a function as below Method to Switch off VCC12 during Power off Sequence During power off sequence it is necessary to switch off VCC12 by driving PSC1 pin low by entering PSS mode power domain 2 off If VCC12 needs to be switched off by other means RSTX needs to be asserted before switching off VCC12 to inacti...

Page 251: ... power source becomes unstable status In that case the value of each registers including RESCAUSEUR Register cannot be guaranteed so these flags should don t care by software processing 168 169 221 241 9 Electric Characteristics 9 1 2Recommended operating condition 9 1 4 11Low Voltage Detection External Voltage 9 1 5 A D converter Revised device revision from B to C as below Error S6J335xxSB S6J33...

Page 252: ... Typ Max Power off time VCC5 50 ms 2 Power ramp rate dV dt VCC5 VCC5 0 2V to 2 6V 1 V µs 3 Undetected power ramp rate dV dt VCC5 VCC5 Between 2 4V and 4 5V 50 mV µs 4 Correct Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Power off time VCC5 100 μs 2 Power ramp rate dV dt VCC5 VCC5 1 5V to 2 6V 1 V µs 3 Maximum ramp rate guaranteed to not generate power on reset dV dt VCC5 VCC...

Page 253: ...nd 3 must be satisfied When neither 2 nor 3 can be satisfied assert external reset RSTX at power up and any brownout event Power off time Power ramp rate VCC tOFF 0 2V 0 2V dV dt 2 6V Correct 1 This specification is at 1V μs of power ramp rate 2 VCC5 must be held below 1 5V for a minimum period of tOFF 3 Power ramp rate must be 1V us or less from 1 5V to 2 6V Power on can detect by satisfying powe...

Page 254: ...tage after trimming VRDLAT VCC12 1 0 784 0 8125 0 841 V When power supply voltage falls Typ 3 5 0 888 0 95 0 984 Correct Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Detection voltage after trimming VRDLAT VCC12 1 0 7841 0 8125 0 8410 V When power supply voltage falls Typ 3 5 223 9 Electric Characteristics 9 1 4 12Low Voltage Detection Internal Voltage Revised as below Low v...

Page 255: ...supply voltage has passed the detection voltage range Correct Parameter Symbol Pin Name Conditions Value Unit Min Typ Max Supply voltage range VRDP5 1 05 1 21 V Detection voltage VRDL 1 0 75 0 85 0 95 V Hysteresis width VRHYS 75 mV Low voltage detection time TRd 30 μs 1 If the power fluctuation time is less than the low voltage detection time TRd and has passed the detection voltage range the dete...

Page 256: ...on voltage range Correct Parameter Symbol Pin Name Conditions Value Unit Min Typ Max Supply voltage range VRDP5 1 05 1 21 V Detection voltage before trimming VRDLBT 1 0 775 0 875 0 975 V Detection voltage after trimming VRDLAT 1 0 844 0 875 0 906 V Hysteresis width VRHYS 75 mV Low voltage detection time TRd 30 μs 1 If the power fluctuation time is less than the low voltage detection time TRd and h...

Page 257: ...ime todsel M_SSEL0 1 5 5 ns tcyc 4 5ns M_SCLK M_SSEL Output hold time tohsel M_SSEL0 1 4 5 ns Notes This is Target Spec Correct 1 DDR HSSPI Interface Timing SDR mode Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max HSSPI clock cycle tcyc M_SCLK0 CL 20pF IOL 10mA IOH 10mA 10 ns 20 when Quad Page Program M_SCLK delayed sample clock tspcnt 0 31 5 ns M_SDATA M_SLCK Input setup time tisd...

Page 258: ... delay time todsel M_SSEL0 1 7 0 ns tcyc 3 0ns M_SCLK M_SSEL Output hold time tohsel M_SSEL0 1 3 0 ns Notes This is Target Spec Correct 2 DDR HSSPI Interface Timing DDR mode Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max HSSPI clock cycle tcyc M_SCLK0 CL 20pF IOL 10mA IOH 10mA 12 5 ns M_SCLK delayed sample clock tspcnt 0 31 5 ns M_SDATA M_SLCK Input setup time tisdata M_SDATA0_0 3...

Page 259: ...SS M_CS _1 2 CL 20pF IOL 10mA IOH 10mA tCKCYC 2 0 ns CK CS Chip select hold time tCSH M_CS _1 2 tCKCYC 2 ns 234 9 Electric Characteristics 9 1 4 16 Hyper BUS Revised as below Error 16 2 Hyper Bus Write Timing HyperRAM Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max CS CK Chip Select setup time tCSS M_CS _1 2 CL 20pF IOL 10mA IOH 10mA 3 0 ns CK CS Chip select hold time tCSH M_CS _1 ...

Page 260: ...d time tIH M_DQ7 0 1 25 ns CK CS Chip select hold time tCSH M_CS _1 2 0 ns RDS DQ valid RDS transition to DQ valid tDSS M_DQ7 0 0 8 0 8 ns RDS DQ invalid RDS transition to DQ invalid tDSH M_DQ7 0 0 8 0 8 ns Correct 3 Hyper Bus Read Timing HyperFlash Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max CS CK Chip Select setup time tCSS M_CS _1 2 CL 20pF IOL 10mA IOH 10mA tRDSCYC 2 0 ns D...

Page 261: ...dicator Valid tRIV M_RWDS 6 ns CK RWDS Hi z Refresh Indicator Hold tRIH M_RWDS 0 ns Correct 4 Hyper Bus Read Timing HyperRAM Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max CS CK Chip Select setup time tCSS M_CS _1 2 CL 20pF IOL 10mA IOH 10mA tRDSCYC 2 0 ns DQ CK Setup time tIS M_DQ7 0 1 25 ns CK DQ Hold time tIH M_DQ7 0 1 25 ns CK CS Chip select hold time tCSH M_CS _1 2 tRDSCYC 2 ...

Page 262: ...nction should be referred in the S6J3300 hardware manual Though the chapter of I O port in Traveo Platform Hardware Manual describes another A D converter function do not refer it A D Channel Control Register ADC12Bn_CHCTRL0 bit5 0 ANIN 5 0 Analog Input Selection bits This register setting is possible of channel 0 31 the register value is 00_0000 to 01_1111 14 3 Product Description 3 2 Product des...

Page 263: ...event such overvoltage or over current conditions at the design stage Correct 1 Preventing Over Voltage and Over Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device and in extreme cases leads to permanent damage of the device Try to prevent such overvoltage or over current conditions at the design stage...

Page 264: ...ese LVD channels LVDL0 LVDL1 LVDL2 LVDH0 LVDH1 LVDH2 Detection voltage of the external low voltage detection reset initial is 2 6V 3 5 2 3 or 4 0V 3 5 1 This detection voltage level setting is below the minimum operation assurance voltage 2 7V 2 3 or 4 0V 1 Between this detection voltage and the minimum operation assurance voltage MCU functions are not guaranteed except for the low voltage detecto...

Page 265: ...n using SSCG_PLL output for these internal clock the MAX value of frequency has the following restrictions On the presumption that the modulation mode of SSCG_PLL is used with down spread the MAX value of the frequency is standardized This means that MAX value of frequency is the maximum value when SSCG_PLL was modulated Unused means a clock source which doesn t have any supply destinations Config...

Page 266: ...vice can be used on a standard mode I2 C bus system as long as the device satisfies the requirement of tSUDAT 250 ns 222 9 Electric Characteristics 9 1 4 11 Low Voltage Detection External Voltage Added 5 and 5 sentences as below Error Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Detection voltage after trimming VDLAT VCC5 1 3 86 3 4 0 3 4 14 3 V When power supply voltage fal...

Page 267: ...ration guarantee voltage the LVD reset factor flag is set as the voltage drops below the detection level 224 9 Electric Characteristics 9 1 4 12 Low Voltage Detection Internal Voltage Added 2 and 2 sentences as below Error Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Detection voltage after trimming VRDLAT 1 0 844 0 875 0 906 V When power supply voltage falls Typ 3 5 Correct...

Page 268: ...eference software sample application the reference board design and so on are explained Software and hardware engineer Under consideration Correct Document Type Definition Primary User Document Code S6J3350 Datasheet The function and its characteristics are specified quantitatively Investigator and hardware engineer 002 10634 S6J3300 hardware manual The function and its operation of S6J3300 series...

Page 269: ... input ports Max See 2 2 3 7 2 Function List 2 2 1 Basic option Error Correct Notes The main RAM size is configured as follows according to Digit E TCRAM 128KB System RAM 384KB D TCRAM 128KB System RAM 256KB C TCRAM 128KB System RAM 128KB B TCRAM 64KB System RAM 128KB 8 2 Function List 2 2 2 ID Error Function Digit Revision Chip ID JTAG ID S U T V C 0x10122100 0x1000B5CF A C E G C 0x10128100 0x100...

Page 270: ... The product series supports the power off control of PD1 PD2 including PD3 and 5 PD4_0 PD4_1 and PD6 19 4 Package and Pin Assignment 4 2 1 TEQFP208 Error Correct Revised PKG figure Added PKG Code 20 4 Package and Pin Assignment 4 2 2 TEQFP176 Error Correct Revised PKG figure Added PKG Code 21 22 4 Package and Pin Assignment 4 2 3 TEQFP144 Error Correct Revised PKG figure Added PKG Code 25 5 IO Ci...

Page 271: ...5 o C PD 1100mW 169 9 Electric Characteristics 9 1 2 Recommended operating condition Error Operating temperature TA 40 105 o C PD 2000mW TA 40 125 o C PD 1200mW Correct Operating temperature TA 40 105 o C PD 2000mW TA 40 125 o C PD 1100mW 169 9 Electric Characteristics 9 1 2Recommended operating condition Error S6J335xxSC S6J335xxUC S6J335xxTC S6J335xxVC S6J335xxBC S6J335xxDC S6J335xxFC S6J335xxHC...

Page 272: ...guaranteed except for the low voltage detector Note that although the detection level is below the minimum operation guarantee voltage the LVD reset factor flag is set as the voltage drops below the detection level Correct LVDL0 LVDL1 LVDL2 LVDH0 LVDH1 LVDH2 When it is used outside recommended range this is the range of guaranteed operation contact your sales representative The initial detection v...

Page 273: ... 810 µA TA 25 C 4MHz crystal for main oscillator PD1 ON PD4_0 ON PD4_1 ON 360 780 µA TA 25 C 4MHz crystal for main oscillator PD1 ON PD4_0 ON or PD4_1 ON 350 750 µA TA 25 C 4MHz crystal for main oscillator PD1 ON 450 890 µA TA 25 C 8MHz crystal for main oscillator PD1 ON PD4_0 ON PD4_1 ON 440 860 µA TA 25 C 8MHz crystal for main oscillator PD1 ON PD4_0 ON or PD4_1 ON 430 830 µA TA 25 C 8MHz crysta...

Page 274: ... time tOFF VCC5 100 μs 2 223 248 9 Electric Characteristics 9 1 4 11Low Voltage Detection External Voltage 9 1 5 A D converter Error S6J335xxSC S6J335xxUC S6J335xxTC S6J335xxVC S6J335xxAC S6J335xxBC S6J335xxCC S6J335xxDC S6J335xxEC S6J335xxFC S6J335xxGC S6J335xxHC Correct S6J335xxSx S6J335xxUx S6J335xxTx S6J335xxVx S6J335xxAx S6J335xxBx S6J335xxCx S6J335xxDx S6J335xxGx S6J335xxFx S6J335xxGx S6J335...

Page 275: ...ection voltage and the minimum operation assurance voltage MCU functions are not guaranteed except for the low voltage detector Note that although the detection level is below the minimum operation guarantee voltage the LVD reset factor flag is set as the voltage drops below the detection level Correct Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Supply voltage range VDP5 VC...

Page 276: ...en this detection voltage and the minimum operation assurance voltage MCU functions are not guaranteed except for the low voltage detector Note that although the detection level is below the minimum operation guarantee voltage the LVD reset factor flag is set as the voltage drops below the detection level Correct Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Supply voltage ra...

Page 277: ...oltage detection time TRd 30 μs 4 2 This detection voltage level setting is below the minimum operation assurance voltage Between this detection voltage and the minimum operation assurance voltage MCU functions are not guaranteed except for the low voltage detector Note that although the detection level is below the minimum operation guarantee voltage the LVD reset factor flag is set as the voltag...

Page 278: ...e TRd 30 μs 3 2 This LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage as these detection levels are below the minimum guaranteed MCU operation voltage 3 After the brown out event where the voltage level dips below the detection threshold for less than this time the detection may occur or be canceled 244 245 246 247 9 Electric Charac...

Page 279: ... D 3 136KB 112KB 384KB 16 16KB 7 2 Function List 2 2 1 Basic option Error Notes The main RAM size is configured as follows according to Digit E TCRAM 128KB System RAM 384KB D TCRAM 128KB System RAM 256KB C TCRAM 128KB System RAM 128KB B TCRAM 64KB System RAM 128KB Correct Notes The main RAM size is configured as follows according to Digit E TCRAM 128KB System RAM 384KB D TCRAM 128KB System RAM 256...

Page 280: ... 1 Absolute Maximum Rating Error Correct System Thermal Resistance Theta j a1 17 o C W TEQFP 208 The minimum value depends on the system specification of heat radiation The described value is estimated under the condition which is specified at 9 1 2 Recommended operating condition Theta j a2 19 o C W TEQFP 176 Theta j a3 20 o C W TEQFP 144 0 5mm Pitch Theta j a4 22 o C W TEQFP 144 0 4mm Pitch Pack...

Page 281: ...can be turned on in shown sequence or simultaneously 174 9 Electric Characteristics 9 1 2 Recommended operating condition Error Correct Note TA Ambient temperature JEDEC TC Case temperature JEDEC the maximum measured temperature of package case top Both rating of TA and TC should simultaneously be satisfied as maximum operation temperature The following condition should be satisfied in order to fa...

Page 282: ... 240MHz HPM 120MHz CPU 200MHz HPM 200MHz 600 100 0 mA TA 40 125 C CPU 180MHz HPM 90MHz ICCH12 Timer Stop Mode 650 mA Correct Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Power supply current ICC12 VCC12 Normal operation 320 800 mA TA 40 105 C CPU 240MHz HPM 120MHz CPU 200MHz HPM 200MHz 220 690 mA TA 40 125 C CPU 180MHz HPM 90MHz Flash write erase 350 850 mA TA 40 105 C CPU 2...

Page 283: ... time Program 320 4096 µs System level overhead time excluded 1 32bit write time Work 30 384 µs System level overhead time excluded 1 Correct Parameter Rating Unit Remarks Min Typ Max 3 Sector erase time 120 180 ms Large sector 1 Internal preprogramming time included 120 180 ms 8kB sector 1 Internal preprogramming time included 120 180 ms 4kB sector 1 Internal preprogramming time included 16bit wr...

Page 284: ...evision 8 2 Function List 2 2 3 Restriction Error Table 2 2 Correct Table 2 2 Pin Restriction 10 3 Product Description 3 2 Product Description Error Table 3 1 Correct Table 3 1 Product Features 16 4 Package and Pin Assignment 4 1 1 TEQFP 208 Pin Assignment Error Figure 4 1 TEQFP 208 Correct Figure 4 1 TEQFP 208 S6J335xKyz 1 1 x y z are selected from the following parameter x E D Memory Size y S A ...

Page 285: ...following parameter x E D Memory Size y S A B U C D T E F V G H Option z C D E Revision 17 4 Package and Pin Assignment 4 1 2 TEQFP 176 Pin Assignment Error Correct Figure 4 2 Revised Pin Assignment figure 18 4 Package and Pin Assignment 4 1 3 TEQFP 144 Pin Assignment Error Figure 4 3 TEQFP 144 Correct Figure 4 3 TEQFP 144 S6J335xHyz 1 1 x y z are selected from the following parameter x E D Memory...

Page 286: ...ode 430 mA ICC5 VCC5 Normal operation 45 85 mA Flash write erase 100 mA ICCT5 Timer mode 370 810 µA TA 25 C 4MHz crystal for main oscillator PD1 ON PD4_0 ON PD4_1 ON 360 780 µA TA 25 C 4MHz crystal for main oscillator PD1 ON PD4_0 ON or PD4_1 ON 350 750 µA TA 25 C 4MHz crystal for main oscillator PD1 ON 450 890 µA TA 25 C 8MHz crystal for main oscillator PD1 ON PD4_0 ON PD4_1 ON 440 860 µA TA 25 C...

Page 287: ... Mode 420 mA ICC5 VCC5 Normal operation 25 45 mA Flash write erase 60 mA ICCT5 Timer mode 370 810 µA TA 25 C 4MHz crystal for main oscillator PD1 ON PD4_0 ON PD4_1 ON 360 780 µA TA 25 C 4MHz crystal for main oscillator PD1 ON PD4_0 ON or PD4_1 ON 350 750 µA TA 25 C 4MHz crystal for main oscillator PD1 ON 450 890 µA TA 25 C 8MHz crystal for main oscillator PD1 ON PD4_0 ON PD4_1 ON 440 860 µA TA 25 ...

Page 288: ...PD1 ON 420 705 µA TA 25 C 8MHz crystal for main oscillator PD1 ON PD4_0 ON PD4_1 ON 415 700 µA TA 25 C 8MHz crystal for main oscillator PD1 ON PD4_0 ON or PD4_1 ON 410 695 µA TA 25 C 8MHz crystal for main oscillator PD1 ON 80 135 µA TA 25 C 32kHz crystal for sub oscillator PD1 ON PD4_0 ON PD4_1 ON 75 130 µA TA 25 C 32kHz crystal for sub oscillator PD1 ON PD4_0 ON or PD4_1 ON 70 125 µA TA 25 C 32kH...

Page 289: ...F H C 0x10120100 D 0x10120200 Correct Function Digit Revision Chip ID JTAG ID S U T V C 0x10122100 0x1000B5CF D E 0x10122200 A C E G C 0x10128100 D E 0x10128200 B D F H C 0x10120100 D E 0x10120200 10 3 Product Description 3 2 Product Description Feature Clock Error Correct Main Oscillation Stabilization Wait Time at 4 MHz 8 19ms Initial value 10 3 Product Description 3 2 Product Description Error ...

Page 290: ...ect 11 3 Product Description 3 2 Product Description Feature PLL SSCG PLL Error Down spread mode is only supported and available Correct Product supports down spread and center spread modes with the conditions defined in 9 1 4 3 Internal Clock Timing 12 3 Product Description 3 2 Product Description Feature Embedded Program Work Flash Memory Error Work Flash can be accessed with 0 wait cycle if CPU...

Page 291: ...See I2 C timing in 9 1 4 6 Multi Function Serial in detail The I2 C is not designed to be hot swappable CTS RTS is not mounted hardware flow control is not supported for this series 13 3 Product Description 3 2 Product Description Feature Hyper BUS I F Error The following register is not supported and cannot be used Controller Status Register HYPERBUSIn_CSR Interrupt Status Register HYPERBUSIn_ISR...

Page 292: ...0 000 5 years Temperature at write erase time Average temperature TA 85 degrees Celsius 1 Guaranteed value for up to 1 000 erases 2 Guaranteed value for up to 100 000 erases 3 Target Value Correct Parameter Rating Unit Remarks Min Typ Max Sector erase time 120 180 ms Large sector 1 Internal preprogramming time included 120 180 ms 8kB sector 1 Internal preprogramming time included 120 180 ms 4kB se...

Page 293: ...VHYS3 TTL input level is selected 0 035 V VHYS4 P1_03 to P1_16 P3_08 to P3_23 P4_08 to P4_23 CMOS hysteresis input level is selected 0 05 V CC5 V VHYS5 Automotive input level is selected 0 03 V CC5 V VHYS6 P1_09 P1_10 P1_15 P1_16 TTL input level is selected 0 035 V VHYS7 P1_17 to P1_31 P2_00 to P2_08 P4_24 to P4_31 CMOS hysteresis input level is selected 0 05 D VCC V VHYS8 Automotive input level i...

Page 294: ...ineer 002 07884 Correct Document Type Definition Primary User Document Code S6J3350 Datasheet This document The function and its characteristics are specified quantitatively Investigator and hardware engineer 002 10634 S6J3300 Hardware Manual S6J3300 Series 32 bit Microcontroller Traveo Family Hardware Manual The function and its operation of S6J3300 series are described Software engineer 002 1018...

Page 295: ...ck 4 PLL2 output clock 4 PLL3 output clock 4 189 9 Electric Characteristics 9 1 4 3 Internal Clock Timing Added the below 4 sentence Error none Correct 4 The PLLx SSCGx cannot set under 200MHz 196 199 202 205 208 211 214 217 248 9 Electric Characteristics 9 1 4 AC Characteristics Modified the shading document name as below Error For details see the hardware manual Correct For details see the Trave...

Page 296: ...P LEW208 Correct Part Number 1 Package S6J335EKSCSE2000A 208 pin plastic TEQFP LEW208 S6J335EKSESE20000 S6J335EKBESE20000 S6J335EJBESE20000 176 pin plastic TEQFP LEV176 Rev I 11 3 Product Description 3 2 Product Description Table 3 1 Product Features Added the below Correct Feature Description A D Converter AN39 to AN63 are not support for S6J335xxAx S6J335xxCx S6J335xxEx and S6J335xxGx option ...

Page 297: ...eup On Lan IEEE 1588 and IEEE 802 1AS Support MAC PFC Priority Based Pause Frame Support Energy Efficient Ethernet support LPI Operation in Cadence IP 802 1Qav Support Credit Based Shaping PHY Interface GMII SGMII TBI 10 100 1000 Operation 10 M 1000 M SGMII Operation Jumbo Frames Physical Control Sub Layer Correct Functions Remark External FIFO Interface Additional Low Latency TX FIFO Interface fo...

Page 298: ...on 6 1 Port Description List Revised the below Error Port Name Description Package Pin Number Remark TEQFP 144 TEQFP 176 TEQFP 208 PPG5_TOUT0_1 Base timer 11 output pin 1 21 27 Correct Port Name Description Package Pin Number Remark TEQFP 144 TEQFP 176 TEQFP 208 PPG5_TOUT0_1 Base timer 10 output pin 1 21 27 37 6 Port Description 6 1 Port Description List Revised the below Error Port Name Descripti...

Page 299: ...TOUT0_1 Base timer 31 output pin 1 163 195 Correct Port Name Description Package Pin Number Remark TEQFP 144 TEQFP 176 TEQFP 208 PPG15_TOUT0_1 Base timer 30 output pin 1 163 195 258 to 259 12 Errata Added section 12 Errata Rev J 6 2 Function List 2 2 Optional Function Revised the shading parts as below Figure 2 1 Option and Part Number for S6J3310 20 30 40 Series Error Option Digit SHE MK_CEER VCC...

Page 300: ...escription Embedded CR oscillation See the Traveo Platform Hardware Manual in detail Stabilization time is as followings 0 35 ms to 0 8 ms for 4 MHz Fast clock 0 43 ms to 1 28 ms for 100 kHz Slow clock Correct Feature Description Embedded CR oscillation See the Traveo Platform Hardware Manual in detail Stabilization time is as followings 30 us or more for 4 MHz Fast CR clock 30 us or more for 100 ...

Page 301: ...Trace clock SSCG CPU core GDC core Hyper BUS DDR HSSPI Product supports down spread and center spread modes with the conditions defined in 9 1 4 3 Internal Clock Timing Correct Feature Description PLL SSCG PLL See the Traveo Platform Hardware Manual in detail Use case assumption is following PLL Sound system clock Sound frequency master clock Peripherals Display clock Trace clock SSCG CPU core GDC...

Page 302: ...9_IN1_0 TOT17_0 TX2_0 SCS161_0 16 4 Package and Pin Assignment 4 1 3 TEQFP 144 Pin Assignment Removed the shading parts as below Package Pin 71 Error X1A P1_12 EINT13_0 PPG4_TOUT2_0 OCU8_OTD1_0 ICU9_IN1_0 TOT17_0 TX2_0 SCS161_0 Correct X1A P1_12 EINT13_0 OCU8_OTD1_0 ICU9_IN1_0 TOT17_0 TX2_0 SCS161_0 35 6 Port Description 6 1 Port Description List Removed the shading parts as below Error Port Name ...

Page 303: ...t Description List Revised the shading parts as below Error Port Name Description Package Pin Number Remark TEQFP 144 TEQFP 176 TEQFP 208 TIN0_1 Reload timer ch 0 event input pin 0 69 81 Correct Port Name Description Package Pin Number Remark TEQFP 144 TEQFP 176 TEQFP 208 TIN0_1 Reload timer ch 0 event input pin 1 69 81 ...

Page 304: ...RLT0_U FSET RLT17_ UFSET OCU2_ OTD0 OCU8_ OTD0 PPG16_ TOUT0 PPG17_ TOUT2 PPG19_ TOUT2 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 Correct RIC_RE SIN521 0x0412 ADC12B0 _HWTRG3 1 RESSEL 0 7 PORT_ PIN RLT17_ UFSET RLT1_U FSET OCU1_ OTD0 OCU2_ OTD0 PPG15_ TOUT2 PPG17_ TOUT0 PPG19_ TOUT0 RESSEL 8 15 PORTSEL 0 7 PORTSEL 8 15 RIC_RE SIN586 0x0494 ADC12B1 _HWTRG3 2 RESSEL 0 7 PORT_ PIN RLT0_U FSET RLT17_ UFSET O...

Page 305: ...x or S6J33xxxCx or S6J33xxxEx or S6J33xxxGx option take care that AVCC5 do not exceed VCC5 at for example the power on time 173 9 Electric Characteristics 9 1 Electrical Characteristics 9 1 4 AC Characteristics 9 1 4 3 Internal Clock Timing Revised the shading parts as below Error Unused means a clock source which doesn t have any supply destinations Configure it as disable with performing at the ...

Page 306: ...95 02 07 2017 ID add ICCT ICCH spec add Power and RSTX sequence add Ordering Information revise For detail see Major Changes D 5782707 06 26 2017 Delete product lineup of flash memory size 2MB and 1 5MB Digit C and B Special spec of total maximum clamp current add Icc12 Icch12 spec change Power sequence add Flash write erase spec change For detail see Major Changes E 5952291 10 31 2017 Revision ch...

Page 307: ...iption of Change I 6300353 09 05 2018 Add an option limitation for Description of A D Converter of Product Description Update Ethernet Support Functions Update Base timer allocation Added 12 Errata For detail see Major Changes J 6943828 08 05 2020 Updated some sentences For detail see Major Changes ...

Page 308: ... MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE No computing device can be absolutely secure Therefore despite security measures implemented in Cypress hardware or software products Cypress shall have no liability arising out of any security breach such as unauthorized access to or use of a Cypress product CYPRESS DOES NOT REPRESENT WARRANT OR GUARANTEE THAT CYPRESS PRODUCTS OR SYSTEMS CREAT...

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