IDT Tsi572, Hardware Manual

Page: 52 / 90

52
Tsi572 Hardware Manual
May 18, 2012
Integrated Device Technology
www.idt.com
3.3.3 Receiver DC Blocking Capacitors
The Serial RapidIO interface requires that the port inputs be capacitor coupled in order to isolate
the receiver from any common mode offset that may be present in the transmitter outputs. DC
blocking capacitors should be selected such that they have low dissipation factor and low series
inductance. The recommended capacitor value is 0.1uF ceramic in an 0402 size.
Figure 24 shows the recommended tracking and capacitor pad placement required. It will be
necessary to model and simulate the effects of the changed track spacing on the channel quality
and determine if any changes are required to the topology. An often used method of correcting
the decreased impedance caused by the larger capacitor mounting pads is to create a slot in the
shield plane below the capacitor bodies and soldering pads. Since the impedance change caused
by the slot is dependent on the capacitor geometry, core thickness, core material characteristics
and layer spacings, the size and shape of the slot will have to be determined by simulation.
Figure 24: Receiver Coupling Capacitor Positioning Recommendation
3.3.4 Escape Routing
All differential nets should maintain a uniform spacing throughout a route. Separation of
differential pairs to go around objects should not be allowed.
Figure 25 illustrates several
options for breaking out a differential pair from the Tsi572 device. The order of preference is
from A to D.
Case D below has a small serpentine section used to match the inter-pair skew of the differential
pair. In this case each serpentine section should be greater than 3 x W (W=width), and the gap
should not increase by more than 2x.
Figure 26 illustrates these requirements.
Do not place the capacitors along the signal trace at a

increment from the driver
in order to avoid possible standing wave effects.