IDT Tsi572, Hardware Manual, Page: 63 / 90

63
Tsi572 Hardware Manual
May 18, 2012
Integrated Device Technology
www.idt.com
3.6.1.2 Stability, Jitter and Noise Content
The maximum input jitter on the S_CLK input is 3pS RMS from 1.5 to 10 MHz to avoid
passing through the PLL loop filter in the SerDes and affecting the transmit data streams. The
maximum input jitter allowable on the P_CLK input is 300 pSpp. Jitter on this input would be
reflected outside of the chip on the I
2
C bus. For more information, refer to Figure 5 on page 37 .
Jitter Equation
The following equation can be used to convert Phase Noise in dBc to RMS jitter:
RMSjitter pS(rms) = [((10
(dBc/10)
)
1/2
) * 2] / [2 * pi * (frequency in hz)]
Using this equation, an example of 312.5 MHz and a phase noise of -63dBc, would produce
0.72pS RMS jitter.
3.6.2 Clock Domains
Table 19: Tsi572 Clock Domains
Clock Domain Clock Source Description
Internal Register Domain P_CLK This clock domain includes all of the internal registers and their
interconnect bus.
The domain uses the input P_CLK directly.
For more information on programming the P_CLK operating
frequency, refer to
“P_CLK Programming” on page 75 .
Internal Switching Fabric
Domain
S_CLK_[p/n] This clock domain includes the switching matrix of the ISF and
the portion of each RapidIO block that interfaces to the ISF.
I
2
C Domain P_CLK divided by 1000 This clock domain is responsible for driving the I
2
C output clock
pin I2C_SCLK.
This clock domain is generated by dividing the P_CLK input by
1000.
The majority of the I
2
C logic runs in the Internal Register
Domain
Serial Transmit Domain S_CLK_[p/n] This clock domain is used to clock all of the Serial RapidIO
transmit ports.