IDT Tsi572, Hardware Manual, Page: 59 / 90

59
Tsi572 Hardware Manual
May 18, 2012
Integrated Device Technology
www.idt.com
3.5.2 Effective Pad Design
Breakout vias for the decoupling capacitors should be kept as close together as possible. The
trace connecting the pad to the via should also be kept as short as possible with a maximum
length of 50mils. The width of the breakout traces should be 20mils, or the width of the pad.
Figure 32: Recommended Decoupling Capacitor Pad Designs
3.5.3 Power Plane Impedance and Resonance
The intent of adding decoupling to a board is to lower the impedance of the power supply to the
devices on the board. It is necessary to pay attention to the resonance of the combined bulk
capacitance and to stagger the values in order to spread the impedance valleys broadly across
the operating frequency range.
Figure 34 demonstrates the concept of staggered bands of
decoupling. Calculate the impedance of each of the capacitor values at the knee frequency to
determine their impact on resonance.
Figure 33: Equation
Table 17: Decoupling Capacitor Quantities and Values Recommended for the Tsi572
Voltage Usage Acronym Component Requirements
1.2V Logic Core VDD 20 x 0.1uF 20 x 0.01uF 16 x 1nF 16 x 22uF
1.2V SerDes core, SerDes bias SP_VDD 8 x 0.1uF 30 x 0.01uF 4 x 10uF 4 x 100uF
3.3V SerDes transceivers SPn_AVDD 8 x 0.1uF 8 x 0.01uF - -
3.3V Single ended I/O ports VDD_IO 12 x 0.1uF 12 x 0.01uF - -
1.2V Clock distribution circuit REF_AVDD 2 x 0.1uF 2 x 0.01uF 1 x ferrite bead 120 ohm @
1.5Amp
Via sharing should not be used in board design with the Tsi572.
F
knee
0.5
T
rise
----------- where
T
rise
time from 10% to 90% = =