IDT Tsi572, Hardware Manual

Page: 78 / 90

78
Tsi572 Hardware Manual
May 18, 2012
Integrated Device Technology
www.idt.com
A.2.2 IDT Specific Timers
The following sections describe how changing the P_CLK frequency to below the recommended
100 MHz operation affect the IDT-specific counters and state machines in the Tsi572.
A.2.2.1 Dead Link Timer
The Dead Link Timer period is controlled by the DLT_THRESH field in the SRIO MAC x Digital
Loopback and Clock Selection Register.
Each time a silence is detected on a link, the counter is reloaded from this register and starts to count
down. When the count reaches 0, the link is declared dead, which means that all packets are flushed
from the transmit queue and no new packets are admitted to the queue until the link comes up.
The duration of the dead link timer is computed by the following formula:
• 2^^13 * DLT_THRESH * P_CLK period
— P_CLK is 100 MHz (which gives a P_CLK period of 10nS)
— Default value of DLT_THRESH is 0x7FFF (which corresponds to 32767)
• Using these parameters, the populated formula is 8192*32767*10e-9 = 2.68 seconds
When enabled, this timer is used to determine when a link is powered up and enabled, but dead (that is,
there is no link partner responding). When a link is declared dead, the transmitting port on the Tsi572
removes all packets from its transmit queue and ensure that all new packets sent to port are dropped
rather than placed in the transmit queue.
The DLT_THRESH is a 15-bit counter with a maximum value of 32767. Table 24 shows equations
using different values for DLT_THRESH and P_CLK.
Table 24: Timer Values with P_CLK and DLT_THRESH Variations
P_CLK Setting Equation Timer Value
25 MHz 8192 * 1 * 1/25 MHz 327 uS
8192 * 32767 * 1/25 MHz 10.74 seconds
50 MHz 8192 * 1 * 1/50 MHz 163.8 uS
8192 * 32767 * 1/50 MHz 5.37 seconds
100 MHz 8192 * 1 * 1/100 MHz 81.9 uS
8192 * 32767 * 1/100 MHz 2.68 seconds