IDT Tsi572, Hardware Manual, Page: 77 / 90

77
Tsi572 Hardware Manual
May 18, 2012
Integrated Device Technology
www.idt.com
DISCOVERY_TIMER_DONE
The RapidIO Interconnect Specification (Revision 1.3) defines the DISCOVERY_TIMER_DONE as
follows:
Asserted when DISCOVERY_TIMER_EN has been continuously asserted for 12 +/- 4msec and
the state machine is in the DISCOVERY state. The assertion of DISCOVERY_TIMER_DONE
causes DISCOVERY_TIMER_EN to be de-asserted. When the state machine is not in the
DISCOVERY state, DISCOVERY_TIMER_DONE is de-asserted.
IDT Implementation
The Tsi572’s discovery timer is programmed in the RapidIO Port x Discovery Timer. The
DISCOVERY_TIMER field is used by serial ports configured to operate in 4x mode. The
DISCOVERY_TIMER allows time for the link partner to enter its discovery state, and if the link
partner supports 4x mode, for all four lanes to be aligned.
The DISCOVERY_TIMER has a default value of 9 decimal, but can be programmed to various values.
The results of changing the DISCOVERY_TIMER value and P_CLK are shown in
Table 23 .
The DISCOVERY_TIMER field is a 4-bit field whose value is used as a pre-scaler for a
17-bit counter clocked by P_CLK.
Table 23: Timer Values with DISCOVERY_TIMER and P_CLK Variations
P_CLK Setting
DISCOVERY_TIMER
Setting Equation Timer Value
100 MHz 9 decimal 9 * 0x1FFFF * 1/ P_CLK 11.79 mS
100 MHz 9 decimal 9 * 131071 * 1/ P_CLK 11.79 mS
25 MHz 1 decimal 1 * 131071 * 1/25 MHz 5.24 mS
25 MHz 2 decimal 2 * 131071 * 1/25 MHz 10.48 mS
25 MHz 15 decimal 15 * 131071 * 1/25 MHz 78.6 mS
50 MHz 1 decimal 1 * 131071 * 1/ 50 MHz 2.62 mS
50 MHz 5 decimal 5 * 131071 * 1/ 50 MHz 13.1 mS
50 MHz 15 decimal 15 * 131071 *1/ 50 MHz 19.7 mS
100 MHz 1 decimal 1 * 131071 * 1/ 100 MHz 1.31 mS
100 MHz 9 decimal 9 * 131071 * 1/ 100 MHz 11.79 mS
100 MHz 15 decimal 15 * 131071 *1/ 100 MHz 19.7 mS