IDT Tsi572, Hardware Manual

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Tsi572 Hardware Manual
May 18, 2012
Integrated Device Technology
www.idt.com
When the timer expires, either the BLTO or DTIMER event is generated, depending on whether the
boot load sequence is active. If FREERUN is set to 1 when timer expires, then the timer is restarted
immediately (the event is still generated), providing a periodic interrupt capability.
• Period(DTIMER) = (COUNT * Period(MSDIV))
— MSDIV is the millisecond period define in I2C Time PeriodDivider Register.
— The reset value for the boot load timeout is four seconds. If the boot load completes before the
timer expires, the timer is set to zero (disabled).
— Tsi572 reset value is 0x0FA0
A.2.4 Other Performance Factors
This section describes any other factors that may impact the performance of the Tsi572 if P-CLK is
programmed to operate lower than the recommended 100 MHz frequency.
A.2.4.1 Internal Register Bus Operation
The internal register bus, where all the internal registers reside, is a synchronous bus clocked by the
P_CLK source. A decrease in the P_CLK frequency causes a proportional increase in register access
time during RapidIO maintenance transactions, JTAG registers accesses, and I
2
C register accesses.
RapidIO Maintenance Transaction
Maintenance transactions use the internal register bus to read and write registers in the Tsi572. If the
P_CLK frequency is decreased, it may be necessary to review the end point’s response latency timer
value to ensure that it does not expire before the response is returned.
JTAG Register Interface
Changing the P_CLK frequency affects accesses to the internal registers through the JTAG register
interface because the interface uses the internal register bus. However, the decreased performance will
not be noticeable.
Boundary scan operations are not affected by a chance in the P_CLK frequency because these
transactions use the JTAG TCK clock signal and do not access the internal register bus.
Changing the frequency of the P_CLK does not affect the operation or performance of the
RapidIO portion of the switch, in particular its ability to route or multicast packets between
ports.