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Tsi572 Hardware Manual

May 18, 2012

Integrated Device Technology

www.idt.com

3.5.1.1

REF_AVDD

The REF_AVDD pins require extra care in order to minimize jitter on the transmitted signals.
The circuit shown in

Figure 30

is recommended for the REF_AVDD signal. One filter is

required for the two pins.

Figure 30: PLL Filter

3.5.1.2

Power and REXT

The circuit in

Figure 31

shows the connection of the power rails as required by the device.

Figure 31: Power and REXT Diagram

REF_AVDD

0.01uF

0.1uF

120

@1.5A

SP_VDD

REF_AVDD

0.01uF

0.1uF

SP_VDD (1.2V)

VSS (all)

SP{n}_REXT

SP_AVDD (3.3V)

VDD

(1.2V)

191 ohms

all pins

VDD_IO

(3.3V)

all pins

3.3V

Kelvin connection
or
separate power supplies

1.2V

Kelvin connection
or
separate power supplies

all pins

Tsi57x

Summary of Contents for Tsi572

Page 1: ...IDT Tsi572 Serial RapidIO Switch Hardware Manual May 18 2012 Titl ...

Page 2: ...on request Items identified herein as reserved or undefined are reserved for future definition IDT does not assume responsibility for conflicts or incompatibilities arising from the future definition of such items IDT products have not been designed tested or manufactured for use in and thus are not warranted for applications where the failure malfunction or any inaccuracy in the application carri...

Page 3: ...ng Conditions 30 2 3 Power 31 2 4 Electrical Characteristics 34 3 Layout Guidelines 41 3 1 Overview 41 3 2 Impedance Requirements 41 3 3 Tracking Topologies 42 3 4 Power Distribution 55 3 5 Decoupling Requirements 57 3 6 Clocking and Reset 61 3 7 Modeling and Simulation 65 3 8 Testing and Debugging Considerations 66 3 9 Reflow Profile 69 A Clocking 71 A 1 Line Rate Support 71 A 2 P_CLK Programming...

Page 4: ...4 Tsi572 Hardware Manual May 18 2012 Integrated Device Technology www idt com ...

Page 5: ...Conventions This document uses a variety of conventions to establish consistency and to help you quickly locate information of interest These conventions are briefly discussed in the following sections Non differential Signal Notation Non differential signals are either active low or active high An active low signal has an active state of logic 0 or the lower voltage level and is denoted by a lowe...

Page 6: ...1 for 125 MHz 1 25 Baud rate to 1 1 November 18 2010 Formal Added a note to Table 13 August 2009 Formal This is the current release of the Serial RapidIO Switch There have been no technical changes to the document the formatting has been updated to reflect IDT June 2009 Formal Changes have been implemented throughout the document State Single line signal Multi line signal Inactive NAME_p 0 NAME_n ...

Page 7: ...ated Device Technology www idt com 7 July 2008 Advance The changes to this documents includes adding industrial variants of the device to Ordering Information on page 87 June 2008 Advance This was the first version of the Serial RapidIO Switch ...

Page 8: ...8 Serial RapidIO Switch May 18 2012 Integrated Device Technology www idt com ...

Page 9: ... features for the Tsi572 It includes the following information Pinlist on page 9 Signals on page 10 Package Characteristics on page 24 Thermal Characteristics on page 27 1 1 Pinlist The pinlist and ballmap information for the Tsi572 are available by visiting www idt com For more information see the following documents Tsi572 Pinlist Tsi572 Ballmap ...

Page 10: ...Multicast event Control symbol 2 REF_AVDD SP_IO_SPEED 1 0 Port Configuration 2 Ports 0 2 4 6 SP_VDD SP 2 4 _T A B _ p n 16 SP_VDD SP0_T A B C D _ p n SP0_R A B C D _ p n SP0_REXT 8 8 SP0_MODESEL 1 1 SP1_PWRDN 1 SP 2 4 _R A B _ p n SP 2 4 _REXT SP 2 4 _PWRDN 4 4 SP 3 5 _PWRDN 4 SP6_T A B C D _ p n SP6_R A B C D _ p n SP6_REXT 8 8 SP6_MODESEL 1 1 SP7_PWRDN 1 SP6_PWRDN 1 Ports 0 2 4 6 SP_AVDD SP_AVDD...

Page 11: ...ng This document follows the bit numbering convention adopted by RapidIO Interconnect Specification Revision 1 3 where 0 7 is used to represent an 8 bit bus with bit 0 as the most significant bit Table 1 Signal Types Pin Type Definition I Input O Output I O Input Output OD Open Drain SRIO Differential driver receiver defined by RapidIO Interconnect Specification Revision 1 3 PU Pulled Up internal ...

Page 12: ...ese port numbers are used within the destination ID lookup tables for ingress RapidIO ports and in numerous register configuration fields Table 2 Port Numbering Port Number RapidIO Port Mode 0 Serial Port 0 SP0 1x or 4x 1 Serial Port 1 SP1 1x 2 Serial Port 2 SP2 1x 3 Serial Port 3 SP3 1x 4 Serial Port 4 SP4 1x 5 Serial Port 5 SP5 1x 6 Serial Port 6 SP6 1x or 4x 7 Serial Port 7 SP7 1x ...

Page 13: ...t Data output 1x mode No termination required SP n _TB_p O SRIO Port n Lane B Differential Non inverting Transmit Data output 4x mode Port n 1 Lane B Differential Non inverting Transmit Data output 1x mode No termination required SP n _TB_n O SRIO Port n Lane B Differential Inverting Transmit Data output 4x mode Port n 1 Lane B Differential Inverting Transmit Data output 1x mode No termination req...

Page 14: ...blocking capacitor of 0 1uF in series SP n _RB_n I SRIO Port n Lane B Differential Inverting Receive Data input 4x mode Port n 1 Lane B Differential Inverting Receive Data input 1x mode DC blocking capacitor of 0 1uF in series SP 0 6 _RC_p I SRIO Port n Lane C Differential Non inverting Receive Data input 4x mode DC blocking capacitor of 0 1uF in series SP 0 6 _RC_n I SRIO Port n Lane C Differenti...

Page 15: ... 10K pull down to VSS_IO Internal pull down may be used for logic 0 SP n _PWRDN I O LVTTL PU Port n Transmit and Receive Power Down control This signal controls the state of Port n and Port n 1 The PWRDN controls the state of all four lanes A B C D of SERDES Macro 0 Port n Powered Up Port n 1 controlled by SP n 1 _PWRDN 1 Port n Powered Down Port n 1 Powered Down Override SP n _PWRDN using PWDN_x1...

Page 16: ...red Down Override SP n 1 _PWRDN using PWDN_x4 field SRIO MAC x Clock Selection Register Output capability of this pin is only used in test mode Must remain stable for 10 P_CLK cycles after HW_RST_B is de asserted in order to be sampled correctly This signal is ignored after reset Pin must be tied off according to the required configuration Either a 10K pull up to VDD_IO or a 10K pull down to VSS_I...

Page 17: ...e sampled correctly These signals are ignored after reset and software is able to over ride the port frequency setting in the SRIO MAC x Digital Loopback and Clock Selection register The SP_IO_SPEED 1 0 setting is equal to the IO_SPEED field in SRIO MAC x Clock Selection Register Output capability of this pin is only used in test mode Pin must be tied off according to the required configuration Ei...

Page 18: ..._SWAP I LVTTL PD Configures the order of 4x transmit lanes on serial ports 0 6 0 A B C D 1 D C B A Must remain stable for 10 P_CLK cycles after HARD_RST_b is de asserted in order to be sampled correctly This signal is ignored after reset Note Ports that require the use of lane swapping for ease of routing only function as 4x mode ports The re configuration of a swapped port to dual 1x mode operati...

Page 19: ...ence clock serial port system clock ISF clock and test clock The maximum frequency of this input clock is 156 25 MHz The clock frequency is defined in Reference Clock S_CLK_p n on page 35 For more information on the S_CLK operating frequency refer to Line Rate Support on page 71 AC coupling capacitor of 0 1uF required HARD_RST_b I LVTTL Hyst PU Schmidt triggered hard reset Asynchronous active low ...

Page 20: ...ggle its value every time an Multicast Event Control Symbol is received by any port which is enabled for Multicast even control symbols Must remain stable for 10 P_CLK cycles before and after a transition No termination required This pin must not be driven by an external source until all power supply rails are stable I2 C I2C_SCLK I O OD LVTTL PU 8mA I2 C input output clock up to 100 kHz If an EEP...

Page 21: ...ngle byte peripheral address is assumed Must remain stable for 10 P_CLK cycles after HW_RST_b is de asserted in order to be sampled correctly This signal is ignored after reset No termination required Internal pull up may be used for logic 1 Pull up to VDD_IO through 10K resistor if an external pull up is desired Pull down to VSS_IO to change the logic state I2C_SA 1 0 I CMOS PU I2 C Slave Address...

Page 22: ...CK I LVTTL PD IEEE 1149 1 Test Access Port Clock input Pull up to VDD_IO through 10K resistor if not used TDI I LVTTL PU IEEE 1149 1 Test Access Port Serial Data Input Pull up to VDD_IO through a 10K resistor if the signal is not used or a if higher edge rate is required TDO O LVTTL 2mA IEEE 1149 1 Test Access Port Serial Data Output No connect if JTAG is not used Pull up to VDD_IO through a 10K r...

Page 23: ... VDD_IO should be used Power Supplies SP_AVDD Port n and n 1 3 3V supply for bias generator circuitry This is required to be a low noise supply Refer to Decoupling Requirements on page 57 REF_AVDD Analog 1 2V for Reference Clock S_CLK_p n Clock distribution network power supply Refer to Decoupling Requirements on page 57 Common Supply VDD_IO Common 3 3V supply for LVTTL I O Refer to Decoupling Req...

Page 24: ...d in the following table The following figures show the top side and bottom views of the Tsi572 package Table 4 Package Characteristics Feature Description Package Type Heat Slug Ball Grid Array HSBGA Package Body Size 21 mm x 21 mm JEDEC Specification 95 1 Section 14 Pitch 1 00 mm Ball pad size 500 um Soldermask opening 400 um Moisture Sensitivity Level 3 ...

Page 25: ...25 Tsi572 Hardware Manual May 18 2012 Integrated Device Technology www idt com Figure 2 Package Diagram Top View Figure 3 Package Diagram Side View ...

Page 26: ...26 Tsi572 Hardware Manual May 18 2012 Integrated Device Technology www idt com Figure 4 Package Diagram Bottom View ...

Page 27: ...i572 is specified safe for operation when the Junction Temperature is within the recommended limits Table 5 shows the simulated Theta jb and Thetajc thermal characteristics of the Tsi572 HSBGA package 1 4 1 Junction to Ambient Thermal Characteristics Theta ja The following table shows the simulated Theta ja thermal characteristic of the Tsi572 HSBGA package The results in the table are based on a ...

Page 28: ...tachment method PWB size layer count and conductor thickness Influence of the heat dissipating components assembled on the PWB neighboring effects Example on Thermal Data Usage Based on the ThetaJA data and specified conditions the following formula can be used to derive the junction temperature Tj of the Tsi572 with a 0m s airflow Tj èJA P Tamb Where Tj is Junction Temperature P is the Power cons...

Page 29: ...tions is not recommended Stressing the Tsi572 beyond the Absolute Maximum Rating can cause permanent damage Table 7 lists the absolute maximum ratings Table 7 Absolute Maximum Ratings Symbol Parameter Min Max Unit Tstorage Storage Temperature 55 125 C VDD_IO 3 3 V DC Supply Voltage 0 5 4 6 V SP_AVDD 3 3 V Analog Supply Voltage 0 5 4 6 V VDD SP_VDD REF_AVDD 1 2 V DC Supply Voltage 0 3 1 7 V VI_SP n...

Page 30: ...limits of the specified junction temperature could affect the device reliability Subjecting the devices to temperatures beyond the maximum minimum limits could result in a permanent failure of the device Table 8 Recommended Operating Conditions Symbol Parameter Min Max Unit Tj Junction temperature 40 125 C VDD_IO 3 3 V DC Supply Voltage 2 97 3 63 V SP_AVDD 3 3 V Analog Supply Voltage 2 97 3 63 V V...

Page 31: ... Vripple1 Power Supply ripple for Voltage Supplies SP_VDD VDD and VDD_IO 100 mVpp Vripple2 Power Supply ripple for Voltage Supplies SP n _AVDD REF_AVDD 50 mVpp IREXT External reference resistor current 10 uA a The current values provided are maximum values and dependent on device configuration such as port usage traffic etc Table 9 Power Consumption for Two links in 4x Mode Four Links in 1x Mode L...

Page 32: ...ided for fully utilized Serial RapidIO lanes 9 Core power reduces by approximately 10 under light traffic conditions Notes 1 Voltage temperature and process are all nominal 2 VDD_CORE supplies the ISF and other internal digital logic 3 SP_VDD supplies the digital portion of the Serial RapidIO SerDes 4 SPn_AVDD supplies the analog portion of the Serial RapidIO SerDes 5 VDD_IO supplies power for all...

Page 33: ...en the powering up of VDD SP_VDD and REF_AVDD are acceptable No more than 50ms after VDD is at a valid level VDD_IO 3 3 V should be powered up to a valid level VDD_IO 3 3V must not power up before VDD 1 2 V SP_AVDD 3 3V should power up at approximately the same time as VDD_IO Delays between powering up VDD_IO and SP_AVDD are acceptable SP_AVDD must not power up before SP_VDD If it is necessary to ...

Page 34: ...card that has been inserted into an active uTCA chassis and the slot power has been left in the off state Table 11 SerDes Receiver Electrical Characteristics Symbol Parameter Min Typ Max Unit Notes ZDI RX Differential Input impedance 90 100 110 Ohm VDIFFI RX Differential Input Voltage 170 1600 mV LCR RX Common Mode Return Loss 6 dB Over a range 100MHz to 0 8 Baud Frequency LDR RX Differential Retu...

Page 35: ...5 Ohm ZDO TX Differential Output Impedance 90 100 110 Ohm VSW TX Output Voltage Swing Single ended 425 600 mVp p VSW in mV ZSEO 2 x Inom x RIdr Inom where Ridr Inom is the Idr to Inom ratio VDIFFO TX Differential Output Voltage Amplitude 2 VSW mVp p 2 VOL TX Output Low level Voltage 1 2 VSW V VOH TX Output High level Voltage 1 2 V VTCM TX common mode Voltage 1 2 VSW 2 V LDR1 TX Differential Return...

Page 36: ... swing VDIFF VSW 2 V VCM Differential Input Common Mode Range S_CLK_p S_CLK_n 2 175 2000 mV The S_CLK_p n must be AC coupled Fin Input Clock Frequency 156 25 156 25 MHz FS_CLK_P N Ref Clock Frequency Stability 100 100 ppm PPM with respect to 156 25 MHz Fin_DC Ref Clock Duty Cycle 40 50 60 Tskew Ref Clock Skew 0 32 ns Between _p and _n inputs TR_SCLK TF_SCLK S_CLK_p n Input Rise Fall Time 1 ns JCLK...

Page 37: ...of LVTTL type IIL LVTTL Input Low Current 10 uA All non PU inputs and I Os of LVTTL type IIH LVTTL Input High Current 10 uA All non PD inputs and I Os of LVTTL type IOZL_PU IIL_PU LVTTL Input Low Output Tristate Current 5 100 uA All PU inputs and I Os of LVTTL type for voltages from 0 to VDD_IO on the pin IOZH_PD IIH_PD LVTTL Input High Output Tristate Current 5 100 uA All PD inputs and I Os of LV...

Page 38: ...with respect to rising edge of P_CLK SP n _MODESEL pins are sampled on every rising edge of P_CLK Tsp_modeseH SP n _MODESEL Hold Time 5 ns with respect to rising edge of P_CLK SP n _MODESEL pins are sampled on every rising edge of P_CLK TISOV1 INT_b SW_RST_b Output Valid Delay from rising edge of P_CLK 15 ns Measured between 50 points on both signals Output Valid delay is guaranteed by design TISO...

Page 39: ... Resistor pull down 28K 54K ohms Vih 2 0V Table 15 AC Specifications for I2 C Interface Symbol Parameter Min Max Units Notes FSCL I2C_SD I2C_SCLK Clock Frequency 0 100 kHz TBUF Bus Free Time Between STOP and START Condition 4 7 s 1 TLOW I2C_SD I2C_SCLK Clock Low Time 4 7 s 1 THIGH I2C_SD I2C_SCLK Clock High Time 4 s 1 THDSTA Hold Time repeated START condition 4 s 1 2 TSUSTA Setup Time for a Repeat...

Page 40: ... test TBSCR TCK Rise Time 25 ns 0 8V to 2 0V Note test TBSCF TCK Fall Time 25 ns 2 0V to 0 8V Note test TBSIS1 Input Setup to TCK 10 ns TBSIH1 Input Hold from TCK 10 ns TBSOV1 TDO Output Valid Delay from falling edge of TCKa a Outputs precharged to VDD 15 ns TOF1 TDO Output Float Delay from falling edge of TCK 15 ns TBSTRST1 TRST_B release before HARD_RST_b release 10 ns TRST_b must become asserte...

Page 41: ...file on page 69 3 1 Overview The successful implementation of a Tsi572 in a board design is dependent on properly routing the Serial RapidIO signals and maintaining good signal integrity with a resultant low bit error rate The sections that follow contain information for the user on principals that will maximize the signal quality of the links Since every situation is different IDT urges the desig...

Page 42: ...e construction is shown in Figure 7 This method also provides clean and equal return paths through VSS and VDD from the I O cell of the Tsi572 to the adjacent RapidIO device The use of broadside coupled stripline construction as shown in Figure 9 is discouraged because of its inability to maintain a constant impedance throughout the entire board signal layer The minimum recommended layer count of ...

Page 43: ...nk Figure 9 Not Recommended Broadside Coupled or Dual Stripline Construction 3 3 1 1 Microstrip When it is necessary to place the differential signal pairs on the outer surfaces of the board the differential microstrip construction is used Figure 10 shows the construction of the microstrip topology Below the figure are the design equations for calculating the impedance of the trace pair Figure 10 ...

Page 44: ...via densities are large and most of the signals switch at the same time as would be the case when a whole data group switches layers the layer to layer bypass capacitors may fail to provide an acceptably short signal return path to maintain timing and noise margins When the signals are routed using symmetric stripline return current is present on both the VDD and VSS planes If a layer change must ...

Page 45: ... consume board real estate but in a dense routing where the potential for crosstalk is present guard traces will save overall space that would have been consumed by separation space Simulation has shown that a 5 mil ground trace with 5 mil spaces between the aggressor and receptor traces offers as much isolation as a 20 mil space between aggressor and receptor traces The aggressor trace is the tra...

Page 46: ...ignals travel through the via rather than across the via A via where the signal goes through the via has a much different effect than a via where the signal travels across the via These two cases are shown in Figure 17 and in Figure 18 The in and out nodes of the via model are shown on the their corresponding locations in the figures Transitioning across a via that is not blind or buried leaves a ...

Page 47: ...capacitance and that the length of the barrel h has a direct effect on the inductance Figure 14 Equation 1 Equation parameters L is the inductance in nH h is the overall length of the via barrel d is the diameter of the via barrel Figure 15 Equation 2 Equation parameters C is the capacitance in pF T is the thickness of the circuit board or thickness of pre preg D1 is the diameter of the via pad D2...

Page 48: ... 2012 Integrated Device Technology www idt com Figure 16 Via Construction Figure 17 Signal Across a Via Figure 18 Signal Through a Via D2 D1 d T T h Signal Signal In Out Stub Via Pwr Gnd Planes Signal In Out Pwr Gnd Planes Via Signal ...

Page 49: ... the via and Lvia is the total inductance of the via These parameters may be extracted using 3D parasitic extraction tools By distributing the R L and C the model better represents the fact that the capacitance resistance and inductance are distributed across the length of the via For the Via model to be accurate in simulation the propagation delay of each LC section should be less than 1 10 of th...

Page 50: ...irs of signals In the case of the differential signals this ensures that both the negative and positive halves of the signals arrive at the receiver simultaneously thus maximizing the data sampling window in the eye diagram Creating a serpentine track is a method of adjusting the track length Ensure that the wave front does not propagate along the trace and through the crosstalk path perpendicular...

Page 51: ... of a microstrip layout 3 3 2 Crosstalk Considerations The Serial RapidIO signals easily capacitively couple to adjacent signals due to their high frequency It is therefore recommended that adequate space be used between different differential pairs and that channel transmit and receive be routed on different layers Cross coupling of differential signals results in an effect called Inter Symbol In...

Page 52: ...he shield plane below the capacitor bodies and soldering pads Since the impedance change caused by the slot is dependent on the capacitor geometry core thickness core material characteristics and layer spacings the size and shape of the slot will have to be determined by simulation Figure 24 Receiver Coupling Capacitor Positioning Recommendation 3 3 4 Escape Routing All differential nets should ma...

Page 53: ...ferential Signal Pairs Figure 26 Differential Skew Matching Serpentine 3 3 5 Board Stackup The recommended board stack up is shown in Figure 27 This design makes provision for four stripline layers and two outer microstrip layers Layers eight and nine are provisioned as orthogonal low speed signal routing layers ...

Page 54: ...54 Tsi572 Hardware Manual May 18 2012 Integrated Device Technology www idt com Figure 27 Recommended Board Stackup ...

Page 55: ...een optimized to provide jitter performance well below the limits required by the Serial RapidIO specifications The guidelines provided below will assist the user in achieving a board layout that will provide the best performance possible The required decoupling by each voltage rail can be found in Electrical Characteristics on page 29 The ripple specifications for each rail are maximums and every...

Page 56: ...from the SP_VDD plane One ferrite will suffice to isolate the SP_VDD from the REF_AVDD Two decoupling capacitors should be assigned to each pin Tip The term Kelvin connection is used to describe a single point of contact so that power from one power plane does not leak past the power supply pin into the other power plane The leakage can be prevented by the fact the output of a power supply is a ve...

Page 57: ...hically represents the parasitics present in a power distribution system Figure 29 System Power Supply Model 3 5 1 Component Selection The recommended decoupling capacitor usage for the Tsi572 is shown in Electrical Characteristics on page 29 The capacitors should be selected with the smallest surface mount body that the applied voltage permits in order to minimize the body inductance Ceramic X7R ...

Page 58: ...ired for the two pins Figure 30 PLL Filter 3 5 1 2 Power and REXT The circuit in Figure 31 shows the connection of the power rails as required by the device Figure 31 Power and REXT Diagram REF_AVDD 0 01uF 0 1uF 120 Ω 1 5A SP_VDD REF_AVDD 0 01uF 0 1uF SP_VDD 1 2V VSS all SP n _REXT SP_AVDD 3 3V VDD 1 2V 191 ohms all pins all pins all pins VDD_IO 3 3V all pins 3 3V Kelvin connection or separate pow...

Page 59: ...stagger the values in order to spread the impedance valleys broadly across the operating frequency range Figure 34 demonstrates the concept of staggered bands of decoupling Calculate the impedance of each of the capacitor values at the knee frequency to determine their impact on resonance Figure 33 Equation Table 17 Decoupling Capacitor Quantities and Values Recommended for the Tsi572 Voltage Usag...

Page 60: ...nology www idt com Figure 34 Decoupling Bypass Frequency Bands As the frequency changes each part of the power distribution system responds proportionally the low impedance power supply responds to slow events bulk capacitors to mid frequency events and so forth ...

Page 61: ...ks that are used to drive the switch s internal clock domains Figure 35 Tsi572 Clocking Architecture I 2 C_SCLK pin pin pin P_CLK S_CLK_p n I 2 C Internal registers and bus Serial Port 0 clk gen Serial Port 7 clk gen Serial Port 0 logic Serial Port 1 logic Serial Port 0 SerDes Serial Port 7 logic Serial Port 8 logic Serial Port 7 SerDes Internal Switching Fabric rxclka rxclkb rxclkc rxclkd txclk r...

Page 62: ...the clock lines is critical It is possible that low frequency noise can interfere with the operation of PLLs which can cause the PLLs to modulate at the same frequency as the noise The high frequency noise is generally beyond the PLL bandwidth which is about 1 10th the S_CLK frequency For more information refer to Figure 5 on page 37 Table 18 Clock Input Sources Clock Input Pin Type Maximum Freque...

Page 63: ...c would produce 0 72pS RMS jitter 3 6 2 Clock Domains Table 19 Tsi572 Clock Domains Clock Domain Clock Source Description Internal Register Domain P_CLK This clock domain includes all of the internal registers and their interconnect bus The domain uses the input P_CLK directly For more information on programming the P_CLK operating frequency refer to P_CLK Programming on page 75 Internal Switching...

Page 64: ...e a monotonic 3 3V swing that de asserts a minimum of 1mS after supply rails are stable The signal de assertion is used to release synchronizers based on P_CLK which control the release from reset of the internal logic P_CLK must therefore be operating and stable before the 1mS HARD_RST_b countdown begins The most versatile solution to this requirement is to AND the HARD_RST_b and TRST_b signals t...

Page 65: ...rLynx GHZ Ansoft SIwave and SiSoft SiAuditor 3 7 1 IBIS The use of IBIS for signal integrity checking at the high frequencies of the Serial RapidIO link have been found to be too inaccurate to be useful Also we have found that most tools do not yet support the IBIS Specification Revision 3 2 for the support of multi staged slew rate controlled buffers Contact IDT at www idt com for an IBIS file wh...

Page 66: ...ds The pinout for a recommended Serial RapidIO 8 channel probe is shown in Table 20 This pin signal assignment has been adopted by several tool vendors but is not an established standard The following notes apply Footprint Channel versus Lane Link Designations Channel either an upstream OR downstream differential pair for a given lane C letter the designator for a channel which accepts a given dif...

Page 67: ... www idt com Figure 37 Analyzer Probe Pad Tracking Recommendation 14 GND 13 CEp Tx2 16 CFp Rx2 15 CEn Tx2 18 CFn Rx2 17 GND 20 GND 19 CGp Tx3 22 CHp Rx3 21 CGn Tx3 24 CHn rX3 23 GND Table 20 8 Channel Probe Pin Assignment Pin Number Signal Name Pin Number Signal Name ...

Page 68: ... SIDE ONLY RESERVED FOR RETENTION MODULE 1 2 MUST MAINTAIN A SOLDERMASK WEB BETWEEN PADS WHEN TRACES ARE ROUTED BETWEEN THE PADS ON THE SAME LAYER HOWEVER SOLDERMASK MAY NOT ENCROACH ONTO THE PADS WITHIN THE PAD DIMENSIONS SHOWN VIA IN PAD NOT ALLOWED ON THESE PADS HOWEVER VIA EDGES MAY BE TANGENT TO THE PAD EDGES 3 PERMISSABLE SURFACE FINISHES ON PADS ARE HASL IMMERSION SILVER OR GOLD OVER NICKEL...

Page 69: ...e board edge connector Board designers can develop a standard test for all 1149 1 compliant devices regardless of device manufacturer package type technology or device speed In addition to the 1149 1 compliant boundary scan TAP controller the Tsi572 also contains an 1149 6 compliant TAP controller to aid in the production testing of the SerDes pins The Tsi572 also has the capability to read and wr...

Page 70: ...70 Tsi572 Hardware Manual May 18 2012 Integrated Device Technology www idt com ...

Page 71: ...hat are outside of the RapidIO specification The ability to support multiple line rates gives the Tsi572 flexibility in both application support and power consumption Table 21 shows the supported line rates for the Tsi572 The Serial Port Select pin SP_IO_SPEED 1 0 must be set to the values shown in Table 21 to achieve the documented line rates Table 21 Tsi572 Supported Line Rates 1 S_CLK_p n MHz B...

Page 72: ...ded method A 1 1 1 Modification by EEPROM Boot Load Modifying the EEPROM is the recommended method for using the S_CLK at 125 MHz to create a 3 125 Gbps link baud rate because the EEPROM boot load accesses the required configuration registers before the SerDes are released from reset This can be performed by modifying the EEPROM loading script for more information see EEPROM Scripts in the Tsi572 ...

Page 73: ...e Maintenance Transaction Sequence on page 73 Example Maintenance Transaction Sequence The following procedure configures port two After these steps are complete port two can train with its link partner at a baud rate of 3 125Gbps 1 Reset the MAC by asserting SOFT_RST_x4 and leave the IO_SPEED set to 3 125 Write offset 0x132C8 with 0x7FFF0012 2 Set the BYPASS_INIT bit to enable control of the foll...

Page 74: ... register Write offset 0x132C0 with 0x4A060005 Write offset 0x132c0 with 0xCA060005 11 Set the MPLL_PWRON bit in the SMACx_CFG_GLOBAL register Write offset 0x132C0 with 0xCA060085 Ensure that BYPASS_INIT remains asserted 12 Set TX_EN 2 0 to 0b011 in the SMACx_CFG_CH0 3 register Write offset 0x132B0 with 0x203C2513 Write offset 0x132B4 with 0x203C2513 Write offset 0x132B8 with 0x203C2513 Write offs...

Page 75: ...fication Revision 1 3 A 2 1 1 Port Link Time out CSR RapidIO Part 6 1x 4x LP Serial Physical Layer Specification Revision 1 3 Section 6 6 2 2 Port Link Time out CSR Block Offset 0x20 The RapidIO Interconnect Specification Revision 1 3 defines the Port Link Time out CSR as follows The port link time out control register contains the time out timer value for all ports on a device This time out is fo...

Page 76: ...be deasserted When the state machine is not in the SILENT state SILENCE_TIMER_DONE is deasserted IDT Implementation The Tsi572 s silence timer does not have user programmable registers The silence timer is sourced from the P_CLK and any changes to P_CLK are directly reflected in the timer timeout period Table 22 Timer Values with P_CLK and TVAL Variations P_CLK Setting TVAL Setting Equation Timer ...

Page 77: ... link partner supports 4x mode for all four lanes to be aligned The DISCOVERY_TIMER has a default value of 9 decimal but can be programmed to various values The results of changing the DISCOVERY_TIMER value and P_CLK are shown in Table 23 The DISCOVERY_TIMER field is a 4 bit field whose value is used as a pre scaler for a 17 bit counter clocked by P_CLK Table 23 Timer Values with DISCOVERY_TIMER a...

Page 78: ...ula 2 13 DLT_THRESH P_CLK period P_CLK is 100 MHz which gives a P_CLK period of 10nS Default value of DLT_THRESH is 0x7FFF which corresponds to 32767 Using these parameters the populated formula is 8192 32767 10e 9 2 68 seconds When enabled this timer is used to determine when a link is powered up and enabled but dead that is there is no link partner responding When a link is declared dead the tra...

Page 79: ... Idle Detect Timer the Byte Timeout Timer the I2C_SCLK Low Timeout Timer and the Milli Second Period Divider Period USDIV Period P_CLK USDIV 1 P_CLK is 10 ns Tsi572 reset value is 0x0063 MSDIV Period Divider for Milli Second Based Timers The MSDIV field divides the USDIV period down further for use by the Arbitration Timeout Timer the Transaction Timeout Timer and the Boot Diagnostic Timeout Timer...

Page 80: ...top condition when generated by the master control logic and the Idle Detect timer The Stop Idle register is broken down as follows The timer period for the STOP_SETUP is relative to the reference clock The timer period for the Idle Detect is relative to the USDIV period The STOP_SETUP time is shadowed during boot loading and can be reprogrammed prior to a chain operation without affecting the bus...

Page 81: ...adowed during boot loading and can be reprogrammed prior to a chain operation without affecting the bus timing for the current EEPROM SDA_SETUP Count for the I2C_SD Setup Period The SDA_SETUP field defines the minimum setup time for the I2C_SD signal that is I2C_SD is set to a desired value prior to rising edge of I2C_SCLK This applies to both slave and master interface Period SDA_SETUP SDA_SETUP ...

Page 82: ...ines the nominal low period of the clock from falling edge to rising edge of I2C_SCLK This is a master only parameter The actual observed period may be longer if other devices pull the clock low Period SCL_LOW SCL_LOW Period P_CLK P_CLK is 10 ns Reset time is 5 00 microseconds 100 kHz Tsi572 reset value is 0x01F4 A 2 3 6 I2C_SCLK Minimum High and Low Timing Register The I2C_SCLK Minimum High and L...

Page 83: ...ount of time for a slave device holding the I2C_SCLK signal low This timeout covers the period from I2C_SCLK falling edge to the next I2C_SCLK rising edge A value of 0 disables the timeout Period SCL_TO SCL_TO Period USDIV USDIV is the microsecond time defined in the I2C Time Period Divider Register The reset value of this timeout is 26 milliseconds Tsi572 reset value is 0x65BB ARB_TO Count for Ar...

Page 84: ...RAN_TO Count for Transaction Timeout Period The TRAN_TO field defines the maximum amount of time for a transaction on the I2C bus This covers the period from Start to Stop A value of 0 disables the timeout Period TRAN_TO TRAN_TO Period MSDIV MSDIV is the millisecond time defined in I2C Time Period Divider Register This timeout is disabled on reset and is not used during boot load Tsi572 reset valu...

Page 85: ...s a synchronous bus clocked by the P_CLK source A decrease in the P_CLK frequency causes a proportional increase in register access time during RapidIO maintenance transactions JTAG registers accesses and I2C register accesses RapidIO Maintenance Transaction Maintenance transactions use the internal register bus to read and write registers in the Tsi572 If the P_CLK frequency is decreased it may b...

Page 86: ...86 Tsi572 Hardware Manual May 18 2012 Integrated Device Technology www idt com ...

Page 87: ...y be three or four digits SS S Maximum operating frequency or data transfer rate of the fastest interface For operating frequency numbers M and G represent MHz and GHz For transfer rate numbers M and G represent Mbps and Gbps Table 25 Tsi572 Ordering Information Part Number Frequency Temperature Package Pin Count TSI572 10GCL 1 25 3 125 Gbit s Commercial HSBGA 399 TSI572 10GCLV 1 25 3 125 Gbit s C...

Page 88: ...contain only one of the six restricted substances Lead Pb These flip chip products are RoHS compliant through the Lead exemption for Flip Chip technology Commission Decision 2005 747 EC which allows Lead in solders to complete a viable electrical connection between semiconductor die and carrier within integrated circuit Flip Chip packages V RoHS Compliant Green These products follow the above defi...

Page 89: ...May 18 2012 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose CA 95138 for SALES 800 345 7015 or 408 284 8200 www idt com for Tech Support 408 360 1533 sRIO idt com ...

Page 90: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information IDT Integrated Device Technology TSI572 10GIL TSI572 10GCL TSI572 10GILV TSI572 10GCLV ...

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