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14. Register Descriptions

156

Tsi384 User Manual
May 5, 2014

Integrated Device Technology

www.idt.com

14.3.4

PCI Miscellaneous 0 Register

This register controls miscellaneous PCI/X functions, such as the latency timer value and cacheline
size.

Register name: PCI_MISC0
Reset value: 0x0001_0000

Register offset: 0x00C

Bits

7

6

5

4

3

2

1

0

31:24

BISTC

SBIST

Reserved

CCODE

23:16

H_TYPE

15:08

Reserved

07:00

CLINE

Bits

Name

Description

Type

Reset value

31

BISTC

BIST Capable;
0 = Tsi384 is not BIST capable

R

0

30

SBIST

Start BIST;
0 = Tsi384 is not BIST capable

R

0

29:28

Reserved

Reserved

R

0

27:24

CCODE

Completion Code;
0 = Tsi384 is not BIST capable

R

0

23:16

H_TYPE

Header Type
This field indicates the Tsi384 is a single-function bridge.

R

0x01

15:08

Reserved

Reserved (Latency timer in PCI/X Interface)

R

0

07:00

CLINE

Cacheline Size

a

04 = 4 x 32-bit word (16 bytes)
08 = 8 x 32-bit word (32 bytes)
10 = 16 x 32-bit word (64 bytes)
20 = 32 x 32-bit word (128 bytes)
This field specifies the system cacheline size in units of
32-bit words. It is used by the PCI/X master to determine the
PCI/X read transaction - that is, memory read, memory read
line, or memory read multiple - it should generate on the
PCI/X bus. CLINE is also used by the PCI/X target to decide
how much data to read on the destination bus.
Note: This field is set to 0 if CLINE is programmed to a value
not specified above.

a. Software programs the system cacheline size in DWORD counts. The value programmed is used by the Tsi384 for prefetching

data from memory for Memory Read Line and Memory Line Multiple transactions on the primary bus interface. Software
should set only one bit at anytime. If multiple bits are set, the register defaults to 0.

R/W

0x0

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Summary of Contents for TSI384

Page 1: ... IDT Tsi384 PCIe to PCI Bridge User Manual May 5 2014 ...

Page 2: ...MPLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR THAT IS CONTAINED ON ANY IDT INTERNET SITE IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT CONSEQUENTIAL INCIDENTAL INDIRECT PUNITIVE OR SPECIAL DAMAGES HOWEVER THEY MAY ARISE AND EVEN IF IDT HAS BEEN PREVIOUSLY ADVISED ABOUT THE POSSIBILITY OF SUCH DAMAGES The code examples also may be subject to United States export control laws and ma...

Page 3: ... 28 2 3 PCI X Interface Signals 29 2 4 EEPROM Interface Signals 32 2 5 JTAG Interface Signals 33 2 6 Power up Signals 34 2 7 Power Supply Signals 34 3 Data Path 37 3 1 Overview 37 3 1 1 Upstream Data Path 37 3 1 2 Downstream Data Path 38 3 2 Transaction Management 39 3 2 1 Upstream Transaction Management 39 3 2 2 Downstream Transaction Management 40 3 3 Buffer Structure 40 3 3 1 Upstream Non poste...

Page 4: ...on 59 5 2 4 Type 1 to Type 1 Forwarding 60 5 2 5 Type 1 to Special Cycle Forwarding 60 5 3 PCIe Enhanced Configuration Mechanism 61 5 4 Configuration Retry Mechanisms 61 6 Bridging 63 6 1 Overview 63 6 2 Flow Control Advertisements 63 6 3 Buffer Size and Management 64 6 4 Assignment of Requestor ID and Tag 64 6 5 Forwarding of PCIe to PCI 65 6 5 1 PCIe Memory Write Request 65 6 5 2 PCIe Non posted...

Page 5: ...table Address Attribute Errors 89 9 2 5 Received Master Abort on PCI X Interface 89 9 2 6 Received Target Abort On PCI X Interface 91 9 2 7 PCIe Unsupported Request Completion Status 92 9 2 8 PCIe Completer Abort Completion Status 93 9 2 9 Receiver of an Unexpected Completion 93 9 3 PCI X as Originating Interface 94 9 3 1 Received PCI X Errors 95 9 3 2 Unsupported Request Completion Status 99 9 3 ...

Page 6: ...11 3 10 D0 State 125 11 3 11 D3Hot State 125 11 3 12 D3Cold State 125 11 3 13 D State Transitions 126 11 3 14 Power Management Event 126 11 3 15 Power State Summary 127 12 Serial EEPROM 129 12 1 Overview 129 12 2 System Diagram 130 12 3 EEPROM Image 132 12 4 Functional Timing 133 13 JTAG 137 13 1 Overview 137 13 2 TAP Controller Initialization 138 13 3 Instruction Register 138 13 4 Bypass Register...

Page 7: ...ed Write Threshold Register 177 14 3 18 Completion Timeout Register 178 14 3 19 Clock Out Enable Function and Debug Register 179 14 3 20 SERRDIS_OPQEN_DTC Register 180 14 4 Opaque Addressing Registers 181 14 4 1 Opaque Memory Lower Register 181 14 4 2 Opaque Memory Upper Base Register 182 14 4 3 Opaque Memory Upper Limit Register 182 14 5 Upstream Non transparent Address Remapping Registers 183 14...

Page 8: ...20 14 9 4 PCIe Uncorrectable Error Severity Register 221 14 9 5 PCIe Correctable Error Status Register 222 14 9 6 PCIe Correctable Error Mask Register 223 14 9 7 PCIe Advanced Error Capabilities and Control Register 224 14 9 8 PCIe Header Log 1 Register 225 14 9 9 PCIe Header Log 2 Register 225 14 9 10 PCIe Header Log 3 Register 226 14 9 11 PCIe Header Log 4 Register 226 14 9 12 PCIe Secondary Unc...

Page 9: ...ics 249 15 4 Power Supply Sequencing 249 15 5 DC Operating Characteristics 250 15 6 AC Timing Specifications 250 15 6 1 PCI X Interface AC Signal Timing 250 15 6 2 PCIe Differential Transmitter Output Specification 252 15 6 3 PCIe Differential Receiver Input Specifications 257 15 6 4 Reference Clock 260 15 6 5 Boundary Scan Test Signal Timing 261 15 6 6 Reset Timing 261 15 7 AC Timing Waveforms 26...

Page 10: ...Contents 10 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com ...

Page 11: ...gure 19 PCI X Arbitration Priority 77 Figure 20 Interrupt Handling Diagram 80 Figure 21 PCIe Flowchart of Device Error Signaling and Logging Operations 83 Figure 22 Transaction Error Forwarding with PCIe as Originating Interface 84 Figure 23 Transaction Error Forwarding with PCI X as Originating Interface 94 Figure 24 Reset Timing 112 Figure 25 PCIe Clocking 114 Figure 26 PCI X Clocking 115 Figure...

Page 12: ...ure 44 Input Timing Measurement Waveforms 262 Figure 45 Output Timing Measurement Waveforms 263 Figure 46 PCI X TOV max Rising Edge AC Test Load 263 Figure 47 PCI X TOV max Falling Edge AC Test Load 263 Figure 48 PCI X TOV min AC Test Load 264 Figure 49 Mechanical Diagram 256 pin 17x17mm BGA 265 Figure 50 Drive Strength and Equalization Waveform 272 ...

Page 13: ... Tsi384 s Response to Split Completion Message 100 Table 18 ECRC Errors 105 Table 19 Poisoned TLP Errors 105 Table 20 Malformed TLP Errors 106 Table 21 Link and Flow Control Errors 107 Table 22 Uncorrectable Data Address Attribute Errors 108 Table 23 Received Master Target Abort Error 109 Table 25 Request Errors 110 Table 24 Completion Errors 110 Table 26 Reset Summary 111 Table 27 Reset Timing 11...

Page 14: ...eristics 249 Table 49 DC Operating Characteristics 250 Table 50 PCI X Clock PCI_CLK Specification 250 Table 51 AC Specifications for PCI X Interface 251 Table 52 PCIe Differential Transmitter Output Specification 252 Table 53 PCIe Differential Receiver Input Specifications 257 Table 54 Reference Clock PCIE_REFCLK_n p Electrical Characteristics 260 Table 55 Boundary Scan Test Signal Timings 261 Tab...

Page 15: ... by a lowercase n An active high signal has an active state of logic 1 or the higher voltage level and is not denoted by a special character The following table illustrates the non differential signal naming convention Differential Signal Notation Differential signals consist of pairs of complement positive and negative signals that are measured at the same time to determine a signal s active or i...

Page 16: ...ndicates there are two versions of the register at different addresses REG0 and REG1 Symbols Document Status Information Advance Contains information that is subject to change and is available once prototypes are released to customers Preliminary Contains information about a product that is near production ready and is revised as required Formal Contains information about a final customer ready pr...

Page 17: ... Formal Removed reference to PCIE_REXT pin because it is not applicable to the Tsi384 Changed the Pin Type definition of various signals see Signal Descriptions Added Design Recommendations for Tsi384 s signals see Signal Descriptions This information previously resided in the Tsi384 Board Design Guidelines Corrected the description of the JTAG_TDO signal Previously it indicated that the signal sh...

Page 18: ...y Sequencing Redefined two SerDes registers see PCIe Debug and Pattern Generator Control Register and PCIe Pattern Matcher Control and Error Register April 2007 Preliminary Updated the description of PCI X bus arbitration see PCI X Arbitration Scheme Added a cautionary note on how to use an EEPROM with the Tsi384 see System Diagram Updated the description of how JTAG can provide access to the Tsi3...

Page 19: ...o the PCI and PCI X bus standards see Figure 1 The Tsi384 s PCIe Interface is a superior performance configurable port that supports 1 2 or 4 lanes This enables the bridge to offer exceptional throughput performance of up to 1 GBps per transmit and receive direction The device s PCI X Interface can operate up to 133 MHz in PCI X mode or up to 66 MHz in PCI mode This interface offers designers exte...

Page 20: ... private device support Non transparent For address remapping of the PCIe and the PCI PCI X domains Compliant to the following specifications PCI Express Base Specification Revision 1 1 PCI Express to PCI PCI X Bridge Specification Revision 1 0 PCI to PCI Bridge Specification Revision 1 2 PCI X Arbiter Error Handling Interrupt Handling Clocking Reset EEPROM Controller Power Mgmt JTAG PCI X Interfa...

Page 21: ...ort for D0 D3 hot D3 cold power management states Packaged in 17 x 17 mm 256 pin PBGA 1 2 2 PCIe Features 1 2 or 4 lanes 512 byte maximum payload Advanced error reporting capability Lane reversal and lane polarity inversion End to end CRC ECRC check and generation Up to four outstanding memory reads Four 128 byte read completion buffers ASPM L0s link state power management Legacy interrupt signali...

Page 22: ...uest queue Downstream read completion buffer Rx PHY SERDES Configurati on R eg is ters Data Link Layer 2K Replay buff ers PCIe Pri mary Interface PCI XInterface Secondary Interface Tar get int erface 4 K 8 e n t r y u p s t r e a m p o s t e d w r i t e b u f f e r s Master interf ace Transaction Layer Tx PHY SERD ES Data Link Layer Tr ansaction Layer orderin g Order ing Addres s decodin g PCI X A...

Page 23: ...ered and pulled from the upstream read completion buffer PCIe is a serialized protocol at the physical layer and a packetized protocol at the data link layer Each PCIe lane operates at 2 5 Gb symbol rate or at 2 0 Gb data rate the difference is a result of the 8 10b coding process The Tsi384 uses the following processes to ensure the accurate and timely delivery of data through the data link layer...

Page 24: ...der that masters on the PCI bus retry is not deterministic If the completion buffer becomes empty prior to the transaction completing the Tsi384 disconnects from the PCI bus When the read transaction is completed the Tsi384 discards any prefetched data that is not used and frees up the buffer A read initiated on the PCI X bus that is decoded for an upstream target is handled as a split transaction...

Page 25: ... master for the transaction and initiates a read transaction on the PCI X bus The read request queue is managed using a round robin algorithm In the case of PCI X the target may respond with a split response which causes the Tsi384 to become the target for the read completion Programmable address decoders instruct the Tsi384 which transactions on the PCI X bus to forward upstream and which transac...

Page 26: ...nal Storage Application Figure 5 Server Add in Cards for Networking and Storage x4 x4 iSCSI Tsi384 PCI X to SATA GbE with TOE PCI X to SATA Integrated CPU DRAM PCI X 133 MHz PCI X 133 MHz PCIe x4 Tsi384 GbE FC Controller GbE FC Controller PCI 66 MHz PCI 66 MHz PCIe x4 Tsi384 SCSI Controller SCSI Controller IOP ...

Page 27: ... the following table Table 1 Pin Types Pin Type Definition 3 3 OD 3 3V CMOS open drain output 3 3 3 state 3 3V CMOS tri state output 3 3 Bidir 3 3V CMOS bi directional 3 3 Bidir PU 3 3V CMOS bi directional with 265K 45K pull up resistor 3 3 Bidir OD 3 3V CMOS bi directional open drain 3 3 In 3 3V CMOS input 3 3 In PU 3 3V CMOS input with 265K 45K pull up resistor 3 3 Out 3 3V CMOS output PCI X Bid...

Page 28: ...ramic capacitor on each TXD_n TXD_p signal PCIE_RXD_n 3 0 PCIE_RXD_p 3 0 PCIE Diff In Receive Data These differential pair signals receive PCIe 8b 10b encoded symbols and an embedded clock from the link partner DC blocking capacitors must be placed in the link between the transmitter and the receiver however the DC blocking capacitors are normally placed near the transmitter When designing an add ...

Page 29: ...nput Clock This signal provides timing for the Tsi384 either from an external clock or from one of the PCI_CLKO 4 0 signals see Clocking None PCI_CLKO 4 0 PCI X Out PCI Output Clock PCI_CLKO 3 0 are for driving four devices and PCI_CLKO 4 can feed back to PCI_CLK to compensate for PCB track length see Clocking Point to point connection to PCI X device IDT recommends a 33 Ohm series termination res...

Page 30: ... to 3 3V PCI_INTBn PCI X In Interrupt B Pull up 2 4K to 3 3V PCI_INTAn PCI X In Interrupt A Pull up 2 4K to 3 3V PCI_IRDYn PCI X Bidir Initiator Ready The bus master asserts this signal to indicate it is ready to complete the current transaction Pull up 8 2K to 3 3V PCI_M66EN PCI X In 66 MHz Enable This signal enables the PCI Interface for 66 MHz operation 0 33 MHz operation 1 66 MHz operation Thi...

Page 31: ... The bus target that receives the data asserts this signal Pull up 8 2K to 3 3V a PCI_PMEn PCI X In Power Management Event This signal indicates a power management event occurred see Power Management Pull up 8 2K to 3 3V a PCI_REQn 3 0 PCI X In PCI X Bidir Bus Request These signals are used to request access to the PCI X bus They are used differently however depending on whether or not the Tsi384 ...

Page 32: ... 3 3V a PCI_TRDYn PCI X Bidir Target Ready The bus target asserts this signal to indicate it is ready to complete the current data phase Pull up 8 2K to 3 3V a a These pull ups must exist somewhere on the PCI X bus b For more information on all combinations of PCI_M66EN PCI_SEL100 and PCI_PCIXCAP see the Reset Clocking and Initialization Table 4 EEPROM Interface Signals Name Pin Type Description D...

Page 33: ...signal controls the state of the TAP controller Connect to 3 3V using a 2K pull up resistor JTAG_TRSTn 3 3 In PU Test Reset This signal forces the TAP controller into an initialized state This signal must be pulsed or pulled low externally to reset the TAP controller If JTAG is not used connect this pin to a 2K pull down resistor If JTAG is used connect to output of AND gate where inputs are TRST ...

Page 34: ...n the PCI X bus 0 Tsi384 uses the internal clock generated from REFCLK to time the PCI X Interface see Master Mode Clocking 1 Tsi384 uses the clock on PCI_CLK compensated through the PLL to time the PCI X Interface This signal can be set to 0 only when the PCI bus frequency is set to 33 MHz or less For all other frequencies this signal must be set to 1 PWRUP_PLL_ BYPASSn 3 3 In PU PLL bypass This ...

Page 35: ...se signals to the 1 2V source through a ferrite bead b VSS GND GND core power None VSS_IO GND GND I O power None VSSA_PLL GND GND analog PLL power None a For filtering and decoupling information for these signals see Power Supply Filtering and Decoupling in the Tsi384 Board Design Guidelines b For more information see Analog Power Supply Filtering in the Tsi384 Board Design Guidelines Table 7 Powe...

Page 36: ...2 Signal Descriptions 36 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com ...

Page 37: ... two different sized buffers for each transaction type posted non posted and completion see Figure 6 The first stage buffering in the PCI Core which supports the store and forward method meets the synchronization requirements of PCI and PCIe This buffer design also provides optimized throughput and improved latencies The second stage buffering in the PCIe Core which supports the cut through method...

Page 38: ...rements S c r a m b l e r r Pos t ed FIFO 5 12bytes NonPostedFIFO 4 Ent ries Comple tionFI FO 6 4 b y te s Retry Bu ffer 2 KB ErrorM ess a geTLP EHU CSR PME_n M a s t e r I n t e r f a c e T a r g e t I n t e r f a c e PostedBuff er 4KB NonPos t edQ u eue 8Entrie s Do w n s tre am Read Complet ionBuf fer 5 12bytes PM C PM E M e s aa ge TL P Po s te d R e que s t Non Pos t ed Requ es t Comple tion ...

Page 39: ...re processed by the TLP arbiter only after ordering rules are satisfied The TLP arbiter selects one of the five input TLPs error message PME message posted completion and non posted TLPs in a round robin mode if sufficient credits and retry buffer space is available for the specific TLPs The TLP arbiter continues to check the available credit and retry buffer space against each of the active input...

Page 40: ... in the transmit path assembles packets and then sends them to the Data link layer unit see Figure 7 The Data link layer unit checks for LCRC and sequence number errors for packets received from the physical layer unit If there are no errors LCRC and sequence number fields are stripped and resultant TLP is sent to Transaction layer unit The Transaction layer unit checks for ECRC errors and framing...

Page 41: ...n the PCI X Interface and are destined to devices on the PCIe Interface 3 3 1 1 Non posted Write Buffer The Tsi384 supports one non posted write transaction Similar to read requests its request information is stored in one of the eight request queue entries and its data is stored in a 32 bit register Non posted write requests are forwarded onto the PCIe Core in two PCIe clock cycles Request inform...

Page 42: ...e 512 byte downstream posted write buffer stores the payload of memory write transactions that originate on the PCIe Interface and are destined for PCI X devices The amount of space assigned to each transaction is dynamic A single transaction can use 512 bytes of buffer space The Tsi384 uses an 8 deep request FIFO to store the request information including the first and last Dwords byte enables Th...

Page 43: ...the transaction that uses the memory read command since the bridge does not know whether or not the transaction address falls in prefetchable region The prefetch algorithm is configured for various commands as follows Memory read Controlled by P_MR MRL_66 and MRL_33 of the Prefetch Control Register The default value of these bits indicates that either one Dword in 32 bit bus mode or two Dwords in ...

Page 44: ... Short Term Caching set the STC_EN bit in the PCI Miscellaneous Control and Status Register When enabled the Tsi384 does not discard the additional prefetched data when the read transaction completes on the initiating bus The Tsi384 then continues to prefetch data up to the amount specified in the Prefetch Control Register If the initiator generates a new transaction that requests the previously p...

Page 45: ...the PCI X Interface for transactions that are forwarded upstream to the PCIe Interface 4 2 Memory mapped I O Space Memory transactions are forwarded across the Tsi384 when their address falls within a window defined by one of the following registers PCI Memory Base and Limit Register PCI PFM Base and Limit Register The memory mapped I O address spacing maps memory address ranges of devices that ar...

Page 46: ...CI X bus are ignored VGA_EN bit in PCI Bridge Control and Interrupt Register The Tsi384 forwards memory transactions downstream from its PCIe Interface to its PCI X Interface if a memory address is in the range defined by the Memory Base and Memory Limit registers when the base is less than or equal to the limit as shown in Figure 8 A memory transaction on the PCI X Interface that is within this a...

Page 47: ...e bit in PCI Control and Status Register Bus Master Enable bit in PCI Control and Status Register VGA Enable bit in PCI Bridge Control and Interrupt Register The Tsi384 forwards memory transactions downstream from its PCIe Interface to its PCI X Interface if a memory address is in the range defined by the Prefetchable Memory Base and Prefetchable Memory Limit registers Conversely a memory transact...

Page 48: ...bridge to I O transactions is controlled by the following configuration register bits I O Space Enable bit in PCI Control and Status Register Bus Master Enable bit in PCI Control and Status Register ISA Enable bit in PCI Bridge Control and Interrupt Register VGA Enable bit in PCI Bridge Control and Interrupt Register The I O Enable bit must be set for any I O transaction to be forwarded downstream...

Page 49: ...efined by the I O base and limit registers If the ISA Enable bit is set the bridge forwards upstream any I O transactions on the PCI X bus that are in the top 768 bytes of each 1 KB block within the first 64 KB of address space even if the address is within the I O base and limit All other transactions on the PCI X bus are forwarded upstream if they fall outside the range defined by the I O base a...

Page 50: ...ble when the VGA Enable bit is 1 VGA memory addresses are 0x0A_0000 through 0x0B_FFFF VGA I O Addresses Address bits 15 10 are not decoded when the VGA 16 Bit Decode bit is 0b are Address bits 9 0 0x3B0 through 0x3BB and 0x3C0 through 0x3DF VGA 16 Bit Decode bit is 0b Address bits 15 0 0x03B0 through 0x03BB and 0x03C0 through 0x03DF VGA 16 bit Decode bit is 1b The VGA Palette Snoop Enable bit is i...

Page 51: ... be mapped to arbitrary positions in PCI X memory space While the Memory Base and Limit registers always define the range of addresses to be claimed on the PCIe link and forwarded to the PCI X bus cycles that are claimed have their addresses modified because of the difference in the base addresses of the windows on the two buses Secondary Interface 0x0_xD000 0x0_xFFF 0x0_xC00 0x0_xCFF 0x0_x000 0x0...

Page 52: ...ented to the Tsi384 that falls within the registers described in the previous paragraph PriSecNPDiff See previous bullet 4 7 2 PCIe to PCI X Prefetchable Address Remapping Downstream transactions that fall within the address window defined by the PCI PFM Base and Limit Register PCI PFM Base Upper 32 Address Register and PCI PFM Limit Upper 32 Address Register are remapped according to the address ...

Page 53: ...e Limit is described in the following equation SecPFLimit PriPFLimit PriSecPFDiff where PriPFLimit Defined by PCI PFM Base and Limit Register and PCI PFM Base Upper 32 Address Register PriSecPFDiff Defines the difference between the Primary Prefetchable Base and the Secondary Prefetchable Base Once the address is claimed as defined above a memory cycle is forwarded from the PCI X bus to the PCIe l...

Page 54: ...of the PCIe link memory windows or undefined operation may result Figure 12 displays an example of memory window remapping Figure 12 Memory Window Remapping Example I O Address Remapping The PCI I O Address Upper 16 Register in the Tsi384 configuration space indicates the number of upper bits of the I O address that are not used when forwarding downstream I O space cycles to the PCI X bus This all...

Page 55: ...in the Tsi384 configuration space This feature can be enabled by setting OPQ_MEM_EN to 1 in the SERRDIS_OPQEN_DTC Register Memory transactions with addresses that fall in the opaque address range are not claimed by either the PCIe or PCI X Interfaces This region is typically used for peer to peer communication between devices on the PCI X bus ...

Page 56: ...4 Addressing 56 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com ...

Page 57: ...ons access devices that reside downstream of the Tsi384 Type 1 transactions are converted to Type 0 transactions if they target devices that reside on the downstream Tsi384 bus If the transaction is intended for a device that is downstream of the bus directly below the Tsi384 the transaction is passed through the Tsi384 as a Type 1 configuration transaction If the transaction is not targeted for t...

Page 58: ...g to a particular Device Number 31 16 00 Register Number Function Number Reserved 1 0 7 2 10 8 15 11 Unique Address AD 31 16 corresponding to a particular Device Number 31 16 00 Register Number Function Number Reserved 1 0 7 2 10 8 15 11 Device Number 15 11 Reserved 31 24 01 Register Number Function Number Bus Number 1 0 7 2 10 8 23 16 Device Number 15 11 Reserved 31 24 01 Register Number Function...

Page 59: ...ber field is not equal to the Secondary Bus Number value but is in the range of the Secondary Bus Number and the Subordinate Bus Number inclusive values the Type 1 configuration request is specifying a Bus Number that is located behind the bridge In this case the Tsi384 forwards the configuration request to the PCI X Interface as a Type 1 configuration transaction 3 If the Bus Number field does no...

Page 60: ...de on the PCI X Interface but is located on a bus segment further downstream To translate the forwarded transaction from a PCIe Type 1 configuration request to a PCI X Type 1 configuration transaction the Tsi384 does the following Sets address bits PCI_AD 1 0 as 0b01 PCI X Register Number Function Number Device Number and Bus Number address bits PCI_AD 23 2 are generated directly that is unmodifie...

Page 61: ...ounters an error condition prior to the bridge s timer expiration the bridge returns an appropriate error completion on PCIe If the configuration request to PCI X does not complete either successfully or with an error prior to timer expiration the bridge is required to return a completion with Configuration Retry Status CRS on PCIe for that request After the Tsi384 returns a completion with CRS on...

Page 62: ...5 Configuration Transactions 62 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com ...

Page 63: ...e main function of the Tsi384 is to allow transactions between a master or a transmitter on one bus link and a target or a receiver on the other bus link The PCI X Interface can operate in 32 64 bit PCI mode up to 66 MHz or in PCI X mode up to 133 MHz Transactions flow through the Tsi384 can be classified as follows PCIe to PCI PCIe to PCI X PCI to PCIe PCI X to PCIe 6 2 Flow Control Advertisement...

Page 64: ...actions forwarded to downstream devices The Tsi384 takes ownership of the upstream and downstream non posted transactions on behalf of original requestors and stores the transaction related state information needed to return the completions to the original requesters The action of replacing the original transaction s requester ID and or Tag fields with the bridge s own assigned values is referred ...

Page 65: ...ad Memory Read Line or Memory Read Multiple based on its cacheline size value requested byte enables and prefetchable and non prefetchable memory windows PCIe Read Request command translation is completed as follows Memory Read if the PCIe Request falls into the non prefetchable address range defined by the PCI Memory Base and Limit Register Memory Read Line if the PCIe Request falls into the pref...

Page 66: ... one of the PCI X memory read commands either Memory Read DWORD or Memory Read Block based on requested byte enables prefetchable and non prefetchable memory windows PCIe Read Request command translation is completed as follows Memory Read DWORD if the PCIe Read request falls into non prefetchable address range and requested byte enables are non contiguous Memory Read Block if the PCIe Read reques...

Page 67: ... the requests repeated by the master and returned completions for the request Since PCI read requests do not specify the amount of data to be read the Tsi384 uses a programmable prefetch algorithm to determine the amount of data to be read on behalf of the original requester The Tsi384 does not attempt to prefetch past the 4 KB address boundary on behalf of the original requester The Tsi384 stores...

Page 68: ...i384 provides normal completion up to the device boundary and split completion error message with master abort for the remaining length if the received PCI X read byte count is in out of range The Tsi384 discards the enqueued split request if the requested data is not returned before the completion timeout expires see Completion Timeout Register and returns a split completion error message with ma...

Page 69: ...ating Interface PCI Interface As a Master As a Target 0000b Interrupt Acknowledge NA NA 0001b Special Cycle Yes NA 0010b I O Read Yes Yes 0011b I O Write Yes Yes 0100b Rsvd NA NA 0101b Rsvd NA NA 0110b Memory Read Yes Yes 0111b Memory Write Yes Yes 1000b Rsvd NA NA 1001b Rsvd NA NA 1010b Configuration Read Yes NA 1011b Configuration Write Yes NA 1100b Memory Read Multiple Yes Yes 1101b Dual Addres...

Page 70: ...terface As a Master As a Target 0000b Interrupt Acknowledge NA NA 0001b Special Cycle Yes NA 0010b I O Read Yes Yes 0011b I O Write Yes Yes 0100b Rsvd NA NA 0101b Device ID Message No No 0110b Memory Read DWORD Yes Yes 0111b Memory Write Yes Yes 1000b Alias to Memory Read Block NA Yes 1001b Alias to Memory Write Block NA Yes 1010b Configuration Read Yes NA 1011b Configuration Write Yes NA 1100b Sp...

Page 71: ...Read Request Locked NA Yes MWr Memory Write Request Yes Yes IORd I O Read Request Yes Yes IOWr I O Write Request Yes Yes CfgRd0 Configuration Read Type 0 NA Yes CfgWr0 Configuration Write Type 0 NA Yes CfgRd1 Configuration Read Type 1 NA Yes CfgWr1 Configuration Write Type 1 NA Yes Msg Message Request Yes Yes MsgD Message Request with Data Payload NA Yes MsgD Vendor Defined Vendor Defined Message ...

Page 72: ...ransaction Unlock messages support locked transaction sequences in the downstream direction This type of message indicates the end of a locked sequence The Tsi384 supports locked transactions in the downstream direction and uses unlocked messages to unlock itself from the PCIe Interface 6 13 4 Slot Power Limit These messages are transmitted to downstream devices by the root complex or a switch The...

Page 73: ... ordering attribute bit is set However the device allows a Read completion with the relaxed ordering attribute bit set to pass a posted transaction Table entries with 1 and 2 are defined as follows 1 Indicates the ordering relationship when the relaxed ordering attribute bit is clear in the second transaction header information 2 Indicates the ordering relationship when the relaxed ordering attrib...

Page 74: ...6 Bridging 74 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com ...

Page 75: ...ck Diagram The bus arbiter handles internal requests from the PCI X Core and external requests from devices on the PCI X bus see Figure 18 When the arbiter is enabled the Tsi384 asserts the grant for PCI X devices and for the PCI Core When the arbiter is disabled there must be an external arbiter on the PCI X bus that handles Tsi384 requests through the PCI_REQ 0 n signal and grants bus access usi...

Page 76: ...the arbitration priority setting requesters are divided into two priority levels see Figure 19 Within each level priority is determined using a round robin method The low priority group is handled as one member of the high priority group Initially a snap shot of requesters with low and high priority is loaded and requests are arbitrated until all flags in the snap shot are cleared A new snap shot ...

Page 77: ...s granted access one of the bus requests from the low priority group in this example device C is granted access to the bus After device C is granted access another snap shot of the requestors is taken If a high priority device is requesting the bus then it is granted access before device D can become bus master This process continues indefinitely on the PCI X bus Device C Device D Low Priority Low...

Page 78: ...7 PCI X Arbitration 78 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com ...

Page 79: ...The Tsi384 s PCI X Interface forwards legacy INTx assertion de assertions in the form of Assert_INTx and Deassert_INTx messages on its PCIe link The Tsi384 handles MSI and MSI X transactions as PCI X memory write transactions When the bridge receives an MSI MSI X transaction on its PCI X Interface it forwards it as a memory write TLP on its PCIe link Both INTx messages and MSI MSI X transactions f...

Page 80: ...llows an Assert message More then one interrupt pin can toggle at any point of time however a round robin arbitration schedules the interrupt message transmission There is no buffering for interrupt messages before loading them into the upstream posted buffer Therefore only one pair of Assert_INTx and Deassert_INTx messages is loaded into the buffer when allowed In the worst case the bridge may se...

Page 81: ... an error severity level programmable by software and a corresponding error message generated on PCIe Each detected error condition has a default error severity level fatal or non fatal and when enabled has a corresponding error message generated on PCIe The error severity level is software programmable PCIe link error message generation is controlled by the following bits SERR_EN in the PCI Bridg...

Page 82: ...esponding errors on the PCIe Interface regardless of the error reporting enable bits The Tsi384 also supports Advisory Non Fatal error messages in the case where a TLP Error detected is a Advisory Non Fatal Error and the Advisory Non Fatal Error mask bit ANFE in the PCIe Correctable Error Mask Register is not masked then a Correctable error message is generated instead of a Non Fatal error message...

Page 83: ...9 Error Handling 83 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com Figure 21 PCIe Flowchart of Device Error Signaling and Logging Operations ...

Page 84: ... bridge has to perform when it forwards a non posted PCIe request read or write to PCI X and the request is completed immediately on PCI X either normally or with an error condition Table 13 Error Forwarding Requirements Step A to Step B for Received PCIe Errors Received PCIe Error Step A Forwarded PCI X Error Mode 1 Parity Step B Write Request or Read Completion with Poisoned TLP Poisoned Data Pa...

Page 85: ... receives a poisoned TLP it completes the following while forwarding it to the PCI X Interface 1 If the severity of the PTLP in the PCIe Uncorrectable Error Severity Register is Non Fatal and the ANFE Mask bit is clear in PCIe Correctable Error Mask Register then A Correctable error message is generated if the COR_ERR_EN bit is set in the PCIe Device Control and Status Register ANFE bit is set in ...

Page 86: ...he PCI_PERRn pin asserted when forwarding a write request transaction with bad parity to the PCI X bus The PERR_AD bit in the PCIe Secondary Uncorrectable Error Status Register is set Secondary Header is Logged and Secondary First Error Pointer is updated if enabled No error message is generated when PCI_PERRn is seen asserted by the bridge when forwarding a Poisoned TLP transaction from PCIe to P...

Page 87: ...RR bit in PCIe Secondary Uncorrectable Error Severity Register if the UDERR Mask bit is clear in PCIe Secondary Uncorrectable Error Mask Register and either SERR_EN bit is set in the PCI Control and Status Register or FTL_ERR_EN NFTL_ERR_EN bit is set in the PCIe Device Control and Status Register 7 S_SERR bit is set in the PCI Control and Status Register if an error message Fatal Non Fatal is gen...

Page 88: ...ng a non poisoned posted write transaction from PCIe it does the following 1 Continues to forward the remainder of the transaction 2 MDP_D bit in the PCI Secondary Status and I O Limit and Base Register is set if S_PERESP bit is set in the PCI Bridge Control and Interrupt Register 3 PERRn Assertion Detected Status bit is set in the PCIe Secondary Uncorrectable Error Status Register 4 Header is log...

Page 89: ...Base Register 3 SERR_AD bit is set in the PCIe Secondary Uncorrectable Error Status Register 4 In this case Header is not logged but the SUFEP is updated in the PCIe Secondary Error Capabilities and Control Register if the SUFEP bit is not valid and SERR_AD Mask bit is clear in the PCIe Secondary Uncorrectable Error Mask Register 5 Error Fatal or Non Fatal message is generated on PCIe as per the s...

Page 90: ...h Unsupported Request status on the PCIe 2 R_MA bit is set in PCI Secondary Status and I O Limit and Base Register 3 R_MA bit is set in PCIe Secondary Uncorrectable Error Status Register 4 Header is logged in the PCIe Secondary Header Log 4 Register and ERR_PTR is updated in the PCIe Secondary Error Capabilities and Control Register if R_MA Mask bit is clear in PCIe Secondary Uncorrectable Error M...

Page 91: ...Interface for posted requests it takes the following actions 1 Drops the entire transaction 2 R_TA bit is set in PCI Secondary Status and I O Limit and Base Register 3 R_TA bit is set in PCIe Secondary Uncorrectable Error Status Register 4 Header is logged in the PCIe Secondary Header Log 1 Register and ERR_PTR is updated in the PCIe Secondary Error Capabilities and Control Register if R_TA Mask b...

Page 92: ...s the entire transaction 2 R_TA bit is set in PCI Secondary Status and I O Limit and Base Register 3 SCD bit is set in PCI X Capability and Status Register 4 TA_SC bit is set in the PCIe Secondary Uncorrectable Error Status Register 5 Header is logged in the Secondary Header log register and ERR_PTR is updated in the PCIe Secondary Error Capabilities and Control Register if TA_SC Mask bit is clear...

Page 93: ...f the UXC bit in PCIe Uncorrectable Error Mask Register is clear and the ERR_PTR is not valid 2 If the severity of UXC in PCIe Uncorrectable Error Severity Register is Non Fatal and the ANFE Mask bit is set in PCIe Uncorrectable Error Mask Register then No error message is generated COR_ERR_DTD bit is set in PCIe Device Control and Status Register ANFE bit in PCIe Correctable Error Status Register...

Page 94: ...etected by the Tsi384 when a transaction targets the PCIe Interface Posted and non posted write data and split completion data received on the secondary PCI X Interface with bad parity are forwarded to PCIe as Poisoned TLPs Table 15 Error Forwarding Requirements for Received PCI X Errors Received PCI X Error Forwarded PCIe Error Write with Uncorrectable Data Error Write request with Poisoned TLP S...

Page 95: ...e S_PERESP bit is set The PERR pin is not asserted on the PCI bus 4 UDERR bit is set in PCIe Secondary Uncorrectable Error Status Register 5 Header is logged in the PCIe Secondary Header Log 1 Register and ERR_PTR is updated in the PCIe Secondary Error Capabilities and Control Register if UDERR Mask bit is clear in PCIe Secondary Uncorrectable Error Mask Register and ERR_PTR is not valid 6 Error F...

Page 96: ...L_ERR_EN bit is set in PCIe Device Control and Status Register 7 S_SERR bit is set in PCI Control and Status Register if an error message Fatal Non Fatal is generated and the SERR_EN bit is set 8 FTL_ERR_DTD NFTL_ERR_DTD bit is set in PCIe Device Control and Status Register 9 3 1 3 Uncorrectable Data Error on a Posted Write When the Tsi384 receives posted write transaction that is addressed such t...

Page 97: ...enerated on PCIe as per the severity level of UDERR bit in PCIe Secondary Uncorrectable Error Severity Register if UDERR Mask bit is clear in PCIe Secondary Uncorrectable Error Mask Register and either SERR_EN bit is set in PCI Control and Status Register or FTL_ERR_EN NFTL_ERR_EN bit is set in PCIe Device Control and Status Register 8 S_SERR bit is set in PCI Control and Status Register if an err...

Page 98: ...or Mask Register and ERR_PTR is not valid 6 Error Fatal or Non Fatal message is generated on PCIe as per the severity level of UADD_ERR bit in PCIe Secondary Uncorrectable Error Severity Register if UADD_ERR Mask bit is clear in PCIe Secondary Uncorrectable Error Mask Register and either SERR_EN bit is set in PCI Control and Status Register or FTL_ERR_EN NFTL_ERR_EN bit is set in PCIe Device Contr...

Page 99: ... also sets the S_TA bit in the PCI Secondary Status and I O Limit and Base Register MA_ERR bit is cleared This is the default PCI compatible mode where an Unsupported Request Error is not considered an error When a Read transaction initiated on the secondary interface results in a completion with Unsupported Request status the Tsi384 returns 0xFFFF_FFFFto the originating master and normally termin...

Page 100: ...rned to the requester 2 R_MA is set in PCI Secondary Status and I O Limit and Base Register 3 R_MA is set in PCIe Secondary Uncorrectable Error Status Register 4 Header is logged in the Secondary Header log register and ERR_PTR is updated in the PCIe Secondary Error Capabilities and Control Register if R_MA Mask bit is clear in PCIe Secondary Uncorrectable Error Mask Register and ERR_PTR is not va...

Page 101: ...t is clear in PCIe Secondary Uncorrectable Error Mask Register and ERR_PTR is not valid 6 Error Fatal or Non Fatal message is generated on PCIe as per the severity level of R_TA bit in PCIe Secondary Uncorrectable Error Severity Register if R_TA Mask bit is clear in PCIe Secondary Uncorrectable Error Mask Register and either SERR_EN bit is set in PCI Control and Status Register or FTL_ERR_EN NFTL_...

Page 102: ... the severity level of USCE bit in PCIe Secondary Uncorrectable Error Severity Register if USCE Mask bit is clear in PCIe Secondary Uncorrectable Error Mask Register and either SERR_EN bit is set in PCI Control and Status Register or FTL_ERR_EN NFTL_ERR_EN bit is set in PCIe Device Control and Status Register 4 S_SERR bit is set in PCI Control and Status Register if an error message Fatal Non Fata...

Page 103: ... 1 CTO bit is set in PCIe Uncorrectable Error Status Register 2 Error Fatal or Non Fatal message is generated on PCIe as per the severity level of the CTO bit in PCIe Uncorrectable Error Severity Register if CTO Mask bit is clear in PCIe Correctable Error Mask Register and either SERR_EN bit is set in PCI Control and Status Register or FTL_ERR_EN NFTL_ERR_EN bit is set in PCIe Device Control and S...

Page 104: ...on PCIe as per the severity level of SERR_AD bit in PCIe Secondary Uncorrectable Error Severity Register if SERR_AD Mask bit is clear in PCIe Secondary Uncorrectable Error Mask Register or SERR_EN bit is set in PCI Bridge Control and Interrupt Register and either SERR_EN bit is set in PCI Control and Status Register or FTL_ERR_EN NFTL_ERR_EN bit is set in PCIe Device Control and Status Register 3 ...

Page 105: ...ed TLP Errors Error Details Primary Reporting Mechanism Secondary Reporting Mechanism Poisoned TLP Error 1 PCIe Device Control and Status Register COR_ERR_DTD FTL_ERR_DTD 2 PCIe Correctable Error Status Register ANFE in case of Advisory Non Fatal condition 3 PCIe Uncorrectable Error Status Register PTLP 4 PCI Control and Status Register S_SERR if a Fatal error message is sent and SERR_EN bit is se...

Page 106: ...pecified in Completion TLP payload does not match length Mismatch between TD and presence of ECRC Address Length combination crosses 4KByte Received INTx message with TC 0 Received Power Management message with TC 0 Received Error message with TC 0 Received Unlock message with TC 0 TLP Type field uses undefined value Illegal byte enables 1 FBE 0 when Length 1DW 2 LBE 0 when length 1DW 3 LBE 0 when...

Page 107: ...FC contains non zero credit value Invalid that is non outstanding AckNack_Seq_Num in received Ack Nak DLLP 1 PCIe Uncorrectable Error Status Register DLPE 2 PCIe Device Control and Status Register FTL_ERR_DTD NFTL_ERR_DTD 3 Optional ERR_FATAL or ERR_NONFATAL message sent 4 PCI Control and Status Register S_SERR if error message is generated and SERR_EN is set same register TLP ends with EDB but LC...

Page 108: ... PCI Bridge Control and Interrupt Register S_PERESP PCI_PERRn asserted on the PCI Interface while forwarding a posted write transaction from PCIe 1 PCI Secondary Status and I O Limit and Base Register MDP_D if PCI Bridge Control and Interrupt Register S_PERESP 2 PCIe Secondary Uncorrectable Error Status Register PERR_AD PCI_SERRn detected on the PCI interface while forwarding transactions from PCI...

Page 109: ... is set in PCI Bridge Control and Interrupt Register and PCI Control and Status Register SERR_EN is set 2 PCIe Device Control and Status Register FTL_ERR_DTD NFTL_ERR_DTD 1 PCI Secondary Status and I O Limit and Base Register R_MA 2 PCIe Secondary Uncorrectable Error Status Register R_MA Master Abort on the PCI bus while forwarding a non posted write transaction from PCIe 1 PCIe Device Control and...

Page 110: ...Status Register R_TA 1 PCI Secondary Status and I O Limit and Base Register S_TA Received Unexpected Completion Error 1 PCIe Uncorrectable Error Status Register UXC if not masked 2 PCIe Device Control and Status Register COR_ERR_DTD if ANFE N A Completion Timeout Error 1 PCIe Uncorrectable Error Status Register CTO if not masked 2 PCIe Device Control and Status Register COR_ERR_DTD if ANFE N A Tab...

Page 111: ...26 Table 26 Reset Summary Reset Level PCI Definition Trigger EEPROM Load Tsi384 Actions 0 Cold reset Warm reset PCIE_PERSTn Yes Initialize all registers to known state including sticky Drive and release PCI_RSTn 1 ms after PCIE_PERSTn is released 1 Hot reset Reset message or DL_down state Yes Initialize all registers to known state except sticky Drive and release PCI_RSTn 1 ms after Tsi384 is comp...

Page 112: ...n all of Tsi384 s registers are in their power on reset state including sticky bits Clock PCIE_REFCLK_n p and power must be valid prior to the release of PCIE_PERSTn The timing diagram for a cold reset is displayed in Figure 24 while its values are listed in Table 27 Figure 24 Reset Timing 10 1 1 2 Warm Reset Level 0 A warm reset occurs without cycling power This is achieved by bringing PCIE_PERST...

Page 113: ...he PCI X bus using PCI_RSTn There are four conditions that cause the bridge to drive reset onto the PCI X bus 1 Assertion of PCIE_PERSTn cold warm reset 2 Receipt of a hot reset message on the PCIe link hot reset 3 PCIe link going into a DL_down state hot reset 4 Setting the PCI X bus reset bit S_RESET in the PCI Bridge Control and Interrupt Register level 2 Software must ensure there are no reque...

Page 114: ...lock tolerance on any one device 300ppm Buffer overflow is prevented by discarding skip characters Figure 25 PCIe Clocking 10 2 2 PCI X Clocking The PCI X clocking is shown in the Figure 26 The Tsi384 supports clock master and slave mode and is configured by the PWRUP_CLK_MST signal The bridge drives up to four external clocks PCI_CLKO 3 0 which are individually enabled through the Clock Out Enabl...

Page 115: ...distinguish between PCI X 66 133 MHz operation through the new logic level on PCI_PCIXCAP Prior to the configuration of the PCI X bus speed the PCI clock is in bypass mode which generates a 25 MHz clock on the PCI bus After the release of reset the PLL locks to a new frequency based on settings in Table 29 PC I E_REFCLK_p PC I E_REFCLK_n PCI_CLKO 3 0 PCI_M6 6EN PCI_SEL100 PCI_PC I XCAP PCI_PC IXCA...

Page 116: ...ith the same track lengths as PCI_CLKO 3 0 The PCB trace is only required when external clock compensation is used PCI_CLK should be tied to VSS if it is not connected to PCI_CLKO 4 Figure 27 Master Mode Clocking Table 28 PCI X Bus Mode and Speed Capability PCIXCAP Mode and Speed GND PCI 66 MHz 10K to GND PCI X 66 MHz Float PCI X 133 MHz PCIE_REFCLK_p PCIE_REFCLK_n PCI_CLKO 3 0 PCI_M6 6EN PCI_SEL1...

Page 117: ...ropriate bits in the PCI Miscellaneous Clock Straps Register Table 29 Master Mode and Clock Rate Mode and Bus Rate PCI_PCIXCAP PCI_SEL100 PCI_M66EN PCI 25 MHz GND 1 0 PCI 33 MHz GND 0 0 PCI 50 MHz GND 1 1 PCI 66 MHz GND 0 1 PCI X 50 MHz 10K to ground 1 1 PCI X 66 MHz 10K to ground 0 1 PCI X 100 MHz High 1 1 PCI X 133 MHz High 0 1 Table 30 Master Mode External Clock Compensation Mode PWRUP_CLK_MST ...

Page 118: ...d to be operating at greater than 33 MHz for more information see Table 31 Note that the PCI_CLKO 4 0 are not driven in this case they are held at VSS to save power Figure 28 Slave Clocking PCIE_REFCLK_p PCIE_REFCLK_n PCI_CLKO 3 0 PCI_M6 6EN PCI_SEL100 PCI_PCIXCAP PCI_PC I XCAP_PU PW R UP_CLK_MST PCI_ C L K PWRU P_EXT_CLK_SEL PCI_CLKO 4 Decod er Logic Clock insertion Com pens atio n P LL 10 K 0 01...

Page 119: ...ove 33 MHz then clock tree compensation is used 10 3 Initialization When the Tsi384 comes out of reset level 0 1 or 2 its clock speed and capabilities are determined according to Table 29 when in clock master mode and Table 31 when in clock slave mode This allows the Tsi384 to set its programmable PLL divided ratios when it is clock master or muxing in out the clock compensation when it is clock s...

Page 120: ...CIe reset is released sense state of PCI_PCIXCAP PCI_M66EN and PCI_SEL100 2 Configure internal PLLs 3 Apply PCI X initialization pattern The Tsi384 acts as the central resource and will also drive REQ64 low during reset since it is a 64 bit bridge 4 De assert PCI_RSTn Table 33 Initialization Pattern DEVSEL STOP TRDY Mode Bus Rate De asserted De asserted De asserted PCI 33 25 33 PCI 66 50 66 De ass...

Page 121: ...ement events The Power Management PM module connects with the Physical Layer sub block to transition the Link State into low power states when it receives a power state change request from a upstream component or when an internal event forces the link state entry into low power states in ASPM PCIe link states are not visible directly to legacy bus driver software but are derived from the Power Man...

Page 122: ...when the Tsi384 is in the D0 state After a period of idle link time the ASPM function engages the physical layer protocol that places idle link in the power saving state Once in the lower power state transitions to the fully operative L0 state can be triggered by transactions from the PCIe or PCI X Interface The L0entry capability of the Tsi384 is determined by the Root Complex reading the Tsi384 ...

Page 123: ...the L2 or L3 states The process is initiated after the PM module software transitions the Tsi384 into the D3 state and requests power management software to initiate the removal of power and clocks After the PCIe link enters the L2 L3 Ready state the Tsi384 is ready for power removal TLP and DLLP communication over link cannot occur while the Tsi384 is in this state It is also possible to remove p...

Page 124: ...n On L0s Standby state No Yes D0 On On On L1 Low power standby Yes D3hot No On On On L2 L3 ready Stagging point for power removal Yes No On On On L3 Off N A N A Off Off Off L0s L1 L0 L2 L3 Ready L3 LDn Return to L0 through LTSSM L0s Return tp L0 through LTSSM Recovery state L2 L3 Ready Psudo state to prepare component for loss of power and ref clock Link reinitialization through LTSSM Detect state...

Page 125: ... can later be transitioned into the D3Cold state by removing power from the device D3Hot is a useful state for reducing power consumption by idle components in an otherwise running system Once the Tsi384 is programmed to the D3Hot state it initiates L1 entry process The NO_SOFT_RST bit in the PCI Power Management Control and Status Register is set to 1 in the Tsi384 when software programs the brid...

Page 126: ...si384 sends a PM_PME message to the root complex during a power management event The bridge does not support a wake up function through Beacon and WAKE It does not support PME generation from the D3Cold state since the Tsi384 does not support Auxiliary power A PM_PME message are posted TLP packets that are always routed in the direction of the root complex To send a PM_PME message on its upstream ...

Page 127: ...dby D0 L1 D0 Operational Not supported no L1 using ASPM D3hot L0 D3hot D0 PME onlya a The Tsi384 drives PCI_CLKO 4 0 does not assert PCI_RSTn responds to PCI_PMEn does not participate in bus transactions Tsi384 sending PME message when in D3hot or when injecting a PME_TO_Ack TLP when Tsi384 transitions between L1 and L2 L3 ready D3hot L1 D3hot D0 PME only Power saving mode or waiting to transition...

Page 128: ...11 Power Management 128 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com ...

Page 129: ...40A AT25080A AT25160A AT25320A and AT25640A The primary purpose of the EEPROM Controller is to modify some of the default values of the Read only and Read Write registers in the Tsi384 s CSR space for more information see Register Descriptions After reset is de asserted the Controller initiates the read instructions to the external EEPROM and reads its contents If an EEPROM is present the Controll...

Page 130: ...ables and data is required to program one CSR register Table 36 describes the data structure to be maintained by the external EEPROM After the reset is de asserted the EEPROM Controller initiates a read of the first two locations of the external EEPROM to get the identification code The identification code must be 0x28AA Initially it initiates a read transaction with 9 bit address and reads the id...

Page 131: ...r that is EEPROM locations can be written and read by the root complex The root complex initiates configuration write transactions to program the EEPROM Control Register using a write command The EEPROM Controller initiates a WREN Write Enable instruction first followed by a WRITE instruction The Controller sets the BUSY bit in the register when it initiates a write instruction to the external EEP...

Page 132: ... value 0003h Byte count 15 8 Any value but total value of Byte count 15 0 should be multiple of 6 0004h CSR register m Address 7 0 Any number 0005h CSR register m byte enable 3 0 CSR register m Address 11 8 Any number 0006h CSR register m Data 7 0 Any number 0007h CSR register m Data 15 8 Any number 0008h CSR register m Data 23 16 Any number 0009h CSR register m Data 31 24 Any number 000Ah CSR reg...

Page 133: ...ite instructions in support of addresses greater than 0xFFH in 9 bit addressing mode the 8th bit of the address is transmitted in place of the third bit of the opcode of that instruction thus the address phase consists of 8 clock cycles The timing for different instructions of the EEPROM Controller are provided in the following figures Figure 32 9 bit EEPROM Read Timing FFFEh CSR register r Data 2...

Page 134: ...igure 33 16 bit EEPROM Read Timing Figure 34 9 bit EEPROM Write Timing SR_CSn Opcode Address Data SR_CLK SR_DIN SR_DOUT High Z SR_CSn Opcode Address Data SR_CLK SR_DIN SR_DOUT High Z SR_CSn SR_CLK Opcode Address Data SR_DOUT High Z SR_DIN SR_CSn SR_CLK Opcode Address Data SR_DOUT High Z SR_DIN ...

Page 135: ... 37 EEPROM RDSR Instruction Timing SR_CSn SR_CLK Opcode Address Data SR_DOUT High Z SR_DIN SR_CSn SR_CLK Opcode Address Data SR_DOUT High Z SR_DOUT High Z SR_DIN SR_CSn SR_CLK SR_DIN SR_DOUT High Z SR_CSn SR_CLK SR_DIN SR_DOUT High Z SR_CLK SR_DIN High Z SR_CSn SR_DOUT Opcode Data SR_CLK SR_DIN High Z SR_CSn SR_DOUT Opcode Data Note RDSR means Read Status Register Instruction ...

Page 136: ...12 Serial EEPROM 136 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com ...

Page 137: ...itecture standards There are five standard pins associated with the interface JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO and JTAG_TRSTn that allow full control of the internal TAP Test Access Port controller The JTAG Interface has the following features Contains a 5 pin Test Access Port TAP controller with support for the following registers Instruction register IR Boundary scan register Bypass register ...

Page 138: ... Instruction register to control the operation of the JTAG logic Bit combinations that are not equivalent to any instruction are equivalent to the BYPASS instruction 13 4 Bypass Register This register is a 1 bit shift register that provides a single bit scan path between the JTAG_TDI input and the JTAG_TDO output This abbreviated scan path is selected by the BYPASS instruction code and is used to ...

Page 139: ...e the following steps to write to a device register through the JTAG Interface 1 Move to the TAP controller Shift IR state and program the instruction register with the instruction of the DR by writing into Instruction Register bits with 0x3F_FFFF_FFFF_FFFD 2 Move to the Shift DR state and shift the data 31 0 R W 1 and the address 9 0 serially in the TDI pin To prevent corruption of unused bits th...

Page 140: ...ce 1 Move to the TAP controller Shift IR state and program the instruction register with IRAC instruction by writing into Instruction Register bits with 0x3F_FFFF_FFFF_FFFD This step is optional if the instruction register is already programmed during the write cycle 2 Move to the Shift DR state and shift the R W 0 and the address 9 0 serially in the TDI pin To prevent corruption of unused bits th...

Page 141: ...s high the bridge s JTAG pins access only the top level TAP controller When TEST_BCE is low the daisy chain mode is selected see Figure 40 TEST_BIDIR_CTRL Global tri state this signal is tied high for normal operation This pin controls the direction of the bi directional pins as input 13 8 Accessing SerDes TAP Controller The SerDes has an internal TAP controller that uses IDCODE instruction for th...

Page 142: ...13 JTAG 142 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com ...

Page 143: ...modified by power up signals or serial EEPROM R W Read write R W1C Read Write 1 to clear writing a 0 has no effect These register bits are only set by the Tsi384 RW1CS Sticky Read Only Write 1 to Clear Not initialized or modified by hot reset R WS Sticky Read Write Not initialized or modified by hot reset R W1S Read 0 Write 1 to set writing a 1 triggers an event such as an interrupt These register...

Page 144: ...Status Command 0x004 151 Class Code Revision ID 0x008 155 BIST Header Type Master Latency Timer CacheLine Size 0x00C 156 Base Address Register 0 Reserved 0x00000000 0x010 Base Address Register 1 Reserved 0x00000000 0x014 Secondary Latency Timer Subordinate Bus Number Secondary Bus Number Primary Bus Number 0x018 157 Secondary Status I O Limit I O Base 0x01C 158 Memory Status Memory Base 0x020 161 ...

Page 145: ... Status 0x084 189 Upstream Split Transaction Control 0x088 191 Downstream Split Transaction Control 0x08C 192 Table 39 Power Management Capability Registers 31 0 Offset Page Power Management Capabilities Next Pointer Capability ID 0x0A0 193 Data Reserved 0x00 bridge support extensions Reserved 0x00 PMCSR 0x0A4 195 Table 40 PCIe Capability Registers 31 0 Offset Page PCIe Capability Register Next Po...

Page 146: ...0x108 220 Uncorrectable Error Severity Register 0x10C 221 Correctable Error Status Register 0x110 222 Correctable Error Mask Register 0x114 223 Advanced Error Capabilities and Control Register 0x118 224 Header Log Register 0x11C 225 0x120 225 0x124 226 0x128 226 Secondary Uncorrectable Error Status Register 0x12C 227 Secondary Uncorrectable Error Mask Register 0x130 228 Secondary Uncorrectable Err...

Page 147: ...CI PFM Base Upper 32 Address Register 0x02C PCI_PFM_L_UPPER PCI PFM Limit Upper 32 Address Register 0x030 PCI_IO_UPPER PCI I O Address Upper 16 Register 0x034 PCI_CAP PCI Capability Pointer Register 0x038 Reserved 0x03C PCI_MISC2 PCI Bridge Control and Interrupt Register 0x040 SEC_RETRY_CNT Secondary Retry Count Register 0x044 PCI_MISC_CSR PCI Miscellaneous Control and Status Register 0x048 PCI_MI...

Page 148: ... Register 0x0A4 PCI_PMCS PCI Power Management Control and Status Register 0x0A8 Reserved 0x0AC EE_CTRL EEPROM Control Register 0x0B0 SBUS_DEVMSK Secondary Bus Device Mask Register 0x0B4 STC_PERIOD Short term Caching Period Register 0x0B8 RTIMER_STATUS Retry Timer Status Register 0x0BC PREF_CTRL Prefetch Control Register 0x0C0 PCIE_CAP PCIe Capabilities Register 0x0C4 PCIE_DEV_CAP PCIe Device Capab...

Page 149: ...lities and Control Register 0x11C PCIE_HL1 PCIe Header Log 1 Register 0x120 PCIE_HL2 PCIe Header Log 2 Register 0x124 PCIE_HL3 PCIe Header Log 3 Register 0x128 PCIE_HL4 PCIe Header Log 4 Register 0x12C PCIE_SERR_STAT PCIe Secondary Uncorrectable Error Status Register 0x130 PCIE_SERR_MASK PCIe Secondary Uncorrectable Error Mask Register 0x134 PCIE_SERR_SEV PCIe Secondary Uncorrectable Error Severit...

Page 150: ... DID 23 16 DID 15 08 VID 07 00 VID Bits Name Description Type Reset value 31 16 DID Device ID This field indicates the silicon device identification number This value can be overridden through serial EEPROM programming RE 0x8114 15 0 VID Vendor ID This field indicates the silicon vendor identification number By default the Tsi384 device reports a value of 0x10E3 indicating the vendor as IDT former...

Page 151: ... Completion or Write Request on the PCIe Interface regardless of the state the Parity Error Response bit in the Command register 0 Data poisoning and bad ECRC not detected by the bridge on its PCIe Interface 1 Data poisoning or bad ECRC detected by the bridge on its PCIe Interface R W1C 0 30 S_SERR Signaled System Error This bit is set when the bridge sends an ERR_FATAL or ERR_NONFATAL message to ...

Page 152: ...Ie It always reads 0 R 00 24 MDP_D Master Data Parity Error 0 No uncorrectable data error detected on the PCIe Interface 1 Uncorrectable data error detected on the PCIe Interface This field is set by the Tsi384 if its Parity Error Response Enable bit is set and either of the following conditions occurs The Tsi384 receives a Completion marked poisoned on the PCIe Interface The Tsi384 poisons a writ...

Page 153: ... apply for PCIe bridges It always reads 0 R 0 06 PERESP Parity Error Response Enable This bit controls the Tsi384 s setting of the Master Data Parity Error bit in the Status register in response to a received poisoned TLP from PCIe 0 Disable the setting of the Master Data Parity Error bit 1 Enable the setting of the Master Data Parity Error bit R W 0 05 VGAPS VGA Palette Snoop This field does not ...

Page 154: ...ory Requests on the PCIe Interface as Unsupported Request Received Forward all memory requests from the PCI X Interface to the PCIe Interface 1 Enable forwarding of memory transactions to the PCI X Interface and any internal function R W 0 00 IOS I O Space Enable This bit controls the Tsi384 s response as a target to I O transactions on the PCIe Interface that address a device that resides behind ...

Page 155: ... 0x008 Bits 7 6 5 4 3 2 1 0 31 24 BASE 23 16 SUB 15 08 PROG 07 00 RID Bits Name Description Type Reset value 31 24 BASE Base Class This field indicates the device is a bridge R 0x06 23 16 SUB Sub Class This field indicates the device is a PCI to PCI bridge R 0x04 15 08 PROG Program Interface This field is not applicable for a bridge It always reads 0 R 0x00 07 00 RID Revision ID This field indicat...

Page 156: ...served Reserved Latency timer in PCI X Interface R 0 07 00 CLINE Cacheline Sizea 04 4 x 32 bit word 16 bytes 08 8 x 32 bit word 32 bytes 10 16 x 32 bit word 64 bytes 20 32 x 32 bit word 128 bytes This field specifies the system cacheline size in units of 32 bit words It is used by the PCI X master to determine the PCI X read transaction that is memory read memory read line or memory read multiple ...

Page 157: ...PCI X Interface 00000 PCI reset value 01000 PCI X reset value R W Undefined 26 24 S_LTIMER_8 Set to 000 to force 8 cycle increments for the Secondary Latency Timer R 000 23 16 SUB_BUS_NUM Subordinate Bus Number The system software programs this field with the Tsi384 s highest numbered downstream secondary bus number This value is used by the Tsi384 to respond to Type 1 Configuration transactions o...

Page 158: ...parity error as a target of a write transaction Data parity error as a master of a read transaction 0 Device did not detect a parity error 1 Device detected a parity error R W1C 0 30 S_SERR Received System Error This bit reports the assertion of PCI_SERRn on the PCI X Interface 1 PCI_SERRn was detected on the PCI X Interface 0 PCI_SERRn was not detected R W1C 0 29 R_MA Received Master Abort This b...

Page 159: ...econdary bus interface operates in PCI mode indicating that the bridge can decode fast back to back transactions when the transactions are from the same master but to different targets This bit is hardwired to 1 in PCI X mode but is not important because fast back to back transactions are not supported by PCI X devices R 1 22 Reserved Reserved R 0 21 DEV66 66 MHz Capable PCI Bus This bit is hardwi...

Page 160: ...decoding These bits define the lower bound of address range used by the bridge to forward an I O transaction from one interface to the other These 4 bits correspond to address bits 15 12 The address bits 11 0 are assumed equal to 12 h0 R W 0x0 03 00 ADD_CAP2 Addressing Capability The Tsi384 supports 32 bit I O addressing R 0x1 Continued Bits Name Description Type Reset value ...

Page 161: ...ed in conjunction with the Memory Base Address for forwarding memory mapped I O transactions These bits define the upper bound for the memory address range The upper 12 bits correspond to address bits 31 20 of the address range Bits 19 0 of the address range are 0xFFFFF R W 0 19 16 Reserved Reserved R 0 15 04 BA Memory Base Address This field defines the lower bound of the address range for forwar...

Page 162: ...d I O transactions These bits define the upper bound for the memory address range The upper 12 bits correspond to address bits 31 20 of the address range Bits 19 0 of the address range are 0xFFFFF R W 0 19 16 ADD_LA_64 Addressing Capability Memory Base Address The Tsi384 supports 64 bit addressing R 0x1 15 04 BA Prefetchable Memory Base Address This field defines the lower bound of the prefetchabl...

Page 163: ...th BA in the PCI PFM Base and Limit Register to specify the lower bound of the 64 bit prefetchable address range The 32 bits relate to address bits 63 32 of the Prefetchable Base Address bits R W 0x0 Register name PCI_PFM_L_UPPER Reset value 0x0000_0000 Register offset 0x02C Bits 7 6 5 4 3 2 1 0 31 24 LA 23 16 LA 15 08 LA 07 00 LA Bits Name Description Type Reset value 31 00 LA Prefetchable Memory...

Page 164: ...LA in the PCI Secondary Status and I O Limit and Base Register to define the upper bound 32 bit address range used for decoding I O transactions from the PCIe Interface to the PCI X Interface These bits relate to address bits 31 16 of I O Limit Address R W 0x0000 15 00 IO_BA I O Base Address Upper 16 bits This field is used in conjunction with IO_BA in the PCI Secondary Status and I O Limit and Ba...

Page 165: ... value 0x0000_0080 Register offset 0x034 Bits 7 6 5 4 3 2 1 0 31 24 Reserved 23 16 Reserved 15 08 Reserved 07 00 CAP_PTR Bits Name Description Type Reset value 31 08 Reserved Reserved R 0x0 07 00 CAP_PTR Capabilities Pointer This register contains the head pointer for the capability list in the PCI configuration space see PCI X Capability and Status Register R 0x080 ...

Page 166: ...n the Secondary Discard Timer expires and a Delayed Transaction is discarded from a queue in the bridge The severity is selectable only if Advanced Error Reporting is supported 0 Do not generate ERR_NONFATAL or ERR_FATAL on the PCIe Interface as a result of the expiration of the Secondary Discard Timer Note that an error message can still be sent if Advanced Error Reporting is supported and the De...

Page 167: ...CI clock cycles 1 Secondary Discard Timer counts 210 PCI clock cycles R W 0 24 DISCARD1 Primary Discard Timer This bit does not apply to PCIe It always reads 0 R 0 23 S_FPTP_EN Fast Back to Back Enable The Tsi384 cannot generate fast back to back transactions as a master on the PCI X Interface R 0 22 S_RESET Secondary Bus Reset This bit forces the assertion of PCI_RST on the PCI X Interface The se...

Page 168: ...sted transactions initiated from the PCIe Interface no action is taken that is all data is discarded 1 Report UR Completions from PCIe by signaling Target Abort on the PCI X Interface when the PCI X Interface is operating in PCI mode For posted transactions initiated from the PCIe Interface and Master Aborted on the PCI X Interface the bridge must return an ERR_NONFATAL by default or ERR_FATAL tra...

Page 169: ... the decoding If this bit is set the forwarding of VGA addresses is independent of the following The value of the ISA Enable bit The I O address range and memory address ranges defined by the I O Base and Limit registers the Memory Base and Limit registers and the Prefetchable Memory Base and Limit registers of the bridge The forwarding of VGA addresses is qualified by the I O Enable and Memory En...

Page 170: ...ined by the I O Base and Limit registers that are in the first 64 KB of PCI I O address space top 768 bytes of each 1 KB block R W 0 17 SERR_EN SERR Enable This bit controls the forwarding of PCI X SERR assertions to the PCIe Interface The Tsi384 transmits an ERR_FATAL or ERR_NONFATAL cycle on the PCIe Interface when PCI_SERRn is asserted on the PCI X Interface This bit is set when Advanced Error ...

Page 171: ...st generate parity or ECC if applicable even if parity error reporting is disabled Also a bridge must always forward data with poisoning from PCI X to PCIe on an uncorrectable PCI X data error regardless of the setting of this bit 0 Ignore uncorrectable address attribute and data errors on the PCI X Interface 1 Enable uncorrectable address attribute and data error detection and reporting on the PC...

Page 172: ...EC_RT_CNT Bits Name Description Type Reset value 31 4 Reserved Reserved R 0 3 0 SEC_RT_CNT This field defines the number of retries that the Tsi384 will receive on the secondary bus for a requested transaction before its internal retry counter expires When the counter expires the bridge discards the request 0000 Counting disabled No expiration 0001 256 retries before expiration 0010 64K retries be...

Page 173: ...B3 Enable Arbiter 3 0 Tsi384 disables PCI_REQ3n for arbitration 1 The bridge enables PCI_REQ3n for arbitration R W 1 28 EN_ARB2 Enable Arbiter 2 0 Tsi384 disables PCI_REQ2 for arbitration 1 Tsi384 enables PCI_REQ2 for arbitration R W 1 27 EN_ARB1 Enable Arbiter 1 0 Tsi384 disables PCI_REQ1 for arbitration 1 Tsi384 enables PCI_REQ1 for arbitration R W 1 26 EN_ARB0 Enable Arbiter 0 0 Tsi384 disables...

Page 174: ... Priority 2 0 Tsi384 assigns low priority to PCI_REQ2 1 Tsi384 assigns high priority to PCI_REQ2 R W 0 17 ARB_PRI1 Arbiter Priority 1 0 Tsi384 assigns low priority to PCI_REQ1 1 Tsi384 assigns high priority to PCI_REQ1 R W 0 16 ARB_PRI0 Arbiter Priority 0 0 Tsi384 assigns low priority to PCI_REQ0 1 Tsi384 assigns high priority to PCI_REQ0 R W 0 15 Reserved Reserved R 0 14 11 CPL_INIT_COUNT This is...

Page 175: ...urns the Completion with CRS completion status for the received Type 1 configuration requests if this timer is expired before receiving the Completion from the targeted secondary device 000 25 us 001 40 us 010 50 us 011 100 us 100 200 us 101 500 us 110 1 ms 111 10 ms R W 001 07 00 Reserved Reserved R 0x00 Continued Bits Name Description Type Reset value ...

Page 176: ...0 50 nominal PCI_CLKO 0 PLL Clock is 200 MHz This generates 33 66 nominal PCI_CLKO Note For normal operation leave this bit in its default state R W 1 7 4 Reserved Reserved R 0 3 OP_MODE Operating Mode This bit overrides the PCIXCAP signal from PADS 0 Tsi384 samples the PCIXCAP from PADS 1 Tsi384 overrides the PCIXCAP from PADS R W 0 2 0 CS_MODE Clock Speed and Interface Mode This field defines th...

Page 177: ...ype Reset value 31 5 Reserved Reserved R 0 4 0 UPST_PWR_THRES This field defines the threshold for the upstream posted writes and indicates the length of posted write data to be accumulated in the upstream posted buffer that triggers forwarding of a posted request onto the PCIe core Note Other events may also trigger forwarding For more information see Upstream Posted Buffer This field is defined ...

Page 178: ...mpletion Timeout Enable This bit enables disables the Completion Timeout function The Tsi384 handles an upstream non posted request as if completion is returned with UR if the completion is not returned before its Completion Timeout Timer is expired 0 Disable Completion Timeout Timer 1 Enable Completion Timeout Timer R W 1 30 00 CPL_TO_VALUE Completion Timeout Value This 31 bit register defines th...

Page 179: ...and disables the five clocks PCI_CLK_OUT 4 0 supplied to the PCI X secondary devices when the Tsi384 is enabled as clock master through the PWRUP_CLK_MST power up signal CLKOUT_ENB 0 0 Disable PCI_CLK_OUT 0 1 Enable PCI_CLK_OUT 0 CLKOUT_ENB 1 0 Disable PCI_CLK_OUT 1 1 Enable PCI_CLK_OUT 1 CLKOUT_ENB 2 0 Disable PCI_CLK_OUT 2 1 Enable PCI_CLK_OUT 2 CLKOUT_ENB 3 0 Disable PCI_CLK_OUT 3 1 Enable PCI_...

Page 180: ... Enable 0 Secondary discard timer value sets to either 0x03FF 1K PCI clock cycles or 0x7FFF 32 K PCI clock cycles 1 Secondary discard timer value sets to 0x003F 64 PCI clock cycles R W 0 9 Reserved Reserved R 0 8 SEC_DIST_EN Secondary Discard Timer Enable 0 Disable Secondary Discard Timer 1 Enable Secondary Discard Timer R W 1 07 06 Reserved Reserved R 0 5 OPQ_MEM_EN Opaque Memory Address Enable 0...

Page 181: ...tting OPQ_MEM_EN to 1 in the SERRDIS_OPQEN_DTC Register 14 4 1 Opaque Memory Lower Register Register name PCI_OPQMEMB_OPQMEML Reset value 0x0001_0001 Register offset 0x05C Bits 7 6 5 4 3 2 1 0 31 24 OPQ_LL 23 16 OPQ_LL OPQ_LL64 15 08 OPQ_LB 07 00 OPQ_LB OPQ_LB64 Bits Name Description Type Reset value 31 20 OPQ_LL Opaque memory lower limit R W 0 19 16 OPQ_LL64 Opaque memory lower limit Set to 0x1 t...

Page 182: ...0x0000_0000 Register offset 0x060 Bits 7 6 5 4 3 2 1 0 31 24 OPQ_UB 23 16 OPQ_UB 15 08 OPQ_UB 07 00 OPQ_UB Bits Name Description Type Reset value 31 00 OPQ_UB Opaque memory upper base R W 0x0 Register name PCI_OPQMEMLUP Reset value 0x0000_0000 Register offset 0x064 Bits 7 6 5 4 3 2 1 0 31 24 OPQ_UL 23 16 OPQ_UL 15 08 OPQ_UL 07 00 OPQ_UL Bits Name Description Type Reset value 31 00 OPQ_UL Opaque me...

Page 183: ...ped to different address locations according to following device specific registers 14 5 1 NTMA Control Register Register name NTMA_CTRL Reset value 0x0000_0000 Register offset 0x068 Bits 7 6 5 4 3 2 1 0 31 24 NTMA_LBA 23 16 NTMA_LBA Reserved 15 08 Reserved 07 00 Reserved NTMA_ RMP Reserved Bits Name Description Type Reset value 31 20 NTMA_LBA NTMA primary lower base address R W 0x0 19 04 Reserved...

Page 184: ...its 7 6 5 4 3 2 1 0 31 24 NTMA_UBA 23 16 NTMA_UBA 15 08 NTMA_UBA 07 00 NTMA_UBA Bits Name Description Type Reset value 31 00 NTMA_UBA NTMA Primary upper base address R W 0x0 Register name NTMA_SEC_LBASE Reset value 0x0000_0000 Register offset 0x070 Bits 7 6 5 4 3 2 1 0 31 24 NTMA_LBA 23 16 NTMA_LBA Reserved 15 08 Reserved 07 00 Reserved Bits Name Description Type Reset value 31 20 NTMA_LBA NTMA Se...

Page 185: ... 7 6 5 4 3 2 1 0 31 24 NTMA_UBA 23 16 NTMA_UBA 15 08 NTMA_UBA 07 00 NTMA_UBA Bits Name Description Type Reset value 31 00 NTMA_UBA NTMA Secondary upper base address R W 0x0 Register name NTMA_SEC_LOWER_LIMIT Reset value 0x0000_0000 Register offset 0x078 Bits 7 6 5 4 3 2 1 0 31 24 NTMA_LLA 23 16 NTMA_LLA Reserved 15 08 Reserved 07 00 Reserved Bits Name Description Type Reset value 31 20 NTMA_LLA NT...

Page 186: ...in the PCI Capability Pointer Register 0x034 points to the first PCI X capabilities option while the first PCIe extended capability option is always located at 0x100 see PCIe Advanced Error Reporting Capability Register Register name NTMA_SEC_UPPER_LIMIT Reset value 0x0000_0000 Register offset 0x07C Bits 7 6 5 4 3 2 1 0 31 24 NTMA_ULA 23 16 NTMA_ULA 15 08 NTMA_ULA 07 00 NTMA_ULA Bits Name Descript...

Page 187: ...it when it delays the forwarding of a request from the PCIe Interface to the PCI X Interface due to insufficient buffer space to accept the Split Completion 0 Tsi384 has not delayed a Split Request 1 Tsi384 delayed a Split Request Note The Tsi384 does not support this feature this bit always returns a 0 R 0 20 SCO Split Completion Overrun The Tsi384 sets this bit when it terminates a Split Complet...

Page 188: ...mpletion transaction initiated by the bridge on the PCI X Interface results in a Master Abort or a Target Abort The Tsi384 discards the Split Completion 0 No Split Completion has been discarded 1 Split Completion is discarded R W1C 0 17 CAP133 133 MHz Capable This bit is hardwired to 1 because the Tsi384 can operate at 133 MHz on the PCI X Interface R 1 16 D64 64 bit Device This bit indicates the ...

Page 189: ... feature this bit always returns a 0 R 0 20 SCO Split Completion Overrun The Tsi384 sets this bit when it is unable to return Completion header and or data Flow Control credits to the transmitter due to insufficient buffer space for additional completions that are expected by the bridge The Tsi384 does not set this bit if no additional completions are expected for example the bridge is operating w...

Page 190: ...gned to this bridge by the upstream PCIe device The Tsi384 uses this number as described for the Function Number field Each time the bridge is addressed by a PCIe Type 0 Configuration Write Request it must update this field with the contents of the Device Number field of the Configuration Write Request regardless of which register in the bridge is addressed by the transaction R 0x00 02 00 FUNC_NUM...

Page 191: ...LMT Split Transaction Commitment Limit The value programmed in this field is used as the buffer size in ADQs for forwarding requests from the secondary bus interface Software can program any value greater than or equal to Split Transaction Capacity After reset this field takes the value of Split Transaction Capacity R W 0x0020 15 0 SPLIT_CAP Split Transaction Capacity This field is hardwired to 0x...

Page 192: ...LIT_LMT Split Transaction Commitment Limit The value programmed in this field is used as the buffer size in ADQs for forwarding requests from the primary bus interface Software can program any value greater than or equal to Split Transaction Capacity After reset this field takes the value of Split Transaction Capacity R W 0x0004 15 0 SPLIT_CAP Split Transaction Capacity This field is hardwired to ...

Page 193: ...hat indicates how auxiliary power is routed to the Tsi384 device in the system Given the right power supplies the Tsi384 can assert the PME signals in D3COLD In the absence of Serial EEPROM information the Tsi384 will report PME support for power levels down to D3HOT RE 01111 26 D2_SP D2 Support This field always returns 0 since the Tsi384 does not support the D2 power management state R 0 25 D1_S...

Page 194: ...dicating it supports the PCI Bus Power Management Interface Specification Revision 1 2 R 011 15 8 NXT_PTR Next Pointer This field points to the next capability option PCIe Capabilities Register 0x0C0 R 0xC0 7 0 CAP_ID Capability ID This field contains the value 0x01 indicating a power management capability option R 0x01 Continued Bits Name Description Type Reset value ...

Page 195: ...d R 0x00 23 16 Reserved Reserved It always reads 0 R 0x0 15 PME_ST Power PME Status This field indicates whether this device can generate PME This field s value is independent of whether the Power PME Enable field is set to 1 0 No PME is being asserted by this PCI function 1 A PME status is reported by this PCI function If PME_EN is also set to 1 this PCI function is also asserting the PME signal ...

Page 196: ... generation 1 Enable PME generation R W 0 7 4 Reserved Reserved 1 It always reads 0 R 0x0 3 NO_SOFT_RST Power No Soft Reset This field indicates whether the device needs a soft reset after transitioning from D3HOT to D0 This field always returns 1 indicating a soft reset is not required R 1 2 Reserved Power Reserved 0 It always reads 0 R 0 1 0 PWR_ST Power State This field determines the current p...

Page 197: ...0 No EEPROM 01 9 bit address 10 16 bit address Note A blank EEPROM is indicated with 0b00 If this occurs these bits must be written with the appropriate values before the EEPROM can be accessed R W Undefined 25 BUSY This bit indicates the serial EEPROM is busy with Read Write operation Software must poll this bit before initiating a write read to the external EEPROM through a configuration write t...

Page 198: ...MSK_1 Reserved 15 08 Reserved 07 00 Reserved Bits Name Description Type Reset Value 31 30 Reserved Reserved R 0 29 DEVMSK_13 Device Mask 13 0 Rerouting disabled for device 13 1 Block assertion of PCI_AD Pin 29 for configuration transactions to device 13 assert pin PCI_AD Pin 31 instead R W 0 28 26 Reserved Reserved Masking for devices 12 11 and 10 is not implemented Operation of the Tsi384 is unaf...

Page 199: ...tead R W 0 20 DEVMSK_4 Device Mask 4 0 Rerouting disabled for device 4 1 Block assertion of PCI_AD Pin 20 for configuration transactions to device 4 assert pin PCI_AD Pin 31 instead R W 0 19 18 Reserved Reserved Masking for devices 3 and 2 is not implemented Operation of the Tsi384 is unaffected by the value of these bits R 0 17 DEVMSK_1 Device Mask 1 0 Rerouting disabled for device 1 1 Block asse...

Page 200: ...r name STERM_CACHING_PERIOD Reset value 0x0000_0040 Register offset 0x0B4 Bits 7 6 5 4 3 2 1 0 31 24 ST_CACHE 23 16 ST_CACHE 15 08 ST_CACHE 07 00 ST_CACHE Bits Name Description Type Reset value 31 00 ST_CACHE Short Term caching period This field indicates the number of PCI clock cycles allowed before short term caching is discarded R W 0x0000_ 0040 ...

Page 201: ...C_R_ STAT Bits Name Description Type Reset value 31 03 Reserved Reserved R 0x0 2 SEC_DIS_STAT Secondary Discard Timer status For more information on this timer see DISCARD2 in PCI Bridge Control and Interrupt Register 0 Secondary discard timer has not expired 1 Secondary discard timer has expired R 0 1 Reserved Reserved R 0 0 SEC_R_STAT Secondary Retry timer status For more information on this tim...

Page 202: ...ter for memory read command R W 0 25 P_MRL 0 The Tsi384 prefetches one cacheline of data 1 The Tsi384 prefetches as per the value specified in MRL_66 MRL_33 fields on behalf of the PCI master for memory read line command R W 1 24 P_MRM 0 The Tsi384 prefetches two cachelines of data 1 The Tsi384 prefetches as per the value specified in MRM_66 MRM_33 fields on behalf of PCI master for memory read mu...

Page 203: ... 20 bytes 11 6 MRM_66 This bit indicates the threshold parameter for Memory read multiple command in 66 MHz PCI mode Unit is 64 byte chunk 6 h00 64 bytes 6 h01 128 bytes 6 h3F 4096 bytes R W 0x05 5 0 MRM_33 This bit indicates the threshold parameter for Memory read multiple command in 33 MHz PCI mode Unit is 64 byte chunk 6 h00 64 bytes 6 h01 128 bytes 6 h3F 4096 bytes R W 0x03 Continued Bits Name...

Page 204: ...he Tsi384 device does not have slot status or root port status It always reads 0 R 00000 24 SLOT_IMP PCIe Slot Implemented This field is not applicable for a bridge device It always reads 0 R 0 23 20 DP_TYPE PCIe Device Port Type This field indicates the device is a PCIe bridge device R 0111 19 16 CAP_VER PCIe Capability Version This field returns a version number of 1 indicating it supports PCIe ...

Page 205: ...t by the Set_Slot_Power_Limit Message The default value is 00 R 00 25 18 PL_VAL PCIe Captured Slot Power Limit Value In combination with the Slot Power Limit Scale value this field specifies the upper limit on power supplied by the slot Power limit in Watts calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field This value is set by the Set_Slot_Power_Lim...

Page 206: ...turns 0 since the Tsi384 does not support the L1 ASPM state R 000 8 6 L0S_LAT PCIe Endpoint L0s Acceptable Latency This field indicates the acceptable latency for transition from L0s to L0 state This field is set to 0b000 since the Tsi384 is not an endpoint R 000 5 EXT_TAG PCIe Extended Tag Field Supported This field contains the value 0 indicating 5 bit tag fields are supported R 0 4 3 PH_FUNC PC...

Page 207: ...ved PCIe Reserved It always reads 0 R 0x000 21 TRAN_PND PCIe Transaction Pending This field indicates the Tsi384 issued Non Posted Requests that have not been completed 0 No pending completion of Non Posted Requests 1 Pending completion of Non Posted Requests R 0 20 AUX_PWR_DTD PCIe Aux Power Detected This field indicates whether the Tsi384 detected AUX power The Tsi384 however does not require th...

Page 208: ...nse to Configuration Requests to the target devices below the bridge R W 0 14 12 MAX_RD_SIZE PCIe Max Read Request Size This field sets the maximum read request size for the Tsi384 as a requestor 000 128 bytes 001 256 bytes 010 512 bytes 011 1024 bytes 100 2048 bytes 101 4096 bytes 110 111 Reserved R W 010 11 EN_SNP_NREQ PCIe Enable Snoop Not Required The Tsi384 does not set the No Snoop attribute...

Page 209: ..._REQ_EN PCIe Unsupported Request Reporting Enable This field controls reporting of unsupported requests 0 No error reporting 1 Error reporting enabled R W 0 2 FTL_ERR_EN PCIe Fatal Error Reporting Enable This bit in conjunction with other bits controls sending ERR_FATAL messages for more information see Figure 21 0 No error reporting 1 Error reporting enabled R W 0 1 NFTL_ERR_EN PCIe Non Fatal Err...

Page 210: ...AP Data Link Layer Link Active Reporting Capable For a downstream port this bit must be set to 1 if the component can report the DL_Active state of the Data Link Control and Management State Machine For a hot plug capable downstream port this bit must be set to 1 For upstream ports and components that do not support this capability this bit must be hardwired to 0 Note The Tsi384 does not support D...

Page 211: ... support CLK_PWR_MGT This field always reads 0 R 0 17 15 L1_EXIT PCIe L1 Exit Latency The Tsi384 does not support the L1 ASPM state This field always returns 0 RE 000 14 12 L0S_EXIT PCIe L0s Exit Latency The Tsi384 L0s exit latency will be as 256 512ns which will be reported as 0b011 This value can be overwritten by the serial EEPROM 000 Less than 64 ns 001 64 ns to less than 128 ns 010 128 ns to ...

Page 212: ...29 DLL_LNK_ACT Data Link Layer Active This bit indicates the status of the Data Link Control and Management State Machine This bit is hardwired to 0 R 0 28 SLT_CLK_CONFIG Slot Clock Configuration This bit indicates the Tsi384 uses the same physical reference clock that the platform provides on the connector This bit can be loaded from the serial EEPROM as part of the PCB configuration information ...

Page 213: ... from the bridge side of the link Components use this common clock configuration information to report the correct L0s and L1 Exit Latencies 0 Asynchronous reference clock 1 Distributed common reference clock R W 0 5 RETRAIN PCIe Retrain Link This field is reserved for a bridge device It always reads 0 R 0 4 LNK_DIS PCIe Link Disable This field is reserved for a bridge device It always reads 0 R 0...

Page 214: ...x0E4 Bits 7 6 5 4 3 2 1 0 31 24 SEC_NP_LBASE 23 16 SEC_NP_LBASE Reserved 15 08 Reserved IO_SIZE 07 00 Reserved NP_REMA PP_EN Reserved Bits Name Description Type Reset value 31 20 SEC_NP_LBASE Secondary non prefetchable lower base R W 0x000 19 13 Reserved Reserved R 0x00 12 8 IO_SIZE This field describes how many upper bits of a downstream I O address are discarded R W 0x00 7 4 Reserved Reserved R ...

Page 215: ...7 00 SEC_NP_UBA Bits Name Description Type Reset value 31 00 SEC_NP_UBA Secondary bus non prefetchable upper base R W 0x000 Register name AR_SBPPRECTRL Reset value 0x0000_0000 Register offset 0x0EC Bits 7 6 5 4 3 2 1 0 31 24 SEC_PRE_LBA 23 16 SEC_PRE_LBA Reserved 15 08 Reserved 07 00 Reserved PRE_REM AP_EN Reserved Bits Name Description Type Reset value 31 20 SEC_PRE_LBA Secondary bus prefetchable...

Page 216: ...ister offset 0x0F0 Bits 7 6 5 4 3 2 1 0 31 24 SEC_PRE_UBA 23 16 SEC_PRE_UBA 15 08 SEC_PRE_UBA 07 00 SEC_PRE_UBA Bits Name Description Type Reset value 31 00 SEC_PRE_UBA Secondary bus non prefetchable upper base R W 0x000 Register name AR_PBNPBASEUPPER Reset value 0x0000_0000 Register offset 0x0F4 Bits 7 6 5 4 3 2 1 0 31 24 PRI_NP_UBA 23 16 PRI_NP_UBA 15 08 PRI_NP_UBA 07 00 PRI_NP_UBA Bits Name Des...

Page 217: ...n prefetchable Upper Limit Remap Register Register name AR_PBNPLIMITUPPER Reset value 0x0000_0000 Register offset 0x0F8 Bits 7 6 5 4 3 2 1 0 31 24 PRI_NP_ULA 23 16 PRI_NP_ULA 15 08 PRI_NP_ULA 07 00 PRI_NP_ULA Bits Name Description Type Reset value 31 00 PRI_NP_ULA Primary bus non prefetchable upper Limit R W 0x0000_000 0 ...

Page 218: ...ty structure or 0x000 if no other items exist in the linked list of capabilities For Extended Capabilities implemented in device configuration space this offset is relative to the beginning of PCI compatible configuration space and thus must always be either 0x000 for terminating list of capabilities or greater than 0x0FF R 0x000 19 16 CAP_VER Capability Version This field is a PCI SIG defined ver...

Page 219: ... Name Description Type Reset value 31 21 Reserved Reserved R 0x000 20 UR Unsupported Request Error Status R W1CS 0 19 ECRC ECRC Error Status R W1CS 0 18 MAL_TLP Malformed TLP Status R W1CS 0 17 RXO Receiver Overflow Status R W1CS 0 16 UXC Unexpected Completion Status R W1CS 0 15 CA Completer Abort Status R W1CS 0 14 CTO Completion Timeout Status R W1CS 0 13 FCPE Flow Control Protocol Error Status ...

Page 220: ...ved Undefined Bits Name Description Type Reset value 31 21 Reserved Reserved R 0x000 20 UR Unsupported Request Error Mask R WS 0 19 ECRC ECRC Error Mask R WS 0 18 MAL_TLP Malformed TLP Mask R WS 0 17 RXO Receiver Overflow Mask R WS 0 16 UXC Unexpected Completion Mask R WS 0 15 CA Completer Abort Mask R WS 0 14 CTO Completion Timeout Mask R WS 0 13 FCPE Flow Control Protocol Error Mask R WS 0 12 PT...

Page 221: ...AL_TLP Malformed TLP Severity R WS 1 17 RXO Receiver Overflow Severity R WS 1 16 UXC Unexpected Completion Severity Note In the PCI Express Base Specification Revision 1 1 Unexpected Completions are only reported as correctable errors this bit should not be set to 1 R WS 0 15 CA Completer Abort Severity R WS 0 14 CTO Completion Timeout Severity R WS 0 13 FCPE Flow Control Protocol Error Severity R...

Page 222: ...NFE Advisory Non Fatal Error Status R W1CS 0 12 RT_TO Replay Timer Timeout Status R W1CS 0 11 9 Reserved Reserved R 000 8 RN_RO REPLAY_NUM Rollover Status R W1CS 0 7 B_DLLP Bad DLLP Status This bit is set to indicate the following conditions Calculated CRC was not equal to received CRC R W1CS 0 6 B_TLP Bad TLP Status This bit is set to indicate the following conditions Physical layer indicated err...

Page 223: ... Reserved 23 16 Reserved 15 08 Reserved ANFE RT_TO Reserved RN_RO 07 00 B_DLLP B_TLP Reserved RXE Bits Name Description Type Reset value 31 14 Reserved Reserved R 0x00000 13 ANFE Advisory Non Fatal Error Mask R WS 1 12 RT_TO Replay Timer Timeout Mask R WS 0 11 9 Reserved Reserved R 000 8 RN_RO REPLAY_NUM Rollover Mask R WS 0 7 B_DLLP Bad DLLP Mask R WS 0 6 B_TLP Bad TLP Mask R WS 0 5 1 Reserved Re...

Page 224: ..._CAP ERR_PTR Bits Name Description Type Reset value 31 9 Reserved Reserved R 0x0000_00 8 EC_EN ECRC Check Enable 0 Disable 1 Enable R WS 0 7 EC_CAP ECRC Check Capable This bit indicates the Tsi384 can check ECRC R 1 6 EG_EN ECRC Generation Enable 0 Disable 1 Enable R WS 0 5 EG_CAP ECRC Generation Capable This bit indicates the Tsi384 can generate ECRC R 1 4 0 ERR_PTR First Error Pointer This point...

Page 225: ...2 1 0 31 24 HEADER 127 120 23 16 HEADER 119 112 15 08 HEADER 111 104 07 00 HEADER 103 96 Bits Name Description Type Reset value 31 00 HEADER 127 96 Header of TLP associated with error RS 0 Register name PCIE_HL2 Reset value 0x0000_0000 Register offset 0x120 Bits 7 6 5 4 3 2 1 0 31 24 HEADER 95 88 23 16 HEADER 87 80 15 08 HEADER 79 72 07 00 HEADER 71 64 Bits Name Description Type Reset value 31 00 ...

Page 226: ... 4 3 2 1 0 31 24 HEADER 63 56 23 16 HEADER 55 48 15 08 HEADER 47 40 07 00 HEADER 39 32 Bits Name Description Type Reset value 31 00 HEADER 63 32 Header of TLP associated with error RS 0 Register name PCIE_HL4 Reset value 0x0000_0000 Register offset 0x128 Bits 7 6 5 4 3 2 1 0 31 24 HEADER 31 24 23 16 HEADER 23 16 15 08 HEADER 15 08 07 00 HEADER 07 00 Bits Name Description Type Reset value 31 00 HEA...

Page 227: ...he Tsi384 never sets this bit R 0 12 SERR_AD SERR Assertion Detected No Header Log R W1CS 0 11 PERR_AD PERR Assertion Detected R W1CS 0 10 DTDTE Delayed Transaction Discard Timer Expired Status No Header Log R W1CS 0 9 UADD_ERR Uncorrectable Address Error Status R W1CS 0 8 UATT_ERR Uncorrectable Attribute Error Status R W1CS 0 7 UDERR Uncorrectable Data Error Status R W1CS 0 6 USCM Uncorrectable S...

Page 228: ...ge Error Mask No Header Log R WS 0 12 SERR_AD SERR Assertion Detected Mask No Header Log R WS 1 11 PERR_AD PERR Assertion Detected Mask R WS 0 10 DTDTE Delayed Transaction Discard Timer Expired Mask No Header Log R WS 1 9 UADD_ERR Uncorrectable Address Error Mask R WS 1 8 UATT_ERR Uncorrectable Attribute Error Mask R WS 1 7 UDERR Uncorrectable Data Error Mask R WS 1 6 USCM Uncorrectable Split Comp...

Page 229: ...er Log R WS 0 12 SERR_AD SERR Assertion Detected Severity No Header Log R WS 1 11 PERR_AD PERR Assertion Detected Severity R WS 0 10 DTDTE Delayed Transaction Discard Timer Expired Severity No Header Log R WS 0 9 UADD_ERR Uncorrectable Address Error Severity R WS 1 8 UATT_ERR Uncorrectable Attribute Error Severity R WS 1 7 UDERR Uncorrectable Data Error Severity R WS 0 6 USCM Uncorrectable Split C...

Page 230: ...d 15 08 Reserved 07 00 Reserved SUFEP Bits Name Description Type Reset value 31 05 Reserved Reserved R 0 04 00 SUFEP Secondary Uncorrectable First Error Pointer RS 0x00 Register name PCIE_SEC_HL1 Reset value 0x0000_0000 Register offset 0x13C Bits 7 6 5 4 3 2 1 0 31 24 TRAN_ATT 31 24 23 16 TRAN_ATT 23 16 15 08 TRAN_ATT 15 08 07 00 TRAN_ATT 07 00 Bits Name Description Type Reset value 31 00 TRAN_ATT...

Page 231: ...00 TRAN_CL TRAN_ATT 35 32 Bits Name Description Type Reset value 31 12 Reserved Reserved R 0 11 08 TRAN_CU Transaction Command Upper This value is transferred on C BE 3 0 during the second address phase of a DAC transaction RS 0x0 07 04 TRAN_CL Transaction Command Lower This value is transferred on C BE 3 0 during the first address phase RS 0x0 3 0 TRAN_ATT 35 32 Transaction Attribute This field i...

Page 232: ... the first and second address phases The first address phase is logged in this field and the second address is logged in PCIe Secondary Header Log 4 Register RS 0x0 Register name PCIE_SEC_HL4 Reset value 0x0000_0000 Register offset 0x148 Bits 7 6 5 4 3 2 1 0 31 24 TRAN_ADD 63 56 23 16 TRAN_ADD 55 48 15 08 TRAN_ADD 47 40 07 00 TRAN_ADD 39 32 Bits Name Description Type Reset value 31 00 TRAN_ADD 63 ...

Page 233: ...e 0x0000_0000 Register offset 0x208 Bits 7 6 5 4 3 2 1 0 31 24 Reserved 23 16 Reserved 15 08 REPLAY_L AT_EN REPLAY_LATENCY 07 00 REPLAY_LATENCY Bits Name Description Type Reset value 31 16 Reserved Reserved R 0 15 REPLAY_LAT_EN Replay Latency Enable R W 0 14 00 REPLAY_LATENCY Replay Latency timer value is overwritten by this value if REPLAY_LAT_EN is set to b1 R W 0x0000 ...

Page 234: ...ENCY 15 08 ACKNAK_ LAT_EN Reserved ACKNAK_LATENCY 07 00 ACKNAK_LATENCY Bits Name Description Type Reset value 31 UPDATE_LAT_EN Update Latency Enable R W 0x0 30 28 Reserved Reserved R 0 27 16 UPDATE_LATENCY Update Latency timer value is overwritten with this value if UPDATE_LAT_EN is set to b1 R W 0x009 15 ACKNAK_LAT_EN Ack Nak Latency Enable R W 0x0 14 13 Reserved Reserved R 0 12 00 ACKNAK_LATENCY...

Page 235: ...a Address Base Offset Base 0x800 Register name N_FTS Reset value 0x0000_0020 Register offset 0x210 Bits 7 6 5 4 3 2 1 0 31 24 Reserved 23 16 Reserved 15 08 Reserved 07 00 N_FTS Bits Name Description Type Reset value 31 08 Reserved Reserved R 0x0 07 00 N_FTS This register indicates the N_FTS count value to be advertised to the other end component Note This value should fall in the L0s exit latency ...

Page 236: ...ntrol Register 0x02C PCIE_PM_CTL 0 3 PCIe Pattern Matcher Control and Error Register 0x030 PCIE_SS_EC_CTL 0 3 PCIe SS Phase and Error Counter Control Register 0x034 PCIE_SCTL_FI 0 3 PCIe Scope Control and Frequency Integrator Register PCIe Clock Module Control and Status Registers 0x420 PCIE_CTL_STAT PCIe Control and Level Status Register 0x428 PCIE_CTL_OVRD PCIe Control and Level Override Registe...

Page 237: ... 300 Bits 7 6 5 4 3 2 1 0 31 24 Reserved LOS_CTL Reserved 23 16 RX_EQ_VAL Reserved RX_ALIGN _EN Reserved HALF_ RATE 15 08 Reserved TX_BOOST 07 00 TX_BOOST Reserved Bits Name Description Type Reset Value 31 30 Reserved Reserved R 01 29 28 LOS_CTL LOS filtering mode control R Undefined 27 24 Reserved Reserved R Undefined 23 21 RX_EQ_VAL Receive Equalization control R 0b010 20 Reserved Reserved R 0 1...

Page 238: ...s 7 6 5 4 3 2 1 0 31 24 OVRD Reserved TX_BOOST 23 16 TX_BOOST ReservedP 15 08 ReservedP 07 00 ReservedP LOS Reserved Bits Name Description Type Reset Value 31 OVRD Enable override of relevant bits 16 30 in this register R W 0 30 26 Reserved Reserved R W 00000 25 22 TX_BOOST Transmit Boost control Programmed boost value ratio of drive level of transition bit to non transition bit is boost 20 log 1 ...

Page 239: ...31 15 ReservedP Preserve state on writes R Undefined 14 OVRD_2 Enable override of relevant bits 0 13 in this register R W 0 13 12 LOS_CTL LOS filtering mode control 00 Disabled 01 10 Reserved 11 Heavy filtering The LOS signal is synchronous to the output of the prescaler Heavy filtering means 128 5 cycles of no signal for LOS to be asserted R W 01 11 8 ReservedP Preserve state on writes R W Undefi...

Page 240: ...MODE 15 08 Reserved 07 00 Reserved Bits Name Description Type Reset Value 31 30 Reserved Reserved R 0 29 20 PATO Pattern for modes 3 5 Program the desired pattern in these 10 bits when using modes 3 5 Note This field returns to its reset value on reset R W 0x00 19 TRIGGER_ERR Insert a single error into a LSB Note This field returns to its reset value on reset R W 0 18 16 MODE Pattern to generate 0...

Page 241: ... and COUNT 2 15 1 signals overflow of counter Note This bit may require two reads to get a stable value a a Read operation on this register is pipelined Two reads may be needed to get current value The value is volatile that is the value may change at any time The second read resets the counter R W Undefined 30 16 COUNT Current error count If OV14 field is active then multiply count by 128 a R W U...

Page 242: ...VAL DTHR 15 08 OV14 COUNT 07 00 COUNT Bits Name Description Type Reset Value 31 28 Reserved Reserved R 0 27 17 SS_PVAL Phase value from zero referencea a Read operation on this register is pipelined Two reads may be needed to get current value The value is volatile that is the value may change at any time The second read resets the counter R W 0x000 16 DTHR Bits below the useful resolutiona R W 0 ...

Page 243: ...234 334 Bits 7 6 5 4 3 2 1 0 31 24 Reserved 23 16 Reserved 15 08 Reserved FVAL 07 00 FVAL DTHR_F Bits Name Description Type Reset Value 31 14 Reserved Reserved R W 0 13 1 FVAL Frequency is 1 526 VAL ppm from the reference Value is a signed integer format 2 s complement Note This field may require two reads to get a stable value R W 0 0 DTHR_F Bits below the useful resolution Note This bit may requ...

Page 244: ...lid Register name PCIE_CTL_STAT Reset value Undefined Register offset 0x420 Bits 7 6 5 4 3 2 1 0 31 24 Reserved TX_LVL LOS_LVL 23 16 LOS_LVL ACJT_LVL 15 08 Reserved 07 00 Reserved Bits Name Description Type Reset Value 31 Reserved Reserved R 1 30 26 TX_LVL Fine Resolution setting of Tx signal level Equation Pk Pk output level without attenuation 1230 x 48 tx_lvl 2 63 5 mV Vdiff pp Note TX_LVL shou...

Page 245: ...6 TX_LVL Fine Resolution setting of Tx signal level Equation Pk Pk output level without attenuation 1230 x 48 tx_lvl 2 63 5 mV Vdiff pp Note TX_LVL should be set to 0x1010 which results in an output of 1Vp p For more information on available settings see Table 44 R W 0x10 25 21 LOS_LVL Loss of Signal Detector level R W 0x10 20 16 ACJT_LVL AC JTAG Receiver Comparator level This sets the hysteresis ...

Page 246: ...5 b01110 1065 4 15 0xF 5 b01111 1075 0 16 0x10 5 b10000 1084 7 17 0x11 5 b10001 1094 4 18 0x12 5 b10010 1104 1 19 0x13 5 b10011 1113 8 20 0x14 5 b10100 1123 5 21 0x15 5 b10101 1133 1 22 0x16 5 b10110 1142 8 23 0x17 5 b10111 1152 5 24 0x18 5 b11000 1162 2 25 0x19 5 b11001 1171 9 26 0x1A 5 b11010 1181 6 27 0x1B 5 b11011 1191 3 28 0x1C 5 b11100 1200 9 29 0x1D 5 b11101 1210 6 30 0x1E 5 b11110 1220 3 3...

Page 247: ... Maximum Ratings PCI Symbol Parameter Minimum Maximum Units TSTG Storage temperature 55 125 o C TC Case temperature under bias 40 120 oC Voltage with respect with ground VDD 1 2V DC core logic supply voltage 0 5 2 0 V VDD_PCIE 1 2V DC PCIe digital supply voltage 0 3 1 7 V VDDA_PLL 1 2V DC PLL analog supply voltage 0 5 2 0 V VDD_PCI 3 3V DC I O supply voltage 0 5 4 1 V VDDA_PCIE 3 3V DC PCIe analog...

Page 248: ...ce for Charged Device Model CDM Test Conditions per JEDEC standard JESD22 C101 A 500 V Table 47 Recommended Operating Conditions Symbol Parameter Minimum Maximum Units Notes VDD_PCI 3 3V DC I O supply voltage 3 0 3 6 V VDDA_PCIE 3 3V DC PCIe supply voltage 3 0 3 6 V VDD 1 2V DC core supply voltage 1 14 1 26 V VDD_PCIE 1 2V DC PCIe digital supply voltage 1 14 1 26 V VDDA_PLL 1 2V DC PLL supply volt...

Page 249: ... power and current measurements Avg Current mA Typ Max Typ Max 133 MHz VDD_PCI 3 3V I O power for PCI X and 3 3V I O power for CMOS 0 38 0 73 115 6 220 0 VDD_PCIE 1 2V power for SerDes 0 13 0 15 105 1 127 4 VDDA_PLL 1 2V analog power for PLL 0 01 0 02 10 0 12 1 VDDA_PCIE 3 3V analog power for SerDes 0 18 0 23 53 3 70 9 VDD 1 2V core power 0 60 0 73 502 9 611 2 PTOTAL Total chip power 1 30 1 86 66 ...

Page 250: ...tage IOH 0 9VDD_PCI V VOH_33 3 3 CMOS Output High Voltage IOH 6mA VDD_PCI 0 5 V VOL_33 3 3 CMOS Output Low Voltage IOL 6mA 0 4 V VIH_33 3 3 CMOS Input High Voltage 2 VDD_PCI 0 5 V VIL_33 3 3 CMOS Input Low Voltage 0 5 0 8 V CIN_PCI Input Pin Capacitance 8 8 pF CCLK_PCI Clock Pin Capacitance PCI_CLK 7 5 pF LIN_PCI Input Pin Inductance 8 3 nH LCLK_PCI Clock Pin Inductance PCI_CLK 4 9 nH Table 50 PCI...

Page 251: ... AC Specifications for PCI X Interface Symbol Parameter PCI X 133 PCI X 66 PCI 66 PCI 33 Units Notes Min Max Min Max Min Max Min Max TOV1 Clock to Output Valid Delay for bused signals 0 7 3 8 0 7 3 8 2 6 2 11 ns a b c TOV2 Clock to Output Valid Delay for point to point signals 0 7 3 8 0 7 3 8 2 6 2 12 ns a b c TOF Clock to Output Float Delay 7 7 14 28 ns a d TIS1 Input Setup to clock for bused sig...

Page 252: ...ecification e See the timing measurement conditions in Figure 44 f Setup time applies only when the device is not driving the pin g All output drivers must be floated when PCIE_PERSTn is active h The Tsi384 acts as the central resource and will drive REQ64 low during reset since it is a 64 bit bridge Table 52 PCIe Differential Transmitter Output Specification Symbol Parameter Min Nom Max Units Com...

Page 253: ...VTX D VTX D 2 VTX CM DC VTX CM DC DC AVG of VTX D VTX D 2 See Note 2 VTX CM DC ACTIVE IDLE DELTA Absolute Delta of DC Common Mode Voltage During L0 and Electrical Idle 0 100 mV VTX CM DC during L0 VTX CM DC during electrical idle 100mV VTX CM DC DC AVG of VTX D VTX D 2 L0 VTX CM idle DC DC AVG of VTX D VTX D 2 Electrical Idle See Note 2 VTX_CM LINE DELTA Absolute Delta of DC Common Mode Voltage be...

Page 254: ... to transition to valid TX specifications after leaving an Electrical Idle condition 20 UI Maximum time to meet all TX specifications when transitioning from Electrical Idle to sending differential data This is considered a de bounce time for the TX to meet all TX specifications after leaving Electrical Idle RLTX DIFF Differential Return Loss 10 dB Measured over 50 MHz to 1 25 GHz See Note 4 RLTX ...

Page 255: ...be met using the compliance pattern at a sample size of 1 000 000 UI 4 The Transmitter input impedance shall result in a differential return loss greater than or equal to 10 dB with a differential test input signal no less than 200mV peak value 400 mV differential peak to peak swing around ground applied to D and D lines and a common mode return loss greater than or equal to 6 dB over a frequency ...

Page 256: ...Manual May 5 2014 Integrated Device Technology www idt com Figure 41 Transmitter Eye Voltage and Timing Diagram1 1 This diagram is an excerpt from PCI Express Base Specification Revision 1 1 Revision 1 1 Transmitter Compliance Eye Diagrams page 225 ...

Page 257: ...R Maximum time between the jitter median and maximum deviation from the median 0 3 UI Jitter is defined as the measurement variation of the crossing points VRX DIFF 0V in relation to recovered TX UI To be measured after the clock recovery function in Section 4 3 3 2 of the PCI Express Base Specification Revision 1 1 See Notes 8and 9 VRX CM ACp RMS AC Peak Common Mode Input Voltage 150 mV VRX CM AC...

Page 258: ...ferential test input signal of no less than 200 mV peak value 400mV differential peak to peak swing around ground applied to D and D lines and a common mode return loss greater than or equal to 6 dB no bias required over a frequency range of 50 MHz to 1 25 GHz This input impedance requirement applies to all valid input levels The reference impedance for the return loss measurements is 50 Ohms to g...

Page 259: ... 5 2014 Integrated Device Technology www idt com Figure 42 Minimum Receiver Eye Timing and Voltage Compliance Specification1 1 This diagram is an excerpt from PCI Express Base Specification Revision 1 1 Differential Receiver RX Input Specifications page 230 ...

Page 260: ...ith respect to 100 MHz based on the PCIe Specification Fin_DC Reference Clock Duty Cycle 40 50 60 JCLK REF Total Phase Jitter rms 3 psrms See a a Total Permissible Phase Jitter on the Reference Clock is 3 ps rms This value is specified with assumption that the measurement is performed with a 20 GSamples s scope with more than 1 million samples The zero crossing times of each rising edges are recor...

Page 261: ... ns 0 8V to 2 0V a TBSCF JT_TCK Fall Time 25 ns 2 0V to 0 8V a TSIS1 Input Setup to JT_TCK 10 ns b b See Figure 44 TBSIH1 Input Hold from JT_TCK 10 ns b TBSOV1 JT_TDO Output Valid Delay from falling edge of JT_TCK 15 ns c d c Outputs precharged to VDD33 d See Figure 45 TOF1 JT_TDO Output Float Delay from falling edge of JT_TCK 15 ns c e e A float condition occurs when the output current becomes le...

Page 262: ...rms for the Tsi384 Figure 44 Input Timing Measurement Waveforms PCI_CLK clock stable to de assertion of device reset 100 us Power up strapping hold from de assertion of device reset 0 ns THIZ Assertion of reset to outputs tri state 10 ns Table 56 Reset Timing Continued Symbol Parameter Min Max Units Notes CLK INPUT Valid Vtest Vtest Vtest TIS TIH Vtl Vth Vth Vtl Vmax ...

Page 263: ...t com Figure 45 Output Timing Measurement Waveforms Figure 46 PCI X TOV max Rising Edge AC Test Load Figure 47 PCI X TOV max Falling Edge AC Test Load Vtest CLK OUTPUT FLOAT Vtrise OUTPUT DELAY RISE OUTPUT DELAY FALL Vtfall TOV TOV TOF Vtl Vth Output Test Point 10pF 25 Output 10pF 25 VCC33 Test Point ...

Page 264: ...15 Electrical Characteristics 264 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com Figure 48 PCI X TOV min AC Test Load Output Test Point 10pF 1K 1K VCC33 ...

Page 265: ...mal Characteristics Moisture Sensitivity 16 1 Mechanical Diagram Figure 49 Mechanical Diagram 256 pin 17x17mm BGA Note 1 All dimensions are in millimeters 2 Dimensionning and tolerencing per ASME Y14 5 1994 3 Dimension is measured at the maximum solder ball diameter paralllel to Datum C 4 Datum C is defined by the sperical crowns of the solder balls ...

Page 266: ...ows the simulated thermal characteristic JB and JC of the Tsi384 package Table 57 Thermal Characteristics Table 58 shows the simulated Junction to Ambient JA characteristics of the Tsi384 The thermal resistance JA characteristics of a package depends of multiple variables other than just the package In a typical application designers must take into account various system level and environmental ch...

Page 267: ... of the Tsi384 with a 0 m s airflow can be determined using the following formula TJ JA P TAMB Where TJ is the Junction temperature P is the Power consumption TAMB is the Ambient temperature Assuming a Power consumption of 1 5W and Ambient temperature of 85 C the resultant Junction temperature would be 116 4 C 16 3 Moisture Sensitivity The moisture sensitivity level MSL for the Tsi384 is 3 ...

Page 268: ...16 Packaging 268 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com ...

Page 269: ...ct number may be three or four digits SS S Maximum operating frequency or data transfer rate of the fastest interface For operating frequency numbers M and G represent MHz and GHz For transfer rate numbers M and G represent Mbps and Gbps Table 59 Part Numbers Part Number Frequency Temperature Package Pin Count Tsi384 133ILV 133 MHz Industrial RoHS Green 256 Tsi384 133IL 133 MHz Industrial Eutectic...

Page 270: ... products contain only one of the six restricted substances Lead Pb These flip chip products are RoHS compliant through the Lead exemption for Flip Chip technology Commission Decision 2005 747 EC which allows Lead in solders to complete a viable electrical connection between semiconductor die and carrier within integrated circuit Flip Chip packages V RoHS Compliant Green These products follow the ...

Page 271: ...trolled through TX_LVL in the PCIe Control and Level Override Register and TX_BOOST in the PCIe Output Status and Transmit Override Register see Figure 50 The transmit boost functionality can be programmed by TX_BOOST in the PCIe Output Status and Transmit Override Register The TX_BOOST field controls the drive level of subsequent non transitional bits with respect to the transitional ones The amo...

Page 272: ...internally boosted by configuring RX_EQ_VAL in the PCIe Receive and Output Override Register The equation that uses the 3 bit field is listed below Receiver boost RX_EQ_VAL 1 0 5 dB For example setting RX_EQ_VAL 2 0 3 b100 results in a 2 5dB boost of the received signal This boost is internal to the device and increases the eye opening when the signals arriving at the pins are degraded 0 75 V TX_L...

Page 273: ... address of a transaction falls within the window defined by a device s base and limit registers the device claims the transaction Base and Limit registers are used only by transparent bridges CompactPCI cPCI It is an adaptation of the PCI Local Bus Specification Revision 2 2 for Industrial and or embedded applications that require a more robust mechanical form factor than desktop PCI Completer PC...

Page 274: ...spaces to be connected through defined windows with address translation from one memory domain to another PCI extended capabilities Optional features supported by the PCI Local Bus Specification Some examples of extended capabilities include Vital Product Data Message Signaled Interrupts and Slot Numbering A device that supports extended capabilities uses a PCI capability list to access the featur...

Page 275: ...n PCI X Transparent addressing This type of PCI addressing is used by a bridging device to support configuration mapping but not perform address translation between two buses When a device is configured in transparent mode it provides standard PCI bus bridging support through its base and limit registers These registers define address decode windows for multiple bridges so that transactions can be...

Page 276: ...276 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com ...

Page 277: ...o special cycle 60 Type 1 to Type 0 59 Type 1 to Type 1 60 D D state transitions 126 D0 state 125 D3cold state 125 D3hot state 125 DC and operating characteristics 250 device power states 125 device register map 147 document conventions document status 16 numeric conventions 16 symbols 16 downstream data path 38 non transparent registers 214 E ECRC error 86 EEPROM controller 129 EEPROM device 130 ...

Page 278: ...tics 249 power management 121 power management event 126 power states 122 power supply sequencing 249 prefetchable memory addressing 47 prefetching algorithm 43 R recommended operating conditions 248 register map 147 requestor ID 64 reset PCI 113 PCIe 112 round robin arbitration 76 S SerDes TAP controller 141 short term caching 44 split completion message with completer errors 100 system errors 10...

Page 279: ...Index 279 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com data path 37 non transparent registers 183 V VGA addressing 50 W warm reset 112 ...

Page 280: ...Index 280 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com ...

Page 281: ...d herein is provided without representation or warranty of any kind whether express or implied including but not limited to the suitability of IDT s products for any particular purpose an implied warranty of merchantability or non infringement of the intellectual property rights of others This document is presented only as a guide and does not convey any license under intellectual property rights ...

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