iDEN iO1000 Detailed Service Manual Download

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iO1000 Detailed Service Manual - THEORY OF OPERATION

Figure 14. REDCAP Diagram

SIM(5)

STDB

SRDB

SFSB(2)

SCKB(2)

STDA

SRDA

SFSA(2)

SCKA(2)

MOSI

MISO

SCK

SPICS(5)

ADRS(22)

DATA(16)

R/W

EB0, EB1

CS(6)

MOD

INT(6)

INT6/DRS/

STDA/TRST

INT7/DTR/SCLK/

SRDA/TMS

RST_OUT

RST_IN

COLUMN(5)

ROW5/IC2B/GPIO

COL

UMN6/OC1

COL

UMN5/GPIO

COL

UMN7/PWM

ROW6/DCD/SCA2A/DSP_DE

ROW7/RI/SCKA/TCK

ROW(5)

Baseband

CODEC

Serial Port

BBP

Counter

Audio

CODEC

Serial Port

SAP

DSP Timer

BRM

QSPI

SIM

External

Interface

Module

RESET

RAM (512 x 32)

ROM (4k x 32)

MCU Timers/PWM/

PIT/Watchdog

MCU

Core

Peripheral I/F Gaskat

PIG

GPReg

DSP_IRQ

YROM 9Kx16

YRAM 8Kx16

XROM 9Kx16

XRAM 7Kx16

Shared X/MCU RAM1Kx16

Clocks/PLL

Layer 1

Timer

MCU

Debug

JTAG/OnCE

UART

MUX

PROM (48K x 24)
(24K x 24)

PRAM (512 x 24)

(24K x 24)

CKIH,CKIL

CKOH,CKO

TOUT(8)

DEBUG(6)

DSP_DE
JTAG(5)
MCU_DE
TEST

RTS/IC2A/
RESET_IN

MUX_CTL

CTS/MCU_DE

TX/TDO

RX/IC1/TDI

MCU Int. Ctl

MCU/DSP

Interface

MDI

DSP

Core

Keypad

Interface

GPIO

REDCAP FUNCTIONAL BLOCK DIAGRAM

Summary of Contents for iO1000

Page 1: ...iO1000 Wireless Modem Detailed Service Manual 7 OCT 1999 68P02953C80 O...

Page 2: ...implication estoppel or otherwise any license under the copyrights patents or patent applications of Motorola except for the normal non exclusive royalty free license to use that arises by operation...

Page 3: ...da Safety Code 6 Antenna and Installation Considerations All equipment must be properly installed in accordance with Motorola installation instructions To assure compliance with United States FCC regu...

Page 4: ...ory Mutual Approved Sparks in a potentially explosive atmosphere can cause an explosion or fire resulting in bodily injury or even death Note The areas with potentially explosive atmospheres referred...

Page 5: ...size shape and deployment area can vary by vehicle make model and front compartment configuration for example bench seat vs bucket seats Contact the vehicle manufacturer s corporate headquarters if ne...

Page 6: ...expo sure requirements must reflect product usage posi tioning of the iO1000 within the product the type of antenna used the location of the antenna and other factors that may vary with the design and...

Page 7: ...ttery 40 C to 85 C Channel Spacing 25 kHz Frequency Stability Supply Voltage Frequency Stability Locked to base 0 2 ppm Nominal 3 6 Vdc Locked to base 0 2 ppm Not locked to base 5 ppm Range 3 4 to 3 8...

Page 8: ...MODEL SPECIFICATIONS FOR F2581A viii...

Page 9: ...ion section in the front of this manual Digital Modulation Technology The iO1000 is an 806 866 MHz unit that can operate in three modes dispatch interconnect and multi service It uses two digital tech...

Page 10: ...e for each unit Time allocation enables each unit to transmit its voice information without interference from another unit s transmission Transmission from a unit or base station is accommodated in ti...

Page 11: ...ty Voice compression reduces the number of bits per second while maintaining the voice at an acceptable quality level The iDEN system uses a coding technique called Vector Sum Excited Linear Predictio...

Page 12: ...nnel is created by grouping bursts so that their slot numbers differ by a number referred to as the repetition rate The portable uses two repetition rates for interconnect voice calls 6 1 and 3 1 A si...

Page 13: ...m Description The below figure shows the hardware block diagram of the iO1000 OEM Module This module includes two boards RF and Logic Figure 3 RF and Logic Connection Diagram RF Board The RF board is...

Page 14: ...carrier with baseband data signal 2 Receive Demodulation of received RF signal to generate baseband signal 3 Frequency Synthesizer Channels 806 825 MHz TX and 851 870 MHz RX Logic Board The Logic Boa...

Page 15: ...o ADDAG at a rate of 48 K samples per second The ADDAG provides the serial clock to the DSP and a frame sync pulse to tell the DSP to send a sample Each sample is sent as a 16 bit I word followed by a...

Page 16: ...ransmitter it incorporates an offset synthesizer and all of the circuitry necessary to implement a cartesian feedback closed loop system The iZIF offset synthesizer phase locks an external VCO at 301...

Page 17: ...DAG The gain is tuned at the factory and should not require any adjustment any change in the loop gain can result in the transmitter splattering into the adja cent channel The PA is turned on by suppl...

Page 18: ...AB PA is used for better efficiency and longer battery life The class AB PA is fairly linear but not totally and this causes splatter in the RF spectrum around the transmitted frequency band To reduce...

Page 19: ...RATION Power amplifier Isolator Antenna switch The feedback path includes the following Feedback inductor Attenuator ODCT ASIC Figure 5 Cartesian Loop Amplitude Adjust I Q LO DOWNMIXER 0 90 Phase Adju...

Page 20: ...signal level from exceeding the ramp level which caused the clip The ramp is allowed to decay to zero Figure 6 Level Set Training Negative feedback is required to maintain system stability Phase trai...

Page 21: ...igure 8 on page 14 It operates in the commercial portion of the land mobile receiver band 851 866 MHz The receiver takes an incoming RF signal down converts it to a filtered109 65 MHz frequency IF sta...

Page 22: ...ut to IF output The mixer LO drive is provided from the VCO buffer in the frequency generation portion of the unit The LO drive is provided to the mixer through a saw filter 3 Pole Crystal Filter The...

Page 23: ...order intercept point The next stage in the iZIF lineup is the down conversion mixer This is a quadra ture type of mixer Its inputs are the IF and second LO signals see Second Local Oscillator LO on...

Page 24: ...ch mixes it down to baseband I and Q This information is sent to the ADDAG IC for digitizing prior to sending it to the DSP Frequency Generator RF Section This section contains the following main comp...

Page 25: ...n LO The output of the detector is the control volt age for the main VCO The feedback loop keeps the receive and transmitter fre quencies locked and allows frequency transitions in a short period of t...

Page 26: ...the other synthesizers The crystal based reference oscil lator temperature compensation and frequency error correction is provided by the LV Frac N synthesizer This 16 8 MHz signal is sent to all the...

Page 27: ...er inside the iZIF in the receiver lineup see iZIF IC on page 15 The second LO consists of a VCO loop divider phase detector reference fre quency and loop filter The loop divider and phase detector ar...

Page 28: ...and RSSI signals coming from the iZIF IC To help maximize dynamic range and noise performance these three input signals are fully differential and therefore require a total of six pins on the ADDAG I...

Page 29: ...rcuitry DC voltage distribution Audio circuitry Digital REDCAP and associated circuitry Transmitter path Receiver path Frequency generating RF The keypad contains the high audio speaker microphone and...

Page 30: ...eral interface read write interface Auxiliary battery switch control 100 pin dual die QFP IC package The GCAP II IC is designed to support the needs of portable cellular telephone products It provides...

Page 31: ...ulator supplies 1 875Vdc to the DSP and MCU cores Additionally an external 3 0Vdc linear regulator on the logic board supplies power to the accessories Several sections of the radio are connected dire...

Page 32: ...REG V1 2 775V 60mA GCAP II LINEAR REG V3 1 875V 120mA GCAP II Vref tracks V2 2 775V 5mA Fuse LM2981 3 0V 100mA RAW_B Raw_B LM2664 2 775V Inverter ODCT Super Filter 2 775V 30mA Drain Switch ODCT Up mix...

Page 33: ...core for further processing Received analog signals are converted to digital signals by the ADDAG then sent to the DSP for processing The DSP then sends the processed signals to the CODEC where they a...

Page 34: ...e integrated circuits located in the RF section Within the REDCAP is the DSP and the serial communication interface The digital section contains the following Figure 13 REDCAP Power On Off circuitry S...

Page 35: ...C archi tecture high performance and high code density SPS 56600 NDE UL DSP core running up to 58 8 MHz at 1 8Vdc Fully programmable PLL for system clock generation with low output clock drivers FLASH...

Page 36: ...heral interface to communicate with external peripherals Serial communications interface with baud rate generator up to 525 kbps On chip Emulator OnCE integrated with JTAG port compliance Interrupt ge...

Page 37: ...al Port BBP Counter Audio CODEC Serial Port SAP DSP Timer BRM QSPI SIM External Interface Module RESET RAM 512 x 32 ROM 4k x 32 MCU Timers PWM PIT Watchdog MCU Core Peripheral I F Gaskat PIG GPReg DSP...

Page 38: ...nit When the ON OFF pin J4 17 is held high the GCAP II turns on The GCAP internal low voltage detector provides the initial active low reset to the RISC microprocessor MCU After the VCC3 arrives at th...

Page 39: ...ipherals support many memory and peripheral configurations Serial Peripheral Interface SPI This interface communicates with RF chips using a synchronous serial bus This bus includes the following Mast...

Page 40: ...hen both EB0 and EB1 are driven low Accessory Connector Signal MUX The RCE uses the three serial protocols UART SB9600 and JTAG to communi cate to external devices through the bottom connector of the...

Page 41: ...8 MHz and the DSP PLL is programmed to generate a higher operating frequency The DSP PLL runs at 58 8 MHz Host System Clock Synthesizer During initial power up the host system clock RCE is synthesized...

Page 42: ...M 11 AUDIO _COMMON Analog Ground 12 AUDIO_OUT OUT Audio Out from OEM 13 OPT_SELECT_1 I O 10 27K pull up OEM Configuration 14 OPT_SELECT_2 I O 10 27K pull up OEM Configuration 15 MUX_CNTL IN 100K pull...

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