THEORY OF OPERATION: Digital Section
32
Host Memories
The following types of host memories are available:
Flash memory
1MB x 16 chip. The flash stores unit subscriber and
DSP code. To access the flash, the RCE asserts CS0
and OE low, and then drives EB1 high for reads. For a
write, OE is held high, CS0 and EB1 and driven low.
Host SRAM memory
128 KB x 16 SRAM is used by the RCE to load code-
plug information, program the flash, and store working
parameters. To access SRAM memory, R/W is held
high, the RCE asserts CS2 and OE low, and then drives
EB1 and EB0 low for reads. For a write, CS2 and R/W
are asserted low, and then both EB0 and EB1 are
driven low.
Accessory Connector Signal MUX
The RCE uses the three serial protocols: UART, SB9600, and JTAG to communi-
cate to external devices through the bottom connector of the unit.
There is no external hardware for switching from one protocol to another because
the REDCAP handles the switching and line multiplexing functions internally
Clock Buffers
High frequency clock (16.8MHz) is generated in LVFrac-N in RF Board. Its
amplitude is too low to drive Redcap and GCAP ICs. Therefore, two buffers, one
for GCAP, the second for REDCAP IC, amplify the clock signals to the levels
required by these ICs. GCAP requires a minimum of 700mVp-p clock signal,
while REDCAP requires 285mVp-p signal to function properly. GCAP buffer has
a contorl signal, so that its clock can be stopped to save power.
