IDEC SmartRelay FL1A-H12RCE, Manual

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IDEC SmartRelay Functions
4-7
IDEC SmartRelay User’s Manual
Timing diagram for AND with RLO edge detection
4.2.3 NAND (AND Not)
The parallel connection of a number
of normally closed contacts is repre-
sented in a circuit diagram as
Symbol in IDEC SmartRelay:
The output of NAND only adopts the state 0 if all the inputs
have the state 1 (i.e. they are closed).
If an input pin of this block is not wired (x), then the
following applies to the input: x = 1.
Logic table for NAND
1 2 3 Q
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
1
3
Q
2
Cycle
1 2 3 4 5 6
7 8 9 10