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26: L
ON
W
ORKS
I
NTERFACE
M
ODULE
26-14
O
PEN
N
ET
C
ONTROLLER
U
SER
’
S
M
ANUAL
L
ON
W
ORKS
Interface Module Internal Structure
The L
ON
W
ORKS
interface module block diagram is illustrated in the figure below:
Memory Map
The L
ON
W
ORKS
interface module memory map is illustrated in the figure below:
Flash Memory
The L
ON
W
ORKS
interface module contains a 32KB nonvolatile rewritable memory. Of the 32KB memory area, a 16KB
area of 0000h through 3FFFh is allocated to the Neuron Chip firmware, and the remaining 16KB area of 4000h through
7FFFh is allocated to the application program.
Link Register
Flash
Memor y
Status LED
Ser vice Request Button
Neuron Chip 3150
Transceiver
FTT-10A
Failure
SERVICE
RUN
IO.0
ERR
IO.1
I/O
IO.2
CPU Module
LED
LED
LED
L
ON
W
ORKS
Interface Module
RUN
IO.6
IO.4
L
ON
W
ORKS
Network
Register
SER
LED
Neuron Chip 3150 (6KB)
FFFFh
Unused
Register (4KB)
Unused
Application
Program
(16KB)
Neuron Chip
Firmware
(16KB)
Flash
Memor y
(32KB)
E800h
CFFFh
C000h
7FFFh
4000h
3FFFh
0000h
Reser ved for Memor y
Map I/O (1KB)
Reser ved (2.5KB)
EEPROM (0.5KB)
RAM (2KB)
FFFFh
FC00h
F1FFh
F000h
E800h
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