Manual Number: 00431-220-5
Page A-14
SB586T Series Manual
NA Disabled (NAD) for Ext Cache
Set this option to ENABLED to disable NAD for L2 secondary (external) cache memory. The
settings are ENABLED or DISABLED
.
The optimal and fail-safe default settings are
ENABLED.
Peer Concurrency
Set this option to ENABLED to enable PCI peer-to-peer concurrency. The settings are ENABLED
or DISABLED
.
The optimal and fail-safe default settings are
ENABLED.
DRAM Integrity Mode
Use this option to set the system memory integrity mode. The settings are PARITY, ECC LEVEL1,
ECC LEVEL2, or DISABLED. The PARITY setting allows parity checking for system memory.
LEVEL 1 ECC provides the minimal level of ECC support using the system's standard NMI (non-
maskable interrupt) routine. LEVEL2 ECC adds error scrubbing of correctable errors using operat-
ing-system-independent mechanisms such as SMIs (system management interrupts). The optimal
and fail-safe default settings are
DISABLED
.
PCI 2.1 Passive Release Enable
Set this option to ENABLED to enable the PCI passive release feature defined in Version 2.1 of the
PCI specification. The settings are ENABLED or DISABLED
.
The optimal and fail-safe default
settings are
ENABLED.
Delayed Transaction Enable
Set this option to ENABLED to enable the delayed transaction feature. The settings are EN-
ABLED or DISABLED
.
The optimal and fail-safe default settings are
ENABLED.
North Bridge Retry Enable
The 430HX chipset involves the TXC (North Bridge chip) and the PIIX3 (South Bridge chip). North
Bridge Retry Enable is used to enable delayed transactions between the North and South Bridge
chips of the chipset. The settings are ENABLED or DISABLED. The optimal and fail-safe default
settings are
ENABLED.