Hughes JVC 100, Service Manual

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Chapter 2---System Description
Model 100 Service Manual 2-35
Figure 2-14 I/O diagram of Raster Timing Generator section of SC/RTG PCB.
Output
The RTG will disable the Horizontal Deflection Board by placing a high on the
/H_ENABLE line during any of following events:
!
A. During and about 2 seconds after the programming period of the
FPGA.
!
B. During frequency band change period.
!
C. During the period that the phase locked loop is out of lock.
Deflection Processor PCB
The Deflection Processor PCB is the circuit board directly above the System
Controller/ Raster Timing Generator in the Electronics Module card cage (see
figure 4-10). The following functions are performed by or controlled by the
Deflection PCB:
!
Controls the ILA
®
Bias and Frequency
!
Combines Focus and Dynamic Focus signals to one signal (Focus_sig) for
both the horizontal and vertical for each color
!
L/R and T/B Pincushion