HP j6700, Service Handbook, Page: 48 / 152

48 Chapter 3
Troubleshooting
Identifying LCD-Indicated Conditions
TST 1
n
26 SYS BD CPU
n ext intrpt
CPU n is starting its external interrupt
self-test.
TST 1
n
27 SYS BD CPU
n itimer test
CPU n is starting its interval timer
self-test.
TST 1
n
28 SYS BD CPU
n multi-media
CPU n is starting its multi-media
instructions self-test.
TST 1
n
29 SYS BD CPU
n shadow reg
CPU n is starting its shadow register
self-test.
TST 1
n
2A SYS BD CPU
n diagnse reg
CPU n is starting its diagnose register
self-test.
TST 1
n
2B SYS BD CPU
n rdr test
CPU n is starting its remote diagnose
register self-test.
TST 1
n
2C SYS BD CPU
n bypass test
CPU n is starting its integer bypass
operation self-test.
TST 1
n
30 SYS BD CPU
n start est
CPU n is starting its early (pre-memory)
self-tests.
WRN 1
n
31 SYS BD CPU
n skip est
CPU n is bypassing its early self-tests to
save time.
FLT 1
n
32 SYS BD CPU
n bad tst mod
CPU n detected an unsupported system
mode.
INI 1
n
3C SYS BD CPU
n initialize
CPU n is initializing after self-tests.
TST 1
n
3E SYS BD CPU
n exit est
CPU n finished its early self-tests.
TST 1
n
A0 SYS BD CPU
n fpu tests
CPU n is starting its floating-point unit
self-tests.
TST 1
n
A1 SYS BD CPU
n fpu reg tst
CPU n is starting its floating-point
register self-test.
TST 1
n
A2 SYS BD CPU
n fpu inst
CPU n is starting its floating-point
instruction self-test.
TST 1
n
A3 SYS BD CPU
n fpu traps
CPU n is starting its floating-point trap
self-test.
TST 1
n
A4 SYS BD CPU
n fpu misc
CPU n is starting its floating-point
miscellaneous operations self-test.
TST 1
n
A5 SYS BD CPU
n fpu bypass
CPU n is starting its floating-point
bypassing self-test.
TST 1
n
B1 SYS BD CPU
n TLB RAM tst
CPU n is starting its TLB register
self-test.
Table 3-1. Chassis Codes for J6700 Workstations
Ostat Code FRU Message
Description