Table 52 Processor Events That May Light Diagnostic Panel LEDs
(continued)
Notes
Source
Cause
Sample IPMI Events
Diagnostic
LED(s)
rendezvous
failure
SFW
The logical
monarch CPU
Type E0h, 67d:26d BOOT_MONARCH_TIMEOUT
Processors
(thread) has
timed out
SFW
A logical
slave CPU
Type E0h, 57d:26d BOOT_INCOMPATIBLE_SLAVE
Processors
(thread) is
incompatible
with logical
monarch CPU
SFW
CPU PAL
incompatible
Type E0h, 56d:26d BOOT_INCOMPATIBLE_ PAL
Processors
with
processor
SFW
A processor
failed
Type E0h, 34d:26d BOOT_CPU_FAILED
Processors
SFW
A logical CPU
(thread) failed
early self test
Type E0h, 33d:26d BOOT_CPU_EARLY_TEST_FAIL
Processors
Possible seating
or failed
processor
BMC
No physical
CPU cores
present
Type 02h, 25h:71h:80h MISSING_FRU_DEVICE
Processors
Troubleshooting Memory
The memory controller logic in the zx2 chip supports three versions of memory expanders: a 48
slot version that provides six physical ranks that hold 4/8/12/16/20/24 memory DIMMs in both
memory cells 0 and 1.
All three versions of memory expanders must have their memory DIMMs installed in groups of four,
known as a quad. DIMM quads of different sizes can be installed in any physical rank on all
versions of memory expanders, but they must be grouped by their size.
Both the 24 and 48 slot memory expanders support physical memory ranks with four DIMMs while
the common 8 slot memory expander’s memory cells 0 and 1 each support physical ranks with
two DIMMs. In the 8 slot memory expander, however, the logical quad of four DIMMs includes
ranks from both sides 0 and 1 running in lock step with each other.
Memory DIMM Load Order
For a minimally loaded server, four equal-size memory DIMMs must be installed in slots 0A, 0B,
0C, and 0D on the same side of the 24/48 slot memory expander; and in the 0A and 0B slots
on both 0 and 1 sides of the 8 slot memory expander.
The first quad of DIMMs are always loaded into rank 0’s slots for side 0 then in the rank 0’s slots
for side 1. The next quad of DIMMs are loaded into rank 1’s slots for side 0, then for side 1, and
so on, until all ranks slots for both sides are full.
Best memory subsystem performance result when both memory sides 0 and 1 have the same number
of DIMM quads in them.
158
Troubleshooting
