HP 8340A, Service Manual

Page: 242 / 326

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Model 8340A - Service
ground through R37.
Transistor Ql and surrounding circuitry form a capacitance
multiplier circuit used to provide a filtered +15V supply, TPl,
for the Differential Amplifier, Block E. The output voltage is
determined by the _voltage divider of R49 and R50 less the 0.6V
base-emitter voltage drop. The circuit also provides a one-pole
lowpass filter with Fe = 5.2 Hz (determined by the parallel
combination of R49, RSO, and C14). This circuit also provides a
ground transformation from the.chassis ground to the reference
ground.
Logic Inverter/Translator L
The Logic Inverter/Translator inverts the HLEY (High=Lock Enable,
YO) signal from the A59 Digital Interface assembly through the
A50 YO Loop Interconnect assembly. The circuit has two outputs:
*
LLEY (Low=Lock Enable, YO) is a TTL signal used to control the
Sample and Hold, Block
H.
(LOW
=
sample; HIGH = hold.)
*
YO LOOP DISABLE is an ECL logic signal that is used to disable
the YO loop when in the hold mode {during sweeps). It does
this by pulling HIGH the second input of IF Limiter USA,
Block
B, causing U8B's output to remain LOW. This disables
the sampler IF input to the Phase/Frequency Detector, Block
D,
and causes the output of loop integrator U5 to rail to its
+6.9V limit. This prevents the YO phase detector from
responding to the sweeping YO signal which would produce
noise. This noise, present at the input of U3, could feed
through to cause low-level disturbances of the YO TUNE
signal.
C32 is present to delay the YO Loop Disable signal to assure that
the sample and hold circuit is activated before the loop is
disabled. The circuit is designed so that the discharge rate of
C32 (through Q2) is several times faster than the charge rate
(through R46). The result is that, although the disable signal is
delayed, the loop is quickly enabled so that the YO lock time is
not affected.
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Scans by HB9HCA and HB9FSX