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HP 8340A, Service Manual

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HP 8340A Service Manual Download Page 192

Model  8340A  - Service 

Pretune  current 

+ 

Discriminator  current 

+ 

Sweep  current 

= 

1.5  mA 

The  sensitivity  of  this  node  is  5mA/MHz;  that  is,  if  0.005mA  of 
sweep  current  is  added  to  the  node,  the  input  to  the  PULSE 

GENERATOR  (Block 

A) 

will  decrease  by  0.001  MHz,  causing  the 

discriminator  to  reduce  its  output  current  by  0.005mA,  exactly 
cancelling  the  sweep  current. 

OUTPUT  CURRENT  SOURCE 

G 

The  emitter  of  Q2  provides  a  virtual  ground  to  sum  error  currents 

from  U3  and  feed-forward  signals  from  the  DELTA 

F 

SWEEP 

ATTENUATOR  (Block 

E) 

and  phase-lock  inputs.  The  phase-lock 

feed-forward  path  reduces  the  lock  time  by  feeding  the 

discriminator  tune  voltage  ahead  to  the  output  current  source. 

To  achieve  a  low  noise  junction,  there  is  an  optimum  input  im­
pedance  to  be  presented  by  Q2.  This  requires  a  constant  emitter 
current.  Ql  is  used  to  achieve  a  constant  Q2  emitter-current  of 
about  0.14  mA.  Q2  will  conduct  only  enough  current  to  cause  a  0.7 

V 

drop  across  R47,  at  which  point  Ql  will  turn  on  and  conduct  the 

remaining  current.  The  changing  tuning  current  of  1  to 

9 

mA 

will  then  flow  through  Ql,  leaving  Q2  with  a  constant  current, 

hence  a  constant  input  impedance. 

The  output  of  the  current  source  is  a  current  of  1  to 

9 

mA  sent 

to  the  A40  PLL2 

vco. 

8-265 

Scans by HB9HCA and HB9FSX

Summary of Contents for 8340A

Page 1: ...Scans by HB9HCA and HB9FSX ...

Page 2: ...ent Not Supplied in Service Kit 8 8 Calibration Constants 8 21 I O Devices 8 30 Omitted Direct I O Data Bit Information 8 34 L4 Inductor Values and Part Number 8 112 Approximate Bias Voltage Levels for 100 MHz Buffer Amplifier 8 112 Attenuation and Resistor Values for 100 MHz OUT and 400 MHz OUT 8 113 Table 8B 4 8B 5 8B 6 8C 1 8C 2 8C 3 8D 1 8D 2 8D 3 8E 1 Page Approximate Bias Levels for Quadrupl...

Page 3: ...is is a Safety Class I product provided with a protective earthing terminal An uninterruptible safety earth ground must be provided from the main power source to the product input wiring ter minals power cord or supplied power cord set Whenever it is likely that the protection has been impaired the product must be made inoperative and be secured against any unintended operation BEFORE APPLYING POW...

Page 4: ...ystal Osc t3 MIN Phase Detector t4 MIN VGO Voltage Controlled Osc t5 MIN Oulput 15 Reference MINMotherboard 5 Rectifier 4 PLL1 VGO Voltage Controlled Osc 36 PLL1 Divider 37 PLL1 If 38 PLL3 Upconverter 39 PLL2 VGO Voltage Controlled Osc 40 PLL2 Phase Detector 4t PLL2 Divider 42 PLL2 Discriminator 43 VIG Oscillator YO 18 Directional Coupler 18 7 GHz Low Pass filter 18 _____ A47 Sense Resistor Assemb...

Page 5: ... these assemblies are located The tab for each of the eight functional groups provides an outline of the functional group s contents Typically this includes an introduction overall theory of operation simplified block diagram and a troubleshooting block diagram This is followed by a description of each assembly in the functional group Each assembly description contains an overall theory of operati...

Page 6: ...of Section VIII contains descriptions of the troubleshooting aids that are built into the instrument These aids are the instrument Self Test Digital Signature A nalysis DSA Direct I O Addressing and front panel Diagnostics Overall Instrument Troubleshooting This is the single most important part of the Service Section This troubleshooting guide will allow the repair person to begin troubleshooting...

Page 7: ...Section Power Level Control Power Supplies Fan These sections are further divided into overall troubleshooting guides one for each ofthe above functional groups Each ofthese guides contains the theory ofoperation and block diagrams for the functional group as a whole This is followed by a service guide for each asssembly that makes up that functional group These assembly level service guides conta...

Page 8: ...THEORY TROUBLESHOOTING AIDS INSTRUMENT TROUBLESHOOTING REPAIR SCHEMATIC SYMBOLOGY CONTROLLER SECTION G OVERALL THEORY TROUBLESHOOTING TO ASSEMBLY LEVEL INDIVIDUAL ASSEMBLY SERVICE SECTIONS FRONT PANEL REAR PANEL H OVERALL THEORY TROUBLESHOOTING TO ASSEMBLY LEVEL INDIVIDUAL ASSEMBLY SERVICE SECTIONS RF SECTION I OVERALL THEORY RF ASSEMBLY ACCESS PROCEDURE INDIVIDUAL ASSEMBLY SERVICE SECTIONS POWER ...

Page 9: ...components The filter capacitors on the A35 RECTIFIER assembly bleed off faster than the A19 capacitors Therefore by the time the A19 POWER ON SAFETY INDICATOR LED is dark and the A35 assembly is connected to all of its normal loads the A35 capacitors have had time to discharge Any interruption of the protective grounding conductor inside or outside the instrument or disconnecting the protective e...

Page 10: ...iver Wrench Item RMA Solder EDSYN SILVERSTAT Replacement Tip Wrist Strap 30 pin 36 pin 44 pin 48 pin 62 pin 110 pin 16 pin 20 pin Fits adjustment slot on components BNC Male to SMB Female 2 required 61 mm 2 ft 0 85 in semi rigid SMA Male to SMA Male 2 required 30 mm 12 in SMB Female to SMB Female 9 16 inch to replace front panel BNC nuts 5 16 inch slotted box open end Table 8A 2 Equipment Not Supp...

Page 11: ...ard Functional Group Table 8E 1 alphabetically lists and defines all HP 8340A signal mnemonics references the point to point distribution of each signal to and from thePC board sockets and the cable connectors on the A62 Motherboard assembly and identifies the signal source This table is located in the A62 Motherboard Functional Group 8 9 Scans by HB9HCA and HB9FSX ...

Page 12: ... sent to the RF Section for phase locking the 3 7 GHz Oscillator to the 10 MHz Reference M N LOOP The M N Loop produces an output between 177 197 MHz This M N output drives a Sampler in the YO Loop The variables M and N are integers generated by the processor and control the output frequency of the M N Loop The output from the Sampler in the YO Loop must always be between 20 30 MHz for the instrum...

Page 13: ...ion performs all of the data transfer and coordinates the control signals that operate the HP 8340A It contains a 16 bit microprocessor a total of 34K x 16 ROM and SK x 16 RAM This section also contains interface circuitry for communicating with the rest of the instrument Digital information is exchanged between the microprocessor and other sections of the instru ment on a bidirectional bus In the...

Page 14: ...ry so the YIG Tuned filter in the SYTM can track the YO properly Leveling in Bands 2 4 is the same as in Band 1 Pulse modulation in the HP 8340A is produced by the Pulse Modulator Driver and two fast response time pulse modulators The Band 0 Pulse Modulator located just before the Band 0 Mixer is used when the HP 8340A is operating below 2 3 GHz Operation above 2 3 GHz uses the Band 1 4 Pulse Modu...

Page 15: ...SUPPLY 5 2V L i 40V I l s UP P L Y j lf i l 40V I l5V SUPPLY t5V DB0 11 I SWEEP TIME SCALING RESISTORS I RESET OAC RAMP I GENERATOR f BVSWP VSWP SWEEP I J s wEEP WIDTHI v s wp _ WIDTH 1 1ATTENUATOR __ __ __ _ ________ 20 30 SWP rr I oso 15 PROCESSOR A60 7 I MEMORY I DECODING MEMORY I CLOCK 1 i TIMER SELF TEST JNDICATOR DSA INTERRUPT L_ ENCODER I SWEEP lSWEEP I CONTROL _ CONTROL LOGJC 1 1KR RAl 1P ...

Page 16: ...btain the calibration information required for optimum operation of the instrument In addition to this the HP 8340A will access the Working Data after an INSTR PRESET is initiated and only to verify that the CHECKSUM Cal Constant 99 is accurate see Figure 8A 3 Instrument Preset Calibration Constant Verification Sequence When INSTR PRESET is pressed the Working Data Cal Constants 1 through98 are su...

Page 17: ... DEFAULT DATA CAL CONST THROUGH 99 INTO WORKING AREA LIGHT FAULT DISPLAY CAL DEFAULTED INSTRUMENT CONTINUES OPERATION TROUBLESHOOT FAULT WRITE PROTECTED DATA CAL CONST 1 THROUGH 99 INTO WORKING AREA SUM CAL CONST 1 THROUGH 98 THEN COMPLEMENT NO YES INSTRUMENT PRESET NOT POWER UP DISPLAY CALIBRATION RESTORED CONTINUE NORMAL OPERATION YES CONTINUE NORMAL OPERATION Figure BA 3 Instrument Preset Calib...

Page 18: ...equency allows the HP IB address to be viewed in the ENTRY DISPLAY By rotating the RPG or by keyboard entry the HP IB address may be changed from 00 to 30 When the desired address is set press the Hz key and the HP IB address will be changed and the CHECKSUM updated note that only the Working Data is updated To prevent the HP IB address frombeing changed in thismanner bit 5 of Cal Constant 57 may ...

Page 19: ...umper A59Wl will disable the lockword function 8 CALIBRATION CONSTANT ACCESS WHEN LOCKWORD FUNCTION IS ENABLED SHIFT MHz 2 O Hz This key sequence allows access to the location sub channel where the password for access to the Cal Constants will need to be entered After pressing the above key sequence enter the password via the ENTRY keyboard and press Hz Upon entry of the correct password the Cal C...

Page 20: ...t by adding 19 HP IB address 32 disallows SHIFT LOCAL 0 allows SHIFT SAVE and 128 disallows SHIFT RECALL The other four Cal Constants work in the same manner A hard copy of the HP 8340A s Protected Data is included in a plastic envelope with each instrument It is stored in a bracket which is located underneath the top cover on the side ofthe instrument If the Working and Protected Data are ever lo...

Page 21: ... 27 AT20 SLOPE 4 60 CONFIGURATION 23 93 unused 0 28 AT30 SLOPE 3 61 SERIAL 9999 94 unused 0 29 AT40 SLOPE 5 62 ATIO SLP 20GZ 4 95 unused 0 30 AT50 SLOPE 7 63 AT20 SLP 20GZ 5 96 unused 0 31 AT60 SLOPE 60 64 AT30 SLP 20GZ 5 97 unused 0 32 AT70 SLOPE 8 65 AT40 SLP 20GZ 8 98 MODEL 0 33 AT80 SLOPE 10 66 AT50 SLP 20GZ 9 99 CHECKSUM 9557 8 20 Procedure for manually entering calibration data into the HP 8...

Page 22: ...Band 3 0 131 for single band sweeps or multi band sweeps that begin in Band 3 Compensates for YTMDelay in Band 4 0 131 for single band sweep Adjusts Band 1 in YTMslow speed 0 2040 tracking Adjusts Band 2 YTMslow speed 0 2040 tracking Adjusts Band 3 YTMslow speed 0 2040 tracking Adjusts Band 4 YTMslow speed 0 2040 tracking Slope compensation for RF power in 0 255 Band 0 Slope compensation for RF po...

Page 23: ...on for RF power at 70 200 dB attenuator setting from 0 01 to 26 5 200 GHz Offset compensation for RF power at 80 200 dB attenuator setting from 0 01 to 26 5 200 GHz Offset compensation for RF power at 90 200 dB attenuator setting from 0 01 to 26 5 200 GHz Slope compensation for RF power at 10 255 dB attenuator setting from 2 3 to 20 0 255 GHz Slope compensation for RF power at 20 255 dB attenuator...

Page 24: ... UNUSED UNUSED UNUSED UNUSED Adjusts front panel dBm display 100 accuracy from 01 to 2 3 GHz 100 Adjusts front panel dBm display 100 accuracy from 2 3 to 26 5 GHz 100 Sets the maximum sweep rate in the 1 1000 AUTO sweeptime mode Adjusts front panel dBm display 100 100 Modulation level offset for output 100 power accuracy in AM mode 100 Offsets level DAC A27U14 for internal 100 leveling operation 1...

Page 25: ... 4 Sets maximum allowable stop 11 26 000 frequency Sets minimum allowable start 10 S TOP frequency LIMIT 1 Selects instrument s operating conditions Bits 0 through 7 Selects power level 0 110 after INSTR PRESET Bit 10 PMI N etwork Analy zer retrace 0 1024 compatibility Bit 12 CI IL compatibility if option is 0 4096 installed Selects instrument s operating conditions Bits 0 through 4 selects HP IB ...

Page 26: ...installed Bit 13 Must be set to zero 0 Bit 14 Selects version of A26 Linear 0 16 384 Modulator Assembly Installed 0 selects P N 08340 60021 1 selects P N 08340 60156 Bit 15 Must be set to 0 This selects 0 how attenuator is programmed Selects instrument options Bit 0 Must be set to zero 0 Bit 1 Without or With Option 001 or 0 2 005 No attenuator option Bit 2 Without or With Option 004 or 0 4 005 Re...

Page 27: ...tting from 20 0 to 26 5 255 GHz Slope compensation for RF power at 60 255 dB attenuator setting from 20 0 to 26 5 255 GHz Slope compensation for RF power at 70 255 dB attenuator setting from 20 0 to 26 5 255 GHz Slope compensation for RF power at 80 255 dB attenuator setting from 20 0 to 26 5 255 GHz Slope compensation for RF power at 90 255 dB attenuator setting from 20 0 to 26 5 255 GHz UNUSED U...

Page 28: ...on constants only upon input of the correct password lockword UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED Instrument model number 0 1 99 Serves as check point for Cal Constant Accuracy The sum of Cal Constants 1 through 98 is calculated the sum is complemented and the result is stored as the CHECKSUM Significance Disabled Enabled 0 8340A...

Page 29: ...se lock condition exists for three phase lock loops Each LED is lit when its specific loop is phase locked The LEDS and phase lock loops are as follows 1 A37DS1 PLLl 2 A39DS1 PLL3 3 A50DS1 YO POWER SUPPLY INDICATION LEDS Several yellow LEDS indicate when the power supplies are at their required voltage Each LED is lit when its specific power supply is up The LEDS and power supplies are as follows ...

Page 30: ...ed by the processor on the data bus and then translate and transmit the data in a form required for use in other parts of the instrument These devices consist of DACs 3 to 8 decoders output registers and flip flops To test these devices using Direct 1 0 Addressing a known input must be transmited on the data bus by means of a write command and the output of the device probed by a logic probe or DV...

Page 31: ...5 Output A58U26 Output WRDAC A59U26 A58U4 Output A58Ul9 Output A58U21 Output LRSW A59U26 A59U23 Output A5U19 No Connection A59U19 No Connection UNASSIGNED UNASSIGNED TYOKP A59U26 A54U9 Output PHASE LOCK A59U26 A59U24 Output CNTRL WPDAC A59U26 A54Ull Output A54Ul3 Output M N OSC A59U26 A59Ul0 Output CONTROL A59Ul7 Output A59U12 No Connection A59U10 No Connection No Connection READ STATUS A59U12 A59...

Page 32: ... WLEVEL A27U27 A24Ul5 Output A27U13 Output A27Ul6 Output WBAND A27U27 A27U28 Output A28U14 Output RLEVEL A27U27 A27Ul1 Output A27U12 Input A27U15 Input A27U21 Output WLSWP A27U27 A27U23 Output A27U30 Output WSYTMSLP A27U27 A28U15 Output UNASSIGNED WSYTMCTL A27U27 A28U13 Output WRITE RAM A57U28 A57U2 A57U15 A57U29 Output READ STS A57U28 A57U24 Input READ RAM A57U28 A57U8 A57U16 A57U29 Output Direct...

Page 33: ...t TRIGGER SEL A57U28 A57U18 Output WRITE STROBE A57U28 A57U25 Output MAN DAC A57U28 A57U9 Output A57Ul7 Output WRITE CONTROL A57U28 A57U23 Output WATNS A27U20 A27U8 Output UNASSIGNED WBPlS A27U20 A27U9 Output WBP2S A27U20 A27U10 Output UNASSIGNED WADCC A27U20 A27U29 Output UNASSIGNED RSTAT A27U20 A24714 Input A27U22 Input Direct 1 0 Capability Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Sc...

Page 34: ...ess INSTR PRESET MANUAL Setting the instrument in MANUAL mode prevents the processor from writing data to the device being tested This ensures that the data being entered from the front panel is not changed prior to testing the device 3 Press SHIFT GHz xx Hz This key sequence sets up the I O Strobe Channel Enter the desired Channel number where the xx is located 4 Press SHIFT MHz yy Hz This key se...

Page 35: ...846 Entry Data Line 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Level 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 Level Typically 0 3V 1 Level Typically 3 0V DAC VERIFICATION The DACs which can be tested using Direct 1 0 Addressing are those which have a strobe listed in Table 8A 4 and the data bus connected to them An example of one of these DACs is A54Ul5 Several other DACs have their data sent from an outp...

Page 36: ...ws 1 Verify the operation of the device s I O Strobe as described in the strobe verification procedure 2 Press INSTR PRESET MANUAL 3 Press SHIFT GHz xx Hz This key sequence sets up the I O Strobe Channel Enter the desired Channel number where the xx is located 4 Press SHIFT MHz yy Hz This key sequence sets up the I O Strobe Subchannel Enter the desired Subchannel number where the yy is located 5 P...

Page 37: ...ssuming that A59U18 is the device to be tested refer to A59 Digital Interface Schematic the inputs to the latch would be tied to 5V and ground alternately The connections would be made as follows Input Pin 8 13 2 11 6 15 17 4 Voltage 5 0 5 0 5 0 5 0 Binary Value 1 0 1 0 1 0 1 0 When an 1 0 Read is initiated the data on the input of A59Ul8 is transferred to the processor via the data bus bits 8 thr...

Page 38: ... above test the 5V and ground connections to the inputs of A59U18 would be reversed The connections would be as follows Input Pin 8 13 2 11 6 15 17 4 Voltage 0 5 0 5 0 5 0 5 Binary Value 0 1 0 1 0 1 0 1 The following table would be constructed Bit Number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Binary Value 0 1 0 1 0 1 0 1 x x x x x x x x The binary number above is converted to an octal number The po...

Page 39: ...isplay self test diagnostic function Press SHIFT FREE RUN which will cause every segment of every LED in the displays to light followed by a marching pattern of every character in the display Press SHIFT M5 to cancel this diagnostic routine and to restore the displays to their previous condition SHIFT EXT HP IB SHT3 activates the oscillator diagnostic function When the red UNLK annunciator appears...

Page 40: ... run at power on and after on INSTR PRESET to be displayed in the front panel ENTRY DISPLAY For more information refer to the A60 Processor assembly troubleshooting in the Controller Section SHIFT M5 HP IB SHM5 turns off any of the above diagnostic routines and restores the displays to their previous condition SHIFT XTAL HP IB SHA2 activates a band crossing diagnostic function Press SHIFT XTAL to ...

Page 41: ...r than the desired output power then reduce the power to the desired level by changing the MOD value The POWER dBm display shows actual power when the HP 8340A is in CW or wide pulse pulses modulation modes this actual power changes very little as the pulse width is narrowed even though the POWER dBm reading drops Therefore at this point reduce the pulse width to the desired value and ignore the P...

Page 42: ...ing information presented here is intended to guide the troubleshooter to the appropriate information in the manual Figure 8A 9 Overall Instrument Troubleshooting Diagram and Figure 8A 10 Front and rear panel Items indicate the proper sequence to follow to isolate specific symptoms Each of these is described in detail in the following pages Several categories make reference to Front and rear panel...

Page 43: ...HOWN IN FIGURE BA 10 ON THE FACING PAGE INSTAUMENT PRESET CONDITION CDCD ALL DEAD ALL LEDS ON OR FAN ON WHEN INSTRUMENT IS IN STANDBY CHECK LEDS I OR 11 UNLOCK ANNUNCIATOR FAULT ANNUNCIATOR UNLEVELED ANNUNCIATOR OVERMOD ANNUNCIATOR I FREQUENCY K _ E _ Y _ B OA _ R _ D _ S _ DISPLAYS POWER INCLUDES PULSE AM EXT LEVEL SPECTRAL PURITY SPURIOUS RESPONSE I 0 CONNECTORS REMOTE OPERATION 16 SWEEP Figure ...

Page 44: ...4 Model 8340A Service FRONT PANEL REAR PANEL Figure 8A 10 Front and Rear Panel Items 1s 8 43 Scans by HB9HCA and HB9FSX ...

Page 45: ...nformation 2 ALL DEAD ALL LED s OFF If after INSTR PRESET all of the LED s and annunciators are off suspect a power supply problem Refer to the Power Supply Theory of Operation and Troubleshooting If some of the LED s that should be on are on and somethat should be on are off suspect a problem in the HP 8340A front panel Refer to the front panel Theory of Operation and Troubleshooting ALL LED s ON...

Page 46: ... the oven temperature reaches the desired point the frequency is within 100 Hz of 10 MHz HOVC goes low O 15V HOVC is sent to the A59 Digital Interface board where the microprocessor reads it and determines when to turn the light on or off The OVEN LED is located on the A 2 Display Driver board Block E These LED s are driven by the A3 Display Processor Annunciator Latch Driver The LED is turned on ...

Page 47: ... refers to the kick pulses used to reset the YO and SYTM AT end of sweep the YO and SYTM are tuned below their normal start frequencies by a kick pulse generated on the A54 YO Pretune DAC Delay Compensation board or the A28 SYTM Driver board These kick pulses last a finite period of time If a pulses stays on longer than it should the processor will detect it and indicate a KICK FAULT Refer to the ...

Page 48: ...the A26 Linear Modulator board the Al 2 Band 0 Splitter Detector or the associated microcircuits Refer to the RF Section Theory of Operation and Troubleshooting g If the power is unleveled in Bands 1 4 2 3 GHz to 26 5 GHz only suspect a problem in the switching circuits on the A25 ALC Detector board or A26 Linear Modulator board or the All Band 1 4 Detector and the associated microcircuits Refer t...

Page 49: ...latness by varying the offset and slope correction factors If the frequency response has large perturbations the problem is most likely in the associated RF path Refer to the RF Section block diagram By observing if the problem is in Band 0 only Band 1 4 only or both Band 0 and Band 1 4 part of the RF circuitry may be eliminated If the RF power level is low at 10 MHz and increases with frequency s...

Page 50: ...y ofvalues generated at the last calibration should be located inside the instrument Remove the top cover see pocket along lef t side rail Check the calibration constants in HP 8340A memory against the hardcopy values Restore the correct values ifnecessary Refer to Section VIII Calibration Constants for more informa tion Ifthe attenuator is operating properly and the calibration constants are corr...

Page 51: ...Reference Loop 2 If the HP 8340A failed the phase noise test at offset frequencies from 300 Hz to 50 kHz the problem is most likely the M N Loop Replace the Reference Loop 400 MHz input to the M N Loop as described in step I above If the HP 8340A continues to fail the phase noise test the problem is in the M N or YO Loop An external source couldbe used to replace the M N input to the YO Loop but t...

Page 52: ...alanced and the magnetic radiation may increase Magnetic radiation coupled into the M N Loop can sometimes be reduced by replacing A2 9Ul The amplifier limiter on the Reference Phase Detector board SQUEGGING Band 1 4 only Observe the spurious response on a spectrum analyzer while changing the HP 8340A output power level If the frequency of the spur changes with power level suspect squegging Refer ...

Page 53: ...stic ofcrossing spurs is that the offset ofthe spur from the carrier changes as the carrier is moved therefore there is some frequency that the offset must be zero Assuming the sources ofthe spurs can be tuned to this frequency This frequency is called the CROSSING FREQUENCY ofthe spur The ratio ofthe change in spur offset to the change in carrier frequency is called the ORDER Names can be assigne...

Page 54: ...anges Determine the order of the spur i e Ratio of YO frequency change to spur frequency change If the spur is a crossing spur at some point the spur will be on top of the YO frequency and at some point 50 kHz away from the YO frequency the spur amplitude will decrease If the spur is a crossing spur refer to the appropriate spur family type above It may help determine which internal frequency sour...

Page 55: ...A60 Processor Troubleshooting in the Controller functional group Ifa problem is not observed while running this program and the HP 8340A does not respond properly to other remote commands refer to the computer documentation to read the computer HP IB I O card status By outputting the I O card status the source ofthe problem may be determined Scans by HB9HCA and HB9FSX ...

Page 56: ...oil based thermal compound The use of silicone based thermal compount may cause serious reliability problems Silicone based oil migrates to pass element sockets switch contacts or printed circuit board edge connectors The compound then tends to raise contact resistance or electrically isolate the contacts Silicone based thermal compounds disperse into the air and deposit themselves anywhere in the...

Page 57: ... in the cleaning solution described below Tap water contains chlorine Chloride contamination from tap water salt from skin contact or any other source may cause serious reliability problems dendrite growth trace damage see the preceding warning Always wear a ground strap when handling any internal HP 8340A component or assembly Always hold printed circuit boards by the edges PRINTED CIRCUIT BOARD ...

Page 58: ...e module from HP Refer to the replaceable parts s e c t i o n f o r p a r t numbers I Put restored exchange module in spares stock Return defective mod ule to HP A B c Restored exchange modules are shipped individually in boxes like this In addition to the circuit module the box contains Exchange assembly failure report Return address label Open box carefully it will be used to return defective mo...

Page 59: ... pass either of the above tests do not connect the instrument to the ac mains Troubleshoot the source of the problem at once Check the line fuse to verify that a correctly rated fuse is installed Make sure the line module s line voltage selector pc board is set to the correct voltage AIR FILTER REPLACEMENT The following procedure must be performed periodically to retain the safety features which h...

Page 60: ...ine with arrows nection Y 0 indicates path and dir ection of main signal l v Resistor Indicates path and dir Resistor Temperature 0 ection of main feed Sensitive a back 0 Earth ground symbol Variable Resistor 0 Assembly ground May General purpose diode 0 be accompanied by a number or letter to spec ify a particular ground Step recovery diode 8 Chassis ground Schottky diode Represents n number v Br...

Page 61: ... PRI Edge sensitive 1 0 Input Output SREG n AN SW Analog Switch LINE LABEL ABBREVIATIONS Control MSB Most Significant Bit T Data or Delay Input Flip Flop NC No Connection WR Direction Q 0utput 1 Enable 3 State Enable Input Q Not Q Complement of Q 1 Gating Input Least Significant Bit R Reset or Clear Input RD Read s Set Input 3 State 0utput Figure 8A 12 Schematic Diagram Notes 2 of2 Inverter Negati...

Page 62: ...4 MIN vco Voltage Controlied Osc 15 M N Output 15 Reference MIN Motherboard 5 Rectifier 4 PLL1 VCO Voltage Controlled Osc 36 PLL1 Divider 37 PLL1 IF 38 PLL3 Upconverter 39 PLL2 VCO Voltage Controlled Osc 40 PU2 Phase Detector 41 PLL2 Divider 42 PLL2 Discriminator 43 VIG Oscillator YO 18 Directional Coupler 18 7 GHz Low Pass Filter 18 A47 Sense Resistor Assembly YO circuit 47 SYTM circuit 47 A48 YO...

Page 63: ...ROUBLESHOOTING TO ASSEMBLY LEVEL M N and Reference Loops Troubleshooting Block Diagram REPAIR PROCEDURES INDIVIDUAL ASSEMBLY SERVICE SECTIONS A29 Reference Phase Detector A30 1 00 MHz VCXO A31 M N Phase Detector A32 M N VCO A33 M N Output A34 Motherboard Casting Assembly A51 Reference Oscillator M N LOOP REFERENCE LOOP MAJOR ASSEMBLIES LOCATION DIAGRAM Scans by HB9HCA and HB9FSX ...

Page 64: ...s for each printed circuit board assembly The Reference Loop produces all of the translation and reference signals that are used in the other phase locked loops in the 8340A The Reference Loop consists of the following sections A29 Reference Phase Detector Assembly A30 100 MHz vcxo Assembly The M N Loop generates the 177 197 MHz signal that drives the A48 Sampler in the YO Loop The M N Loop consis...

Page 65: ...CXO is a crystal stabilized voltage controlled oscillator with exceptional noise performance The tuning range of the VCXO is approximately l kHz of its nominal frequency The output of the 100 MHz VCXO is buffered and then split several ways One output is used to drive the sampler in the A8Al 3 7 GHz Oscillator Assembly Another ou tput is first quadrupled in frequency to 400 MHz amplified and hen s...

Page 66: ...r the N divider in the phase detector whose differential output is used to tune the vco This tune voltage keeps the M N Loop phase locked to the output of the N divider The N divider is programmed to divide the 20 MHz reference signal by an integer from 13 to 36 The M N vco is a foreshortened cavity resonator that is varactor tuned from 355 to 395 MHz The M N vco assembly consists of the cavity os...

Page 67: ... and for every increment in N number the output will increase by 200 MHz This relatioriship is given in the following equation where f 20 30 is the output of the 20 to 30 Loop f YO 200 N lO M f MHz 20 30 Scans by HB9HCA and HB9FSX ...

Page 68: ... L ______________ L _______________ L I CONVERTER I I I I I I 20MHz 11 32 I I I I 1 I A32 I 1M N VC01 I I I L _ J 177 l97MHz 3dBm I A48 SAMPLER LO OdBm I I I I A49 YO LOOP PHASE DET L ________ _J L ________________________ J IOMHz I _ __ 4 20 30 A42 OdBm PLLI DIVIDER IOMHz I 20 30 A37 OdBm PLL2 DIVIDER I IOMHz I IOMHz OUT REAR PANEL JS I OdBm I I L j REFERENCE LOOP MIN LOOP 20 30 MHz IN 1 OdBm Fro...

Page 69: ... the rear panel the problem is probably on the Reference Phase Detector board A29 or the 100 MHz VCXO A30 Measure the voltage on TPl TUNE on the cover of A30 board This voltage should be approximately 8 volts If it is at 8 volts then the Reference Loop is most likely locked up and the problem is on the unlock detector portion of the A29 Reference Phase Detector or A59 Digital Interface board If th...

Page 70: ...g device ie counter or spectrum analyzer both locked to the same 10 MHz standard If the measured frequency and the frequency in the first window are the same and the M N Loop is still unlocked then the problem is most likely on the UNLOCK indicator portion of the A31 M N Phase Detector board or the UNLOCK Detector portion of the A59 Digital Interface board tf there is no signal out of A33J2 then t...

Page 71: ... GHz to 6 9 GHz N Number from 13 to 36 At each step record the measured M N output frequency and the frequency displayed in the first window Check the list of frequencies If some of the measurements match and some do not then the problem is most likely on the N Divider portion of the A31 M N Phase Detector board If the measured frequencies in the above two tests do not change as the M or N number ...

Page 72: ...E lra v EN tl o l _ 3 i l l s v TO A35PHB 36 B a 4 J GND CASE GROUND L _TI 4 5 I 20 REF OSC L ClACUIT I 3 7 I 3 µ_ HOVC TO A69P1 10 I I TO A62Pl 20 __ P O W46 J31 J 3 1 Qr 4 17 HXREF TO A59Pl 98 L P 0 Figure 8B 2 Reference Loop M N Loop Block Diagram ALL SERIALS P O 8 95 8 96 Scans by HB9HCA and HB9FSX ...

Page 73: ...LO OdBm 1 OdBm DIGITAL MOTHER REF M N y __ r_ F_____ _ INTERFACE BOARD MOTHERBOARD A32 M N VOLTAGE CONTROLLED LO NOTES I REFER TO FIGURE8A 12FOR A DESCRIPTION OF THE SYMBOLOGY USED ON THIS BLOCK DIAGRAM 2 NOT ALL POWER SUPPLY INTERCONNECTIONS ARE SHOWN ON THIS BLOCK DIAGRAM A31Wl Pll XA59 XA34PI I Pll xA311 PIO Pl Ml 1 33 5 13 I PiOI I P O P 01 lp o Pi01 OSCILLATOR ASSEMBLY VCQ I 1 M7 y 2 A OUTPUT...

Page 74: ...Model 8340A service REPAIR PROCEDURES Refer to the REPAIR PROCEDURES description in the beginning of Section VIII 8 97 8 98 Scans by HB9HCA and HB9FSX ...

Page 75: ...UlA and UlB form a limiting differential follower UlC provides a low impedance U2D is biased with feedback resistor RlO to further limit the 10 MHz signal to a well shaped square wave and set the proper logic levels for digital buffer U2C U2A and U2B generate narrow pulses the width b ing the gate delay of U2A plus the delay from Rll and C5 When the output of U2C goes low the output of U2B goes hi...

Page 76: ...ad Amplifier G and Fourty Five Degree Phase Lag Amplifier H The 4S degree phase shift buffers are used to provide two 10 MHz signals which are 90 degrees apart in phase The purpose of these signals is explained in Lock Indicator Sampler I description the 4S degree phase shift in G is accomplished with C3S and RS3 while in H it is done by RS9 and C38 Lock Indicator Sampler I The lock indicator samp...

Page 77: ...ice W1 MP4 MPS 1DOMHZ BOTTOM SIDE MP3 MP1 IN MP2 MP6 JS J2 1 OMHZ 20MHZ OUT OUT P1 J4 10MHZ OUT MPS A 2233 4S JS 10MHZ OUT Figure 8B 3 A29 Reference Phase Detector Component Location Diagram MP 8 101 8 102 Scans by HB9HCA and HB9FSX ...

Page 78: ...12 13 K 10 GND ov INSTRUMENT GROUND K 11 GND ov INSTRUMENT GROUND K 12 TUNE GROUND ov E XA30P1 12 13 TUNE VOLTAGE E XA30P1 14 14 GND ov INSTRUMENT GROUND K 15 GND ov INSTRUMENT GROUND K A single letter in the source or destination column refers to a function block on this assembly schematic An asterick denotes multiple sources or destinations refer to the A34 Reference Loop M N Motherboard Schemat...

Page 79: ...LIES u 9 l_ Cfj l_ CT _l_ CS 2 6 7 01 01 3 3 RI U 6 I c _o_u_ f cI C4 REF l_ C2 1 20VF 7 O O 7 OI 7 1 Pl 9 HO 10 I C60 C41 C44 1_ 9 01 7 01 01 v 16 Pl 1UN 82 C9 1 CIO J c11 I 01 I 01 I 2 2 Pl 2 UH V V 5 2VF IOVF 40VF BUFFER AMPLIFIER rn 9250 Rl7 l_ Cl7 OJ CRI IO R20 Cl9 L _ _o_ o_ _ 147 01 IOVF 45 PHASE LEAD AMPLIFIER V RJ9 71500 450 PHASE LAG AMPLIFIER R69 c e Ill 1 1 R H5 7500 Q2 83 61 I I L____...

Page 80: ...varactor diode CRl This completes the feedback loop and causes Q5 to oscillate The frequency controlling elements of the feedback network are Yl CRl C4 and ca Yl a 100 MHz quartz crystal is the principle frequency determining element CRl a varactor diode provides the electrical tuning for the oscillator Changing the reverse bias voltage on the varactor varies it s capacitance this varies the phase...

Page 81: ...bility The outp t at the collector of Q6 through the tuned circuit of LB C27 and C2B is applied to the power splitter T2 which splits the signal into two paths In each path the signal goes through a 3 dB pad and a tuned LC circuit and becomes the 100 MHz OUT signal sent to the A29 Reference Phase Detector and the A39 PLL3 Upconverter In the second path from power splitter T3 the signal goes to Q7 ...

Page 82: ...ower Supplies E QlO R9 and C43 function as a capacitance multiplier circuit to filter the 20 v supply The filtering takes place in the base current which controls the collector current This provides improved noise filtering for a given capacitor value The voltage at TP2 should be approximately 18 2 v C48 R62 C49 and C50 filter the 10 V supply with R62 and the parallel combination of C49 and C50 fo...

Page 83: ...z To test the sensitivity to TUNE change the voltage to 25 0 V this should cause the frequency to increase 1 0 kHz Apply 0 0 V to TUNE this should cause the frequency to decrease 1 0 kHz If TUNE is not working correctly then troubleshoot Q5 and surrounding circuitry If TUNE is working correctly and the frequency at 8 0 V is correct then troubleshoot the A29 Reference Phase Detector If the frequenc...

Page 84: ... the de source from TUNE and reconnect the cable at A30Jl to close the Reference Loop If TUNE changes less than 1 0 V from 8 0 V then readjust A30C4 until TUNE closed loop 8 0 V if TUNE changes more than 1 0 V then trouble shoot the A29 Reference Phase Detector 100 MHz Buffer Amplifiers B The signal level of the 100 MHz OUT signals at A30Jl J2 and J3 should be O dBm l dB If no signal is present at...

Page 85: ...C and 400 MHz Amplifier D The 400 MHz OUT signal level should be between 9 and 11 dBm If the signal level is outside these limits then check also the harmonic levels see below If they are out of spec then make the adjustment of C2 and C3 and then recheck the signal level If the harmonic levels are correct and the signal level is still low or if the 400 MHz signal is missing and if the 100 MHz OUT ...

Page 86: ...00 and 800 MHz harmonics of 100 MHz at A30Wl relative to the 400 MHz signal level should be at least 25 dB down The 100 300 500 600 700 and 900 MHz harmonics should be at least 40 dB down If the harmonic levels are too high then adjust A30Cl and A30C2 for the maximum 400 MHz signal level with the lowest possible harmonic levels Then recheck the 400 MHz OUT signal level Scans by HB9HCA and HB9FSX ...

Page 87: ...rvice J1 J2 C3 1OOMHZ 1OOMHZ MP14 400MHZ OUT OUT P1 15 ao J3 100MHZ OUT MP1 C4 TP1 1OOMHZ MP15 MP6 TUNE C56 Figure 8B 5 A30 100 MHz VCXO Component Location Diagram MP13 MP3 MP10 MPS MP2 MP7 MP16 CSHIELO ON BAC KSIOE MP12 22 PLACES MPS 8 115 8 116 Scans by HB9HCA and HB9FSX ...

Page 88: ...STRUMENT GROUND E 11 GND ov INSTRUMENT GROUND E 12 TUNE GROUND ov XA29P1 12 A 13 14 TUNE VOLTAGE XA29P1 13 A 15 GND ov INSTRUMENT GROUND E A single letter in the source or destination column refers to a function block on this assembly schematic An asterick denotes multiple sources or destinations refer to the A34 Reference Loop M N Motherboard Schematic Diagram for a complete representation of sig...

Page 89: ...Bm 3dB PAD NOTE i I c 1 3 TGHz R31 C28 LI J2 IOOMHZ OUT 19 6 2 2pf 1 0 _ _ _ I W35 IOOMHz o _ _ 4 OdllM T2 R30 R32 NOTE 4 I TO A39 110 28T 28T PLL 3 I 9 I I UPCONVERfER J2 R34 C29 LIT JI IOOMHZ OUT 19 6 2 2pf 1 0 _ _ I A29Wl lOOMHz W t i Odl M R33 R35 NOTE 4 I TO A 29 287 287 REFERENCE CI I 9 15PF C44 6 8pf L 15 O I NOTE 3 400 Ll2 R68 46 4 0 MHZ 0 wv v NOTE 4 R49 R5l 3160 511 R50 6810 IOVF C45 IOO...

Page 90: ... Detector Schematic Diagram A31 M N PHASE DETECTOR CIRCUIT DESCRIPTION TTL ECL Level Translators A The numbers to program the frequency dividers come from the A59 Digital Interface in binary at TTL levels U3 Ul3 and Ul7 shift these to ECL levels which are approximately 1 volt logic high and 2 volts logic low Nl and Ml designate the least significant bits N Divider B and M Divider C The Phase Detec...

Page 91: ...ach N 4 or N 4 1 clock pulses If dividing the N number by 4 leaves no remainder the number of clock pulses between output pulses is determined solely by N 4 If there is a remainder the number of clock pulses between outputs is determined by N 4 and N 4 1 where N 4 1 replaces N 4 once for each unit in the remainder For example if N 16 then N 4 16 4 4 with a remainder R O An output pulse occurs for ...

Page 92: ...e count down sequences are N 4 For N 19 N2 Nl 1 the first output is low with the remaining three high This means that the first pulse occurs after N 4 clock pulses and the other three occur after N 4 1 pulses During the final three count down sequences the high at the Increment Decoder Output inhibits U9B allowing the counter to count down to 0001 rather than 0010 before the End of Count Decoder i...

Page 93: ... are approximately 0 9 volts and 1 7 volts Phase Frequency Detector F The outputs of the M and N dividers are compared in Ul When they are in phase the outputs of Ul are narrow coincident pulses For unlock conditions the outputs pulses are of varying widths Preamplifier G Ql and Q2 are a low noise differential pair preamplifier Their outputs are combined in the integrating amplif er of A33 Phase L...

Page 94: ... I 1 I I I I I I I I I I I I I I I I I I I I I II i i o o4 µ s I II I IJ I 0 2 µ s i FREQUENCY AND TIME RELATIONSHIPS FOR N 16 AND M 20 Figure 8B 7 Divider Clock Pulses Versus Output Pulses Frequency and Time Relationship FLIP FLOP NO OUTPUTS I I I I I I I I I I I I I I I I I I I I I INPUT 0 2 4 6 8 10 12 14 16 18 20 PULSE 16 BOTH l n n n I 19 BOTH l n n n I OUTPUT COUNT PULSES 12 CONTROL OUTPUT l...

Page 95: ...ounter 0100 Inactive Reset Reset 1 5 10 15 Minus 4 0011 Inactive Reset Reset 19 2 6 11 16 Minus 4 0010 t 1 Inac ive Reset Reset 3 7 12 17 Minus 4 0001 Active 2 Reset 3 Reset 3 8 13 18 Minus 4 0000 Inactive Set Set 0 3 6 9 Load Counter 0011 Inactive Reset Reset 12 1 4 7 10 Minus 4 0010 Active Reset Reset 2 5 8 11 Minus 4 0001 Inactive Set Set 4 1 Active for step 3 only 2 Inactive for step 4 only 3 ...

Page 96: ... 1 L O L H L H 1 H 1 L H H 4 L L H H The Sequence of four states is controlled by a modified ring counter made up of the two flip flops contained in UlO The count sequence of UlO may be checked by verifying that the active high outputs of the flip flops follow the sequence LL HH LH and HL UlOA pin 2 and UlOB pin 15 respectively 8 127 8 128 Scans by HB9HCA and HB9FSX ...

Page 97: ...2B J1 W1 MP57 20 W2 MP60 MP55 HP63 MP1 1 MP27 MP35 MP56 MP36 100 MHZ IN MP61 MP53 MHZ IN MP5B MP5 1 355 395MHZ IN 1 18 P1 15 90 U7 UB us TP3 TP I I U1B U1S U20 5 U10 c U11 51 U12 dEP TP6 1 51 51 U23 Figure 8B 9 A31 MIN Phase Detector Component Location Diagram MP59 MP62 MP1 MP2 8 129 8 130 Scans by HB9HCA and HB9FSX ...

Page 98: ...34P1 1a A 10 N3 m XA34P1 13 A 25 N4 m XA34R1 12 A 11 GND av INSTRUMENT GROUND I 26 HULM TIL HIGH TRUE H XA34P1 8 12 GND av INSTRUMENT GROUND I 27 GND av INSTRUMENT GROUND I 13 M1 TIL HIGH TRUE XA34P1 5 A 28 M2 TIL jHIGH TRUE XA34P1 6 A 14 M3 TIL HIGH TRUE XA34P1 3 A 29 M4 TIL HIGH TRUE XA34P1 4 A 15 M5 TIL HIGH TRUE XA34P1 1 A 3a LMNE TIL jLOW TRUE XA34P1 2 NOT USED A single letter in the source o...

Page 99: ...24 GAUGE FINE WIRES THEIR OUTER CONDUCTORS ARE ELECTRICALLY CONN CTED TO PC BOARO GROUND THROUGH ldF CllANICAL SCREW CONNECTIONS IN THE ASSEMBLY COVF PLATE c e r t c r t NC I I G2 UP 2 2 G3 DOWN G4 HOLD 13 6 2 1C5 II UISf IDOO Pl 2 17 IN rl 2BUNl r 12 J _J I Pl 13 1Nl 1 11 J _J I CD PONER SUPPLIES 20VF _ic1e i 1 Pl 3 IB INJ 1 li _ cl t 2 o t c t r r livr 022 2 2 022 00 oo Pl 1 l CINl 240 1 lr IKJ ...

Page 100: ...ew that capacitively loads the cavity center post This is used to adjust the frequency to within the electrical tuning range The frequency is adjusted electrically by using reverse biased varactor diodes CRl and CR2 The reverse bias to the diodes is the TUNE voltage from A33 M N Output Board The actual electrical tuning network components are physically located inside the resonator housing Chip ca...

Page 101: ...er Amplifier B The Buffer Amplifier provides both isolation and gain for the vco output signal Ll provides an impedance match to the cavity output for the base of Ql the amplifier transistor R3 RS R7 RlO and Rll provide the de bias for Ql R3 provides negative feedback for fhe amplifier and R2 and L2 provide the output impedance The Buffer Amplifier provides at least 0 dBm output over the 355 to 39...

Page 102: ...Model 8340A Service MP1 wa CFAR SIDE MP2 MP3 Figure 8B ll A32 MIN VCO Component Location Diagram 8 137 8 138 Scans by HB9HCA and HB9FSX ...

Page 103: ...cy response of the integrator See also the M N Loop Frequency Response section in the A31 M N Phase Detector circuit description Cl2 and Cl5 are feed forward compensation capacitors for Ul The network consisting of VRl VR2 CR3 and CR4 function to speed up the charging time response of the output load of Ul whenever the output voltage is changing very rapidly It does this by bypassing R34 whenever ...

Page 104: ... for the ECL divider U2 so that it can be driven by the 0 dBm signal Divide By 2 D U2 is an EECL HP ECL divider used to generate the M N output signal which is at one half the frequency of the M N vco LMNE Low M N Enable is an M N Loop control line that could be used to turn on and off the divider through the operation of the TTL ECL Level Shifter In the 8340A the LMNE line is hard wired to ground...

Page 105: ...2lf MP25 CTYPICAL 2 PLACES ASll M N OUTPUT 16 Model 8340A Service MP26 P1 MP2ll 15 so J2 M N OUT W1 Figure 8B 12 A33 MIN Output Assembly Component Location Diagram MP20 JS MPB MP17 C2ll S55 ll95 MH Z o oeM 8 141 8 142 Scans by HB9HCA and HB9FSX ...

Page 106: ...MENT GROUND F 1a GND av INSTRUMENT GROUND F 11 GND av XA34P2 6 7 F 12 4aV 4aV INSTRUMENT GROUND F 13 GND av F 14 LMNE m LOW TRUE INSTRUMENT GROUND D 15 GND ov F A single letter in the source or destination column refers to a function block on this assembly schematic An asterick denotes multiple sources or destinations refer to the A34 Reference Loop M N Motherboard Schematic Diagram for a complete...

Page 107: ...INTRODUCTION FOR DETAILED SCHEMATIC DIAGRAM SYMflOLOGY NOTES 2 RESISTANCE VALUES ARE IN OHMS CAPACITANCE IN MICROFARADS AND INDUCTANCE IN MICROHFNRIES UNLESS OTHERWISE NOTED 3 A32AIC4 IS AN AIR DIELECTRIC CAPACITOR FORMED BY THE RESONATOR HOUSING ANO THE RESONATOR CENTER CONDUCTOR 4 PWR ADJUSTMENT THIS IS AN ADJUSTABL E PROBE MOUNTED ON THE A32AI M N VCO PC BOARD AND EXTENDING INTO THE RESONATOR H...

Page 108: ...OARD Top View MP2 WASHER MP3 NUT EACH 2 PLACES 14 PLACES Cl3 Cl4 Cl4 Cl3 CB C7 r 1 I XA34P2 1 il CG C9 XA33 M N OUT XA30 100 MHz VCXO A34 08340 60039 A 2231 45 L _ J 2 th j 1 11A Jl j MP4 WASHER MP5 NUT EACH 12 PLACES Cl 12 MPG MP7 MPS CD 4 PLACES MP9 Figure BB 14 A34 Reference Loop MIN Loop Motherboard Component Location Diagram 8 147 8 148 Scans by HB9HCA and HB9FSX ...

Page 109: ...eference MIN Motherboard P2 Pin IIO A34 Pin Mnemonic Levels Source Destination 1 2 2aV 2aV XA52P1 16 4a 3 2aV 2aV XA52P1 16 4a 4 5 2V 5 2V XA52P1 17 18 41 42 5 5 2V 5 2V XA52P1 17 18 41 42 6 4aV 4aV XA53P1 11 3a 7 4aV 4aV XA53P1 11 3a 8 10V 10V XA53P1 12 13 31 32 g 10V 1aV XA53P1 12 13 31 32 1a GND av A62 STAR GND 11 GND av A62 STAR GND 12 5 2V 5 2V XA53P1 1B 36 13 5 2V 5 2V XA53P1 18 36 14 HULR T...

Page 110: ... 12 2r LGND l j r V P I 5 INJ M I _____C J t t I3 281 C J PI 6 IN M2 Pl 3 1Nl M3 f 1 f t 14 29 r c Pl 4 1Nl M4 Pl l IN M5 C J t f t 15 30 t c J Pl 2 1N LMNE E9 El3 I 3 R3 CG 8 j 9 t 10 II 5000PF E24 i u __ o4 0Vc J 12 E23 C9 E26 13 5000PF LMNE 2 _fl r 9 94 4 Q i P J if t t 14 E25 t t I5 7 GNO E2 P2 14CINl HULR t i t 1 t l O 5000PF S 2V r QI 7 I _ _ _ _ 1 10 TUNE GROUND i II E f t I2 11 r C 1 J t t...

Page 111: ...10 MHz COARSE and FlNE Frequency Adjustments PIN A51W1P1 1 2 3 SIDE VIEW SIGNAL 22V GND OVEN HOVC 4 GND CASE GND OSCILLATOR 5 20 A51W1 1 2 3 4 5 6 BOTTOM VIEW A51J1 Figure 8B 16 A51 JO MHz Reference Oscillator Component Location Diagram 8 153 8 154 Scans by HB9HCA and HB9FSX ...

Page 112: ...1 20V REF DSC PIN 1 OV 20V 2 GND PIN 2 ov 3 HOVC PIN 3 3V DVEN WARM 4 GND PIN 4 ov 5 22V PIN 5 22V Note Refer to M N and Reference Loops Troubleshooting Block Diagram and A62 Motherboard Wiring List for signal source and destination information 8 155 8 156 Scans by HB9HCA and HB9FSX ...

Page 113: ...Scans by HB9HCA and HB9FSX ...

Page 114: ...nce Phase Detector A30 100 MHz VCXO VoltageControlledCrystalOsc A31 M N Phase Detector r 32 A33 434 A36 A37 A38 A39 ft 40 0 A41Y A42 i 13 A44 A45 A46 PLL1 VCO Voltage PLL1 Divider PLL1 IF PLL3 U converter PL i c Ontrolleij Ost PLL2 _if PLL Qjiid r 2 FLL2Discritninatoi viG osciliaior YOJ Directional Coupler 7 GHz Low Pass Filter A47 A iir M9 Sense Resistor Assembly YO circuit _ SYT_M circuit I IH I...

Page 115: ...escription PLL1 Loop Description TROUBLESHOOTING TO ASSEMBLY LEVEL 20 30 Loop Troubleshooting Block Diagram REPAIR PROCEDURES INDIVIDUAL ASSEMBLY SERVICE SECTIONS A36 PLL1 VCO A37 PLL1 Divider A38 PLL1 IF A39 PLL3 Upconverter A40 PLL2 VCO A41 PLL2 Phase Detector A42 PLL2 Divider A43 PLL2 Dliscriminator 20 30 LOOP MAJOR ASSEMBLIES LOCATION DIAGRAM Scans by HB9HCA and HB9FSX ...

Page 116: ...leshooting Block Diagram Circuit Descriptions Component Location Diagrams Pin I O Tables and Schematic Diagrams for all 20 30 Loop Assemblies LIST OF ASSEMBLIES PLL2 Assemblies A40 PLL2 VCO Voltage Controlled Osc A41 PLL2 Phase Detector A42 PLL2 Divider A43 PLL2 Discriminator PLL3 Assembly A39 PLL3 Upconverter PLLl Assemblies A36 PLLl VCO Voltage Controlled Osc A37 PLLl Divider A38 PLLl IF 8 159 8...

Page 117: ...he 20 30 Loop remains fixed and the YO is swept lock and roll sweep These assemblies form a frequency synthesizer with the following performance characteristics Fixed frequency output range from 20 to 30 MHz Analog sweep widths between 100 Hz and 5 MHz CW frequency resolution as low as 1 Hz The 20 30 Loop contains three phase locked loops that are used in three different configurations to achieve ...

Page 118: ...on is 5 kHz so the divided output will have 1 kHz resolution The VCO can be swept a maximum of 25 MHz so the divided output will sweep up to 5 MHz sweep widths This path is used directly as one of the three configurations of the 20 30 Loop Notice that PLLl and PLL3 are not used at all in this configuration CONFIGURATION 2 3 These configurations are used in sweep widths 100 kHz For sweep widths bel...

Page 119: ...quency the PLL3 output will also change frequency with the same resolution and sweep width but at a higher operating frequency PLLl functions as a programmable offset to the output of PLL3 Like PLL3 it will not effect the resolution since it is an offset The selected PLL2 divided output is still determining the resolution and sweep width of the signal PLLl contains a 200 to 300 MHz VCO that will b...

Page 120: ... Hz and CW Mode 8 164 Model 8340A Service Table 8C l 20 30 Loop Parameters Loops Used PLL2 VCO Divide divided by 10 PLLl PLL2 PLL3 by PLLl x 5 x x x 25 10 x x x 500 10 Total 20 30 divide output number resolu tion 5 1 kHz 250 20 Hz 5000 1 Hz Scans by HB9HCA and HB9FSX ...

Page 121: ...NSERT IN FRONT OF PAGE 8 165 8 166 JI I 60 300kHz IOHz STEPS 3 eMHz 200Hz STEPS J3 I 76 160MHz 0 r I _j SEE ADJACENT TABLE J4 L ___ _ ______ _i P O Figure 8C l 20 30 Loop Simplified Block Diagram ALL SERIALS P 0 8 165 8 166 Scans by HB9HCA and HB9FSX ...

Page 122: ... PLL2 VCO J2 76 1 SOMHz SAMPLE ll HOLD J _ J I I 60 300kHz IOHz STEPS 3 6MHZ 200Hz STEPS 1 Y I I IOMHz Od8m FROM A29 REF PHASE DF TECTOR J4 W 34 IOOMHz OdBm FROM A30 IOOMHZ vcxo J2 W35 61 O IMHz A39WI 15 30MHZ L _J IkHz STEPS SEE ADJACENT TABLE 6F O l 6MHz I I A37 PLLI DIVIDER L 3 60 13 97 PLL3 A39 PLL3 UP CONVERTER J2 IOOMHz x 1 6 I I5 30MHz ___J A36 W I I ___ J A36 PLLI VCO 160 15 156MHz 2DdBm A...

Page 123: ...ning in CW Mode DISCRIMINATOR FEEDBACK In narrow sweeps 5 MHz it is the 20 30 Loop that is being swept Since PLL2 is the loop that PLLl PLL3 and the YO Loop track its sweep accuracy will determine the instrument s sweep accuracy To improve the accuracy of the sweeps a discriminator is used in a feedback loop around PLL2 vco The discriminator is a very accurate frequency to current converter Its fr...

Page 124: ...VCO combination Since the discriminator feedback loop is still intact and the phase lock loop is now opened any voltage introduced at the input to the discriminator vco will be cancelled through negative feedback The result is a ramp in the vco frequency that will cause the discriminator output to exactly cancel the sweep ramp at the input SAMPLE AND HOLD CIRCUIT The sample and hold circuit that r...

Page 125: ...NCE LOOP Model 8340A Service 20 r 1 SAMPLE ANO lIOLO I tr Ii 1 I I I TUNE VOLTAGE FRACTIONAL DIVIDER vco 7fi 150MHz 13KH7 STEPS _____ CllANGES FREQ TO CURRENT RATIO DlSCRIMINATOR t5 20 I LINEARIZED VC0 I _ _J Figure 8C 3 Phase Lock Loop 2 Operation 6 DED OUTPUTS 5 8 169 Scans by HB9HCA and HB9FSX ...

Page 126: ... FROM PHASE FREQUENCY DETECTOR 8 170 Model 8340A Service 5V SAMPLE AND HOLD CONTROL COUNTER DOWN ANALOG INTEGRATOR DAC Figure 8C 4 PLI 2 Simplified Sample and Hold Circuit TO DISCRIMINATOR TUNE Scans by HB9HCA and HB9FSX ...

Page 127: ...s to be sent to various destinations These divided outputs are shown in Table 8C 2 OUTPUT Table 8C 2 20 30 Loop Frequency Range vs Divider Configuration OF PLL2 VCO FREQ RANGE DESTINATION Direct output of vco 75 150 MHz PLL2 FRACTIONAL DIVIDER Divided by 5 15 30 MHz used as a 20 30 output Divided by 25 3 6 MHz Sent to PLL3 Upconverter Divided by 500 150 300 kHz Sent to PLL3 Upconverter DIVIDER The...

Page 128: ...nd PLL3 Loops are used to translate the high resolution low frequency PLL2 output up to a 200 to 300 MHz range Since a translation is a fixed offset in frequency it will not change the resolution or sweep width as does dividing or multiplying After the frequency translation the output of PLLl is divided by 10 to reduce the phase lock range from 200 300 MHz to 20 30 MHz This also increases the outp...

Page 129: ...h identical low pass filters and a voltage divider filter The output of the voltage divider is sent to a varactor diode that tunes the vco 160 to 166 MHz vco The 160 to 166 MHz vco is a varactor tuned Colpitts transistor oscillator A buffer transistor output provides a 160 to 166 MHz signal that drives the MIXER PHASE LOCK INDICATOR The PHASE LOCK INDICATOR senses the outputs of the phase detector...

Page 130: ...sion sweeps and high resolution of the PLL2 Loop are effectively tra nsferred up in frequency to the PLLl vco A simplified diagram of the PLLl Loop is shown in Figure SC 6 The phase frequency detector for PLLl which resides on the A37 PLLl DIVIDER assembly operates at 5 MHz One of the phase detector inputs comes from a 10 MHz A29 Reference Phase Detector reference which is divided by two on the A3...

Page 131: ...being used in this mode and PLL2 is used by itself Fout the 20 30 output frequency can be determined by pressing SHIFT Ml and reading the right FREQUENCY MHz display Nl can be calculated from these two frequencies using the above equation As the Nl divide number changes the gain of the loop amplifier is adjusted to maintain an approximately constant loop gain This is done through FET switches on t...

Page 132: ...0 30 4L_ _ _o_ _ f otJ _T__ __ __ __ _ 1 o __ T o _ Y_ o_L _O OP GAIN SWlTCHlN i A36 PLLI VCO I I I I 1 A38 PLLI IF I _ FPLL3 NI 10 I I _ 15 T O 30t IH fnOM A40 PLL2 VCO OUTPUT SWITCH OPERATION AF POSlTHlll CIMH1 TO I OOl Hz IOOt Hr TO loOHz Figure 8C 6 160 I TO 166Lfit FROM A39 PLL3 UPCONVERTER PLLJ Simplified Diagram 8 177 8 178 Scans by HB9HCA and HB9FSX ...

Page 133: ... 5 LOW PASS i 1 _ j 140MH At APLIFIER MIXER LO Jl o l l A M PLIF ER IN LO 200 300 r 1 e i __ I J 1 L _ __ _J A43Wl I I I00 MHz ADJUST 0 1 0 75 ISOM i J I UTPUT J 1 I BUFFER J FREQUENCY DIVIDERS 75 I50Mf l z l8 2dBm 140MHz FILTER LOW PASS t r f IOdBm FILTER r o J __J l60MHz NULL O J I I_6m Hz NULL 0 l 70MH NULL o A39 PLL 3 CONVERTER IN IOOMH W36 l l2 FREQUENCY MULTIPLIER XI 6 Od8m _c _ I Jlz I t IO...

Page 134: ...Model 8340A Service TROUBLESHOOTING TO ASSEMBLY LEVEL Ref er to OVERALL INSTRUMENT TROUBLESHOOTING in the Service Introduction 8 181 8 182 Scans by HB9HCA and HB9FSX ...

Page 135: ...Model 8340A Service REPAIR PROCEDURES Refer to the REPAIR PROCEDURESn description in the Service Introduction 8 183 8 184 Scans by HB9HCA and HB9FSX ...

Page 136: ...utput goes through a switch and a filter to the 20 30 output To prevent spurious responses the oscillator is turned off for sweeps that are greater than lOOkHz but less than or equal to 5MHz LOOP AMPLIFIER A A diagram of the equivalent circuit of the loop amplifier is shown in Figure 8C 8 It functions as differential integrator due to the feedback presented by R30 C33 and R29 C34 The gain block sh...

Page 137: ...eaches about 5V at which point the hysteresis around U6B due to R24 causes U6B to return to its inactive HIGH state A mode exists where the vco may be OFF and when programmed ON will remain disabled due to noise driving the phase detector and loop amplifier such that the vco is continually driven to its OFF state To ensure that the vco will always oscillate the vco range limiter clamps the lower e...

Page 138: ...s CR2 in Block A to conduct and pull the base of Q2 to about 0 7V This sets the clamp voltage at the cathode of CR7 to about 0 7V This maximum voltage of 0 7V quarantees that the diodes will be biased on disabling the vco The output of Q5 is applied to Q4 where it is amplified and sent to A38 PLLl IF and to Block F DIVIDE BY 10 Q 11 Cl6 Rl9 Rl8 CR4 L4 Rl6 Cl7 L5 Figure 8C 9 200 300 MHz VCO Simplif...

Page 139: ...10 VCO frequency as its input DIVIDE BY 10 F Q3 is a common emitter amplifier which drives U3 through a high pass filter U3 is an ECL divide by 10 counter which generates the necessary 20 to 30 MHz from the vco output 8 188 Table 8C 3 FET Switch Programming Table Divide Active FET Number n1 ll7 Q8 ll6 3 x x 4 x 5 x x 6 x x 7 x x x 8 x 9 x x 10 x x 11 x x x 12 x x 13 x x x Scans by HB9HCA and HB9FS...

Page 140: ...OMHZ IN FOR AF 1 5MHZ Model 8340A Service J1 J2 OUT 20 aoMHZ MP17 OUT 200 SOOMHZ MP7 S PLACES j i i riin i i r r i _ MPS U5 TPS Of A 214 Figure BC JO A36 PLLJ VCO Component Location Diagram MP12 MP1S 8 189 8 190 Scans by HB9HCA and HB9FSX ...

Page 141: ... 1a GND av A62 STAR GND G 25 PH2 a TO 5V A62R13 A 11 GND av A62 STAR GND G 26 GND av A62 STAR GND G 12 1aV 1av XA53P1 12 13 31 32 THRU A62L8 TO G 27 1aV 1av XA53P1 12 13 31 32 THRU A62L8 TO G 13 12V Lil ADJ 1a 5V XA52P1 1a THRU A62L2 TO G 28 12V Lil ADJ 1a 5V XA52P1 1a THRU A62L2 TD G 14 GND av A62 STAR GND G 29 GND av A62 STAR GND G 15 5 2V 5 2V XA52P1 17 18 41 42 THRU A62L1 TO G 3a 5 2V 5 2V XA5...

Page 142: ...J L___ 3 _ 0 _ _ _ __ R _ __ _ _ R14 1000 c13 IOPF I I I I _ _ ___ __ J 5 30 MHz IN FOR AF O l 5MHz o dBm FROM A40 PLL2 VCO J4 Pl 23 1N SWI R21 147 I OVF OUTPUT SWITCH Ll3 I 2 5VF I R2 1000 6YF1 C27 i 6 8 R3 1330 DIVIDE BY 10 uzc 0 l L 9 NC 4 U IC U3 5YF I NC 12 13 16 ECL NC ECL P 14 Ill UID 1000 R4 8260 CRI U2B I11 IODD OUT Z0 30MHl CI RI 2 O L1 3 O L 1 3 JI W39 16 301 lHz A36WI D2_2 _ _ _ 5_s _ ...

Page 143: ...ber that is between 0 and 99 The pulses out of the rate multiplier are not necessarily evenly spaced but will always be X 100 times the number of input pulses to the rate multiplier Each time the rate multiplier outputs a pulse the input signal in the DIVIDE BY N block is effectively ignored for one entire input pulse This means that N l input pulses will transpire before the next output pulse wil...

Page 144: ...NPUT 8 196 Model 8340A Service 1111 N OUTPUT DISABLE COUNT FOR ONE INPUT PULSE RATE f MULTIPLIER 1111 1111 X 2 DIGIT BCD Figure 8C 12 Fractional Division Using Pulse Swallowing Scans by HB9HCA and HB9FSX ...

Page 145: ...h clock pulse until the count of 2 is reached At this time the wire OR d bits TP8 will be 0 and Ul4B pin 15 will be set up to be clocked LOW on the following clock pulse Ul4B pin 15 is LNLOAD so the counter will be loaded with the integer divide number synchronously with the next rising clock edge This operation repeats every N clock pulses unless the SWALLOW CONTROL causes HSWALLOW to go HIGH Fig...

Page 146: ...PUT CLOCK TP3J TPS WIRE OR OUTPUT TP6 LNLOAD TPl3 DIVIDER OUTPUT COUNTER CONTENTS 5 Model 8340A Service 4 3 I ASYNCHRONOUS 2 5 Figure BC 13 N Divider Operation N 5 HSWALLOW not used 4 Scans by HB9HCA and HB9FSX ...

Page 147: ... 8C 14 The things to notice in Figure 8C 14 are Whenever LOW SWALLOW ENABLE was HIGH prior to the output pulse TP13 HSWALLOW always remained LOW throughout the sequence and no input pulse was swallowed Whenever the rate multipliers Ul and U2 did output a pulse LOW SWALLOW ENABLE was left in the LOW state regardless of the previous state of the line The definition of these lines can then be stated ...

Page 148: ...BLE 0 HSWALLOW CTP5l 0 TP7 O LOW SWALLOW ENABLE 0 HSWALLOW TP6 0 TP7 o LOW SWALLOW ENABLE 0 STATE I RATE MULTIPLIER DOES OUTPUT A PULSE LOW SWALLOW ENABLE WAS HIGH STATE 412 RATE MULTIPLIER DOES NOT OUTPUT A PULSE LOW SWALLOW ENABLE WAS LOW STATE 3 RATE MULTIPLIER DOES OUTPUT A PULSE LOW SWALLOW ENABLE WAS LOW STATE 4 RATE MULTIPLIER DOES NOT OUTPUT A PULSE LOW SWALLOW ENABLE WAS HIGH Figure 8C 14...

Page 149: ...ong TTL delays compared to ECL the effect of the RlO and Cll time delay on HSWALLOW is insignificant The Ul5B pin 10 input will still go low before the clock pulse from Ul U2 arrives PHASE FREQUENCY DETECTOR E The Phase Frequency Detector compares the divider output with a 5 MHz reference frequency When the two inputs are in phase the outputs are ECL HIGH approximately 4 volts with very narrow pul...

Page 150: ...on the de voltage at the base of Q3 is lower than that at the base of Q2 so Q3 is ON and Q2 is OFF If the loop unlocks the input to the phase lock indicator consists of varying width pulses the average de value of which is about half way between a logic LOW and HIGH The voltage divider consisting of R35 and Rl5 causes the voltage at Q2 base to be lower than that at Q3 base so Q2 turns ON indicatin...

Page 151: ...fS filfil B U2 us W1 IN PLL1 IF TP2 U3 TP U1 TPS TPS U11 B 000000000000000000 19 P1 19 36 us CD J U7 TP11 TP13 U1S TP U1S 10 TP12 N i a 1c1ril TP1ll Figure BC 15 A37 PLLJ Divider Component Location Diagram 081 ON PLL1 lfLOCK MP16 MP13 8 203 8 204 Scans by HB9HCA and HB9FSX ...

Page 152: ... TO 5V E XA36P1 24 29 GNO ov A62 STAR GNO H 12 PH2 0 TO 5V E XA36P1 25 30 GNO ov A62 STAR GNO H 13 GNO ov A62 STAR GNO H 31 GNO ov A62 STAR GNO H 14 GNO ov A62 STAR GNO H 32 GNO ov A62 STAR GNO H 15 GNO ov A62 STAR GNO H 33 GNO ov A62 STAR GNO H 16 GNO ov A62 STAR GNO H 34 GNO ov A62 STAR GNO H 17 GNO ov A62 STAR GNO H 35 GNO ov A62 STAR GNO H 18 5 2V 5 2V XA52P1 17 18 41 42 THRU A62L3 TO H 36 5 2...

Page 153: ... 1 I FRACTIONAL DIVIDE QI 4t 1 5VF 1000 U2 I _ __ _ Y cc v U4B HiVF U14A 6 1 c R FF U13C 1000 IN 10 MHz OdBm W34 JI 022 ID lJ7C FROM 2 1 II i 14 I REFERENCE L I _ NOTE 3 i otm _ _ J t _ V N N _ 61 1 1000 l C4 7 O v I 022 v LOW SWALLOW ENABLE V 7 2 ID Ul6 D NC O g I C h t 1 f J o _ ______ __ R I g 1 v FF B IJ R Ff 7 17 U I 6A I t i t 4 R FF I 1 L __ Q___ R25 ooO vw DS 5 R22 I000 ___ ___ _ _ _ __ I ...

Page 154: ... Pass Filter attenuates the harmonics of the RF signal input The 10 dB pad RlO Rll and Rl2 reduces the RF signal input from approximately 20 dBm to approximately 30 dBm IF INPUT AMPLIFIER C The IF INPUT AMPLIFIER has an input filter to partially filter the RF and LO signals from the mixer The amplifier Q3 has emitter degeneration Rl7 to reduce distortion IF OUTPUT AMPLIFIER D The IF OUTPUT AMPLIFI...

Page 155: ...m I J lc1 I J lc1al I i lc21I j Ill u 11 I J I U1 I I I _ _ lc2sl E E u LB LS 000000000000000 A 21 1 5 16 15 P1 30 L11 1B5MHZ NULL Figure BC 17 A38 PLLJ IF Component Location Diagram MP2 7 MP10 12 MP17 1S CTYPICAL 3 PLACES MP13 MP15 MP16 L13 170MHZ NULL L12 1BBMHZ NULL 8 211 8 212 Scans by HB9HCA and HB9FSX ...

Page 156: ... ov A62 STAR GND F 10 GND ov A62 STAR GND F 25 GND ov A62 STAR GND F 11 GND ov A62 STAR GND F 26 GND ov A62 STAR GND F 12 10V 10V XA53P1 12 13 31 32 THRU A62L8 TD F 27 10V 10V XA53P1 12 13 31 32 THRU A62L8 TD F 13 12V UI ADJ 10 5V XA52P1 10 THRU A62L5 TD F 28 12V UI ADJ 10 5V XA52P1 10 THRU A62L5 TO F 14 GND ov A62 STAR GND F 29 GND ov A62 STAR GND F 15 GND ov A62 STAR GND F 30 GND ov A62 STAR GND...

Page 157: ...ANCE VALUES SHOWN ARE IN OHMS CAPACITANCE JN NICROFARAOS 1 AND INDUCTANCE IN MICROHENRIES UNLESS OTHERWISE NOTED R10 Rl2 F INPUT AMPLIFIER 3 JI A38WI AND A38W2 CENTER CONDUCTORS ARE ELECTRICALLY CONNECTED TO THE PC BOARD THROUGH SOLDERED 2 GUAGE FINE WIRES THEIR OUTER CONDUCTORS A RE CONNECTED 100 0 UI DOUBLE BALANCED fAIXER CCASE 3 T 100 v I I IF I I I I I I SHIE LDING C AN 1 I I I I I I Ll4 0 22...

Page 158: ...enerates 160 MHz by dividing the 100 MHz input reference signal by five and then selecting the eighth harmonic U3 is an ECL bi qinary counter that is connected so that the output skips one pulse every five input counts as can be seen from the waveforms in Figure 8C 19 threshold 100 MHz REF Figure BC 19 A39 PLL3 Frequency Multiplier Waveforms U3 OUTPUT The net effect of the pulse skipping is to pro...

Page 159: ... Lll C33 C36 C37 and CR3 a varactor diode C33 and C36 provide a capacitive divider for the signal that is fed back into the emitter of Ql Lll is adjustable allowing the center of the vco tuning range to be varied Q2 is connected in a common base configuration and is used by PLLl as a buffer amplifier for the 160 166 MHz output Q4 is connected in a common emitter configuration and is used as a buff...

Page 160: ...tector differential outputs are the inputs to the LOOP AMPLIFIER Each of the differential inputs is passed through identical low pass filters RS R9 C2 R6 RlO and C3 C9 Rl6 C8 and Rl7 provide a large de gain for the loop amplifier while insuring that each of the differential inputs see the same impedance over all frequencies Rl4 Rl5 and C7 form an ac voltage divider which sets the loop bandwidth to...

Page 161: ... by R23 and summed into the inverting input of UlA The inverted outputs of the flip flops are tied together wire or and input to the non inverting input of UlA Cl filters out the high frequency components of the flip flop outputs so the phase lock indicator is looking at the average voltages on each input When the inverting input of UlA is more positive than the non inverting input the indicator w...

Page 162: ... liJ LDCK MP1 MP5 MP1B 5 PLACES J1 OUT 160 16GMHZ C41 C42 ffi fil R44 U I Figure 8C 21 A39 PLL3 Upconverter Component Location Diagram MP1 1 L16 160MHZ PEAK L17 160MHZ PEAK cso 160MHZ PEAK J I 0 15 SMHZ 27DBM 8 221 8 222 Scans by HB9HCA and HB9FSX ...

Page 163: ... GND H 24 GND ov A62 STAR GND H 10 GND ov A62 STAR GND H 25 GND av A62 STAR GND H 11 GND av A62 STAR GND H 26 GND av A62 STAR GND H 12 1aV 10V XA53P1 12 13 31 32 THRU A62L4 TD H 27 1aV 10V XA53P1 12 13 31 32 THRU A62L4 TD H 13 GND ov A62 STAR GND H 28 GND ov A62 STAR GND H 14 GND ov A62 STAR GND H 29 GND ov A62 STAR GND H 15 5 2V 5 2V XA52P1 17 18 41 42 THRU A62L3 TD H 30 5 2V 5 2V XA52P1 17 18 41...

Page 164: ... l Hz o rp p o 2v FROM A40 PLL2 VCO J3 FOR ll 5 _o IMHz 10 U6B I 0 I l 4 1960 USC Ill II 4700 U4F 4roo U5 TP 2 TP3 eel u 1 i N OTES I REFER TO THE SERVICE SF CTION INTRODUCTION l OR OETA IL ED SCHEMATIC DIAGRAM SYMBOLOGY NOTES 2 RESISTANCE VALUES ARE HI OHMS CAP CITMICE IN l IICRO ARADS AND INDUCTANCE IN l IICROHENRIES UNLESS OTHERWISE NOTED I c o JI 160 166MKi j r 1___ J M B ll 160 IBBMHz R33 NOT...

Page 165: ... will be unaffected by any voltage fluctuations on the inductors The VCO tuning voltage at TPl in vco Block B is a function of the current from the A43 PLL2 Discriminator flowing through the equivalent resistance of Rl R5 which is essentially a current to to voltage converter The tuning current passes through the 50kHz filter and into Rl R5 Since the varactors CR1 CR4 are reverse biased negligible...

Page 166: ...s Block D providing low input impedances In the normal case Rl4 and Rl5 dominate If Q3 or Q4 are defective the vco may not oscillate since its load will no longer be dominated by Rl4 and Rl5 75 150 MHz OUTPUT BUFFER C Q4 is a grounded base amplifier which isolates the vco from the load circuits The output of Q4 is filtered attenuated and used to drive the A42 PLL2 Divider A 13 dB attenuator R20 R2...

Page 167: ...Model 8340A Service V QI r I L4 AND L5 I CR2 I I CR I CR4 I I I I L ___________ J OUT LOAD Figure 8C 23 Equivalent VCO Resonant Circuit 8 229 Scans by HB9HCA and HB9FSX ...

Page 168: ...8 230 76 MHz TO 100 MHZ U3 5 Model 8340A Service 16 MHz TO 30 MHz _ U2 6 2 3 MHz TO 6 MHz r a Figure 8C 24 Simplified Divider Circuit UI 6 2 f 0 16 MHz TO 0 3 MHz Scans by HB9HCA and HB9FSX ...

Page 169: ...0 30 MHz output 0 1 5 MHz DELTA F SWITCH F For delta F or sweep widths of 0 1 to 5 MHz the 15 to 30 MHz output is used The output of U3 in Frequency Dividers Block D is routed through U6D U7D and Tl This combination serves as a switch with 90 dB of isolation in the off state The TTL signal SWl from the A42 PLL2 Divider on Pl 24 controls this switch For maximum isolation the two gates U6D U7D are c...

Page 170: ...S MP5 MPS 1 16 Model 8340A Service J1 J2 JS W1 75 TO 150MHZ 15 TO aoMHZ oM Z VC O TUNE IN MP10 OUT OUT AF _ 1MHZ P1 15 so J4 15 SOMHZ OUT FOR AF MP11 MP7 1 5MHZ A 22 82 45 Figure 8C 25 A40 PLLJ VCO Component Location Diagram MPS 8 233 8 234 Scans by HB9HCA and HB9FSX ...

Page 171: ... SENSE 4aV XA53P1 11 3a XA53P1 23 A 26 4aV 4aV SENSE 4aV XA53P1 11 3a XA53P1 23 A 12 10V 10V XA53P1 12 13 31 32 G 27 1aV 1aV XA53P1 12 13 31 32 G 13 2aV 2aV XA52P1 16 4a G 28 2aV 2aV XA52P1 16 4a G 14 GND av A62 STAR GND G 29 GND av A62 STAR GND G 15 5 2V 5 2V XA52P1 17 18 41 42 G 3a 5 2V 5 2V XA52P1 17 18 41 42 G A single letter in the source or destination column refers to a function block on th...

Page 172: ...NCE IN MICROHENRIES UNLESS OTHERWISE NOTED Rl6 619 ID BVF R20 R22 NOTE 3 L r TO M2 PLL2 o 9 7 5 I 3 JI 1J2 J3 J 4 AND A 40W I CENTER CONDUCTORS ARE ELECTRICALLY CONNECTED TO THE PC BOARD THROUGH SOLDERED 24 GAUGE F NE WIRES THEIR OUTER CONDUCTORS ARE ELECTRICALLY CONNECTED TO PC 80ARO GROUND THROUGH MECHANICAL SCREW CONNECTIONS IN THE ASSEMBLY COVER PLATE FREQUENCY DIVIDERS CII R14 I0001 F 75 RIB ...

Page 173: ...g in approximately zero current flow through the 50 kHz low pass filter LPF consisting of C2 Ll and C3 C4 is used to stabilize the two grounds between the sample and the hold modes Q8 is ON when High Lock Enable HLE2 is HIGH A pulse from the PLL2 Divider on Pl pin 19 clocks the Q output of U6A pin 5 HIGH turning Q9 off With both Q9 and QlO off Q8 will sink current out of the 50 kHz LPF A subsequen...

Page 174: ...error voltage and the analog integrator is left with a much less significant portion When the analog error voltage TP3 in ANALOG INTEGRATOR SAMPLE AND HOLD Block C goes below 4 7V Q5 is turned ON and its collector voltage is pulled down to l 4V At this point CR4 and CR3 become forward biased clamping U2 and preventing further negative movement of TP3 Simultaneously the input of U7B will have been ...

Page 175: ...cy signal path that bypasses the slow responding integrators and speeds up the phase locking process U4 CS C9 Rl2 and the internal lOK ohm resistor in UlO of DIGITAL INTEGRATOR XBlock B between pins 1 and 16 form an active 3kHz low pass filter The output of U4 is the tuning voltage that goes to the A43 PLL2 Discriminator board and effectively changes the gain of the discriminator to tune the PLL2 ...

Page 176: ... 8340A Service MPS P1 MP7 15 30 TP6 TP7 MP2 MPS HUL2 MP4 II DET OUT MP1 MP15 l c11 L2 rnJ 08340 60047 A 2318 45 MP7 Figure 8C 27 A41 PLI 2 Phase Detector Component Location Diagram 8 243 8 244 Scans by HB9HCA and HB9FSX ...

Page 177: ...NE 0 TO 7 VOLTS D XA43P1 28 9 24 10 GND ov A62 STAR GND F 25 GND ov A62 STAR GND F 11 GND ov A62 STAR GND F 26 GND ov A62 STAR GND F 12 10V 10V XA53P1 12 13 31 32 F 27 10V 10V XA53P1 12 13 31 32 F 13 20V 20V XA52P1 16 40 F 28 20V 20V XA52P1 16 40 F 14 GND ov A62 STAR GND F 29 GND ov A62 STAR GND F 15 5 2V 5 2V XA52P1 17 18 41 42 F 30 5 2V 5 2V XA52P1 17 18 41 42 F A single letter in the source or ...

Page 178: ... 15 I CT 15 GI LOAD R 1 CT O CTRl6 I D I I D 1 0 4 I D 8 I 12 13 5VF U9 16 l CT l5 12 I LO C r 0 13 CTRIS I 2 4 1_ _ 8 e I OUTPUT AMPLIFIER INDICATOR 5VF R25 TOK R26 1211 IDVF R10 464K R I I 6190 j_ Cl4 01 NC NC R27 237K TP6 TP7 r DAc 20VF UIO OA C10 RFB IS R23 3160 7V 15 VREFl II 20VF R2B 422K cg 0047 IOVF 2DVF IOVF 12 2 2 s __ t P i 3 23 0UTl U4 UI 5VF R13 2150 C24 COVER 5000PF TP7 TEST POINT iI...

Page 179: ...he PLL2 DIVIDER Refer to the Frequency Range and CW Mode Accuracy Performance Test for use as a troubleshooting aid LATCHES A Latches Ul2 Ul3 and Ul4 store the BCD numbers used to preset the various counters on the PLL2 Divider board The schematic Figure 8C 32 shows the relationship of each output line to the frequency of the PLL2 vco The frequency of the VCO can be determined by adding the total ...

Page 180: ... 11 mode can be thought of as a pulse swallowing mode since it requires one more pulse than the divide by 10 mode to produce the same output pulse The output of the prescaler after being converted to TTL signal levels by UlB and buffered by U9C becomes the clock signal for all the other circuits of the fractional divider Everything is referenced to this clock signal DIRECT DIVIDE B The direct divi...

Page 181: ...WALLOW was asserted HIGH However it should be mentioned that LSWALLOW is not forced LOW until one clock pulse after LRESET Thus with the integer counter preset to 5 the LSWALLOW line was LOW for 5 clock pulses which means the prescaler was in divide by 11 mode for 5 clock pulses If the counter had been preset to 4 one additional clock pulse would have been required so that the divide by 11 mode wo...

Page 182: ... input pulses So 32 out of 100 cycles the prescaler is swallowing one less pulse than it normally would have causing the input frequency to decrease the output frequency is fixed because of phase lock In fact the amount of decrease is 32 100 X 500 kHz or 160 kHz In terms of pulses and using the previous example of divide by 215 we would have 32 cycles of divide by 214 and 100 32 or 68 cycles of di...

Page 183: ...ESCALER DIRECT DIVIDE CLOCK 20 Q 1 1 7 DIVIDED OUTPUT I 0 I I LSWALLOW LRESET CLOCK SYNCHRONIZER TO 29 Q INTEGER COUNTER STOP SWALLOW LRESET STOP SWALLOW EARLY HLE2 Figure 8C 29 PLL2 Divider Simplified Block Diagram 8 253 Scans by HB9HCA and HB9FSX ...

Page 184: ... COUNT U3A Q 8 254 23 24 25 26 10 10 FOR 16 CYCLES 27 Model 8340A PRESET TO 8 PRESET TO 6 10 Service II 12 13 14 15 16 17 18 rIF UJ IQ HIGH STOP SWALLOW EARLY J r 11 1 10 JI FOR 5 CYCLES Figure BC 30 Partial Circuit Timing for 215 Example 19 20 21 22 Scans by HB9HCA and HB9FSX ...

Page 185: ...PG MP7 MP1 MP4 JN U5 IJ us U12 MP3 TP3 US r l j U10 LJ fil J B 08 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 017 I GG 1 19 P1 16 36 Figure SC 31 A42 PL12 Divider Component Location Diagram J1 10 MHZ lN MP5 8 255 8 256 Scans by HB9HCA and HB9FSX ...

Page 186: ... N2 TTL LOW TRUE 8 C 10 GNO ov A62 STAR GNO H 28 GNO ov A62 STAR GNO H 11 29 12 30 13 31 14 SW2 TTL A XA40P1 22 32 SW1 TTL A 15 10V 10V XA53PH2 13 31 32 NOT USED 33 10V 10V XA53PH2 13 31 32 NOT USED 16 20V 20V XA52P1 16 40 NOT USED 34 20V 20V XA52P1 16 40 NOT USED 17 GNO ov A62 STAR GNO H 35 GNO ov A62 STAR GNO H 18 5 2V 5 2V XA52PH7 18 41 42 H 36 5 2V 5 2V XA52P1 17 18 41 42 H A single letter in ...

Page 187: ...Scans by HB9HCA and HB9FSX ...

Page 188: ...t the summing node This forms a frequency locked loop with the discriminator as the feedback element The result is the equivalent of having a very linear VCO See Figure 8C 33 This discriminator linearized VCO is used inside a phase lock loop In this configuration the phase lock loop tunes the VCO indirectly by changing the gain of the discriminator This provides the capability to establish an accu...

Page 189: ...lified and level shifted by Q6 and Q7 At the begining of a cycle both inputs to U7D are LOW When Q7 collector goes HIGH U7D output goes LOW saturating Qll and causing resonator L4 ClS and Cl6 to ring at 5 2 MHz This damped oscillation appears at Q9 collector is clipped by QlO and used to drive counter U6 QlO is a comparator The signal appears across LS driving the base of QlOA and QlOB in opposite...

Page 190: ...the summing point of the discriminator loop The average value of this current is directly proportional to the input frequency being about 1 5 mA at 0 3 MHz The 0 3 MHz Adjust R9 in the U4 feedback loop adjusts the the discriminator gain by changing the amplitude of the 1 6 microsecond current pulses into the filter The tuning voltage input N2 Tune from the A41 PLL2 Phase Detector Pl pin 28 is also...

Page 191: ...in a table on the schematic diagram Figure 8C 35 for any combination of HIGHS and LOWS on these latched control lines Switch UlA when closed passes the O to 10 volt ramp un attenuated to the summing junction in SUMMING AMPLIFIER Block F Switch UlB and switch UlC are used for cancellation of the ON resistance of switch UlA Cancellation is achieved by scaling the sweep ramp with R29 and switch UlC a...

Page 192: ...k inputs The phase lock feed forward path reduces the lock time by feeding the discriminator tune voltage ahead to the output current source To achieve a low noise junction there is an optimum input im pedance to be presented by Q2 This requires a constant emitter current Ql is used to achieve a constant Q2 emitter current of about 0 14 mA Q2 will conduct only enough current to cause a 0 7 V drop ...

Page 193: ...I 7V 300KHz 7 ADJ DISCRIMINATOR BLOCK A AND B SAMPLE AND HOLD lo AVG 6mA MHz TP6 vco TUNE NON INVERTING ________ VOLTAGE l vco I 160MHz TO I 75MHz I T 6 J 7 ADJ A40 PLL2 VCO INTEGRATOR TO CURRENT _______ CONVERTER I ______________________________________J EQUIVALENT TO LINEAR VCO Figure 8C 33 Simplified A43 PLL2 Discriminator Diagram IOMHz REF FROM VCXO TO PLL I AND PLL3 Scans by HB9HCA and HB9FSX...

Page 194: ...8340A Service FEED FORWARD PATH I I CURRENT SOURCE B _J R50 PRETUNE R43 D R42 R4I I 5MA 1 t R40 C23 I R44 UI r 1 I A 0 7V I I I I B I I c R45 TUNING VOLTAGE p 1 28 R2 PIO AF SWEEP ATTENUATOR E Figure 8C 34 Simplified ll F Sweep Attenuator Circuit vco NY TUNE 8 267 8 268 Scans by HB9HCA and HB9FSX ...

Page 195: ...NE OUT 2MHZ MP16 MP12 aMHZ MP11 1s aoMHZ IN MP1 R29 U1 R32 U2 c ru I R2S 0 0 CR2 us U11 U12 ca o i Clf OJ C5 cm 000000000000000000 P1 19 1S 86 Figure 8C 35 A43 PLLJ Discriminator Component Location Diagram MP15 MP3 MPS MPS MP11f MP2 MP10 8 269 8 270 Scans by HB9HCA and HB9FSX ...

Page 196: ...JV REF 7V c XA41Pl 7 27 GND ov A62 STAR GND H 10 N2 TUNE RTN ov XA41Pl 8 c 28 N2 TUNE 0 TD 7V XA41Pl 23 B G 11 GND ov A62 STAR GND H 29 GND ov A62 STAR GND H 12 GND ov A62 STAR GND H 30 13 GND ov A62 STAR GND H 31 14 GND ov A62 STAR GND H 32 15 10V 10V XA53P1 12 13 31 32 H 33 10V 10V XA53P1 12 13 31 32 H 16 20V 20V XA52P1 16 40 H 34 20V 20V XA52P1 16 40 H 17 GND ov A62 STAR GND H 35 GND ov A62 STA...

Page 197: ...TA Ul2 7 64 6 12e 5c 250 4 512 MSB C26 l I 30PF TPI FF Pl 24 1NJ 086 C l JI J l fDo fJl O_J r oc c_1 0 I N VR RFB 2 7 I R42 R4l 11 8 13 4K BOO 7V J _ VREF 2 CR2 Y NC Pl S INJ 087 C J 6c io fJ7 ___ P1 25 IN 088 C l J1 l 3cjco fJl12___ Pl 7CIN 089 c 4 jDo j 5 dl c2lr j UI0 f CW J 2 I 4 p I 0 2MHZ O v 2 v2 I OVF NC ADJUST CURRENT R40 I p1 26 IN DBI C J J1 4cJco fJl 5 p a IN DBI I C J c io t 2 ____ I ...

Page 198: ...Scans by HB9HCA and HB9FSX ...

Page 199: ... 15 A34 Reference MINMotherboard 5 A35 Rectifier 4 A36 Pll1 VCO Vol1age Controlled Osc 36 A37 Pll1 Divider 37 A38 Pll1 IF 38 A39 Pll3 Upconverter 39 A40 Pll2 VCO Voltage Controlled Osc 40 I Top View A41 Pll2 Phase Detector 41 A42 Pll2 Divider 42 A43 Pll2 Discnminator 43 A44 YIG Oscillator YO 18 A45 Directional Coupler 18 A46 7 GHz low Pass Filler 18 _________ A47 Sense Resistor Assembly YO circul1...

Page 200: ...Sweep Generator and YO Loop Detailed Troubleshooting Block Diagram REPAIR PROCEDURES INDIVIDUAL ASSEMBLY SERVICE SECTIONS A44 VIG Oscillator A45 Directional Coupler A46 7 GHz Low Pass Filter A47 Sense Resistor Assembly Primary Reference A48 YO Loop Sampler A49 YO Loop Phase Detector A50 YO Loop Interconnect A54 YO Pretune Delay Compensation A55 YO Driver A58 Sweep Generator AT215 dB Attenuator SWE...

Page 201: ...e the YO according to the mode of operation selected The Sweep Generator consists of the following assemblies AS4 YO Pretune Delay Compensation Assembly ASS YO Driver Assembly AS8 Sweep Generator Assembly The YO Loop phase locks the YO at the appropriate frequency when the instrument is operated in the CW and Manual Sweep modes The YO Loop consists of the following assemblies A44 YO Assembly A4S P...

Page 202: ...n be in one of three conditions single band sweep multiband sweep or narrow band sweep CW MANUAL SWEEP OPERATION When the CW mode is selected the sweep Generator YO Loop Circuitry phase locks the YO at the appropriate frequency The processor addresses and sends a number to the A54 YO Pretune Delay Compensation board which is converted to a voltage VDAC and summed with the constant DC voltage VREF ...

Page 203: ...ard also generates a 0 to lOV voltage ramp MKR RAMP which has the same duration as VSWP Because of the inherent delay characteristics of the YO during sweeps a ramping compensation voltage VCOMP is summed with PRETUNE in the A55 YO Driver VCOMP is generated by summing correction data from the processor with the VSWP ramp This is done in the YO Delay Compensation portion of the A54 YO Pretune Delay...

Page 204: ... A49 YO Loop Phase Detector keeps the YO phase locked to this signal for the duration of the sweep For narrow band YO sweep widths between 500 kHz and 5 MHz PRETUNE is also swept VSWP summed in a proportional amount so that the pretuned YO frequency will remain within the capture range of the YO Phase Lock Loop This is in addition to the phase locked error correction by YO TUNE For YO sweep widths...

Page 205: ...ge on the A54 YO Pretune Delay Compensation board The resulting voltage ramp produces a current ramp from the A55 YO Driver board which in turn sweeps the frequency of the YO VSWP is also used on the A54 YO Pretune Delay Compensation board to produce another negative going ramp called VCOMP This is added to PRETUNE on the A55 YO Driver board to compensate for the eddy current induced swept frequen...

Page 206: ...he following three events takes place 1 LBX Low Bandcross goes LOW The A57 Marker Bandcross board pulls LBX and HSP LOW at bandcrossings and at the end of the sweep The A58 sweep Generator pulls LBX LOW if there is an instrument malfunction which allows VSWP to go beyond its normal limits 2 LSSP Low Stop SweeP on the rear panel is pulled LOW Note this line is meant for special dedicated applicatio...

Page 207: ...y the A58 sweep Generator board A buffered version of this SWEEP OUTPUT is available on the front and rear panels MARKER RAMP is a monotonic ramp with pauses for bandcrossings It starts at zero at the beginning of each sweep It reaches five volts at the center frequency of the sweep and goes to ten volts at the end of the sweep Scans by HB9HCA and HB9FSX ...

Page 208: ... Low Voltage sweep disable is LOW to shunt out any unwanted noise contribution from the VSWP line YO Tune The YO TUNE voltage is generated by the A49 YO Loop Phase Detector from the 20 30 MHz input from the 20 30 Loop and the Sampler IF which is the down converted product of the YO RF OUTput and the Nth harmonic of the M N OUTput The A45 Preleveler couples a portion of the YO Output back through t...

Page 209: ...s a linear function of the desired YO frequency The OFFSET adjustment varies the offset of the curve the GAIN adjustment varies the slope These two adjustments are used to ensure the tuning accuracy of the YO versus PRETUNE voltage over its full range of operating frequency OFFSET has greater effect on the low end of the range 2 30 GHz and GAIN has greater effect on the high end 6 99 GHz The Volta...

Page 210: ...54 YO PRETUNE DELAY C0 11PENSATION1 RETRACE KICK PULSE SATION PRETUNE VCOMP L________________________ J A58 SWEEP GENERATOR SWEEP TIME SWEEP CONTROL LOGIC SCALING RESISTORS RESET RAMP GENERATOR SUMMING AMPLIFIER A47 SENSE RESISTOR ASSEMBLY PRETUNE I I I VOLTAGE TO CURRENT CONVERTER I I I I I SWEEP WIDTH ATTENUATOR Figure 8D l Sweep Generator and YO Loop Block Diagram VSWP BVSWP 20 30 SWP MKR RMP 8...

Page 211: ... unlock condition exists when the YO indicator is flashing In the majority of cases the error condition will occur in the CW MANUAL mode and the troubleshooting should be done in this mode first If the YO Loop will not acquire phase lock in CW MANUAL at all frequencies then it wil also not function properly in the SWEPT mode To troubleshoot in the CW MANUAL mode answer the following questions 1 AR...

Page 212: ...heck the YO TUNE voltage at TP3 TUNE on the A55 YO Driver When the loop is operating properly the YO TUNE voltage should be close to zero volts If YO TUNE is within the range of nominally 6 0 V de then the YO Loop is locked and the UNLK indication Ts false proceed to question 5 If YO TUNE is at maximum positive or negative approximately 6 9 V then the YO Loop is unlocked go to question 6 NOTE In t...

Page 213: ... SHIFT Ml on the front panel see question 7 above The correct power is 0 dBm 3 dB If no power is present or if the power and or frequency is incorrect then troubleshoot the 20 30 Loop If the signal is correct then proceed to question 9 9 IS THE YO FREQUENCY CHANGE PROPORTIONAL TO YO TUNE Record the actual YO frequency Then disconnect YO TUNE and FM COIL DRIVE cables A49Jl and A49J2 Place a 50 Ohm ...

Page 214: ...resent or if the power is incorrect then proceed to question 13 13 IS PRE LEVELER POWER OUT OF A45J2 OK Check the coupled back RF power out of the A45 Preleveler at A45J2 If no signal is present or the power level is incorrect then troubleshoot the A45 Preleveler If the RF power is correct then troubleshoot the A46 7 GHz Low Pass Filter and connecting cables 14 IS PRE LEVELER POWER OUT OF A45J3 OK...

Page 215: ... Pretune Delay Compensation board If VSWP is much different than zero volts then proceed to question 19 19 IS LVSX LOW If the VSWP voltage is much different than zero volts it will affect the PRETUNE voltage only if the Sweep Disable Switch A54 Block E is also not operating correctly If LVSX Low Voltage sweep Disable is HIGH or intermittent then troubleshoot the A59 Digital Interface board If LVSX...

Page 216: ...mv added from VSWP to PRETUNE will result in the YO being tuned outside of the capture range of the YO Phase Locked Loop If VSWP is zero then proceed to question 3 If VSWP is not zero then troubleshoot the A58 Sweep Generator board 3 IS THE YO KICK PULSE OK Check to see that the YO Kick Pulse is being generated correctly The LKICK line should be 2V for a time at the start of the sweep and then ret...

Page 217: ...eing driven by the A57 Marker Bandcross board and LRSP being driven by the A59 DIGITAL INTERFACE board LBX is an open collector line that can be driven by both the A58 Sweep Generator and A57 Marker Bandcross boards HSP is coupled to LBX on the A57 Marker Bandcross board so that if LBX is pulled down the A57 Marker Bandcross board pulls down on HSP also If the instrument is in the continuous sweep...

Page 218: ...g used For example if the instrument is sweeping from 8 to 10 GHz the instrument sweep width is 2 GHz However this is the second harmonic of the YO so that the YO is sweeping from 4 to S GHz a sweep width of 1 GHz The sensitivity of VSWP is 2 volts GHz of YO sweep width In the example above VSWP should be a ramp starting at zero and going to 2 volts If VSWP is correct then look at PRETUNE TP3 on t...

Page 219: ... sweep width 100 KHz 50 KHz volt YO sweep width 10 KHz 10 KHz volt YO sweep width 1 KHz 1 KHz volt YO sweep width 500 Hz 500 Hz volt YO sweep width 100 Hz 50 Hz volt verify that VSWP is not sweeping more than 0 O to 15 mv and tha t 20 30 SWP is correct If both of these are correct the problem is most likely in the 20 30 Loop 8 297 8 298 Scans by HB9HCA and HB9FSX ...

Page 220: ...t A A60P1 76 L 29 OB3 l ROt A A60P1 21 l 11 DB FROt A ABOPl 77 L 30 DB FROl I A60Pl 22 12 D86 FROM AGOPl 78 1 31 l f31 FRDY ABOPl 23 L 13 DBB FROM A60Pl 79 L 32 Ofi9 FROl I A60P1 2 L 14 DB10 FROt A A60P I 00 33 DAii FRDl l A60Pl 25 L l5 DBl2 FROM ABOPl 01 1 34 DBl3 FROt A A60Pl 26 L 16 DB14 FROt A AS f 1 82 35 DB15 FROt A A60P1 27 lT 3 CDAC FROl I A59P1 0 L 2 I I 69 4 1 LBX TO A57P1 69 ANO A59P J ...

Page 221: ...DELAY COMP GENERATOR DELAY COMP BLOCK E YES YES ANO A59 DIGITAL 18 IS VSWP 19 IS LVSX NO VOLTAGE OK LOW INTERFACE BOARD REMOVE YO TUNE AND FM COIL 7 IS MIN OUT Bl IS 20 30 OUT DRIVE CABLES FREQUENCY AND FREQUENCY AND PLACE 50 n i POWEft OK POWER OK LOAD ON YO TUNE CABLE NO NO MIN LOOP 20130 LOOP 9 IS YO FREQUENCY CHANGE PROPORTIONAL TO YO TUNE NO A55 YO DRIVER BLOCK E NO 10 IS OPEN LOOP YO FREQ l ...

Page 222: ...ngage W3 from where it connects to the YO Loop via a hole in the motherboard refer to Figure 8I 8 View C in the RF Section before lifting out the YO Loop or damage to the instrument will result When replacing the YO Loop assembly be careful not to smash the ribbon connector A50Wl 8 303 8 304 Scans by HB9HCA and HB9FSX ...

Page 223: ...e This signal is buffered on the ASO YO Loop Interconnect board by an open collector darlington inverter The resulting signal LFIL goes to the YO Bias board where it pulls down on the base of Ql through R9 This turns Ql ON and pulls R6 UP to S volts R6 and R7 form a voltage divider going to the gate of an SCR When its gate is pulled positive with respect to its cathode it turns ON and provides a v...

Page 224: ...S A44J2 RF OUT TP2 40V RCllE FACTORY SELECTED TPS 20V MP1 A 2221 45 2 PLACES A44A1J2 TP3 TP5 A44A1R4 YO FM COIL M G FACTORY ADJUSTMENT NOTE Refer to Sweep Generator YO Loop Troubleshooting Block Diagram for schematic of A44 Figure 8D 3 A44Al YIG Oscillator Component Location Diagram Scans by HB9HCA and HB9FSX ...

Page 225: ...Jl This signal is attenuated by AT2 and goes through the A46 7 0 GHz Low Pass Filter to the A48 YO Loop Sampler where it is mixed with the Nth harmonic of the M N Out signal The result is the Sampler IF signal to the A49 YO Loop Phase Detector The RF Signal from the coupler s main line path is the YO Out signal at A45J3 This signal is sent to the Al6 Modulator Splitter 307 Scans by HB9HCA and HB9F...

Page 226: ... Service AT2J2 AT2 15 dB ATTENUATOR CTO A46 VIA W43 AT2JI A45J3 RF OlITPIIT A45JI CTO AISJ2 VIA WSI AND W3 CTO A44 YO J2 VIA W42 Figure 8D 4 A45 Directional Coupler Component Location Diagram Scans by HB9HCA and HB9FSX ...

Page 227: ...46 7 GHz Low Pass Filter is connected by coaxial cables between the A45 Pre leveler and the A48 YO Loop Sampler It is used to filter out the harmonics of the coupled back portion of the YO Output from the Pre leveler to prevent unwanted mixing products in the Sampler 309 Scans by HB9HCA and HB9FSX ...

Page 228: ...ELEA J2 Model 8340A Service NOTE J2 OUTPUT 2 a TO 7 0 GHZ TO W44 ANO A49U1J1 Refer to Sweep Generator YO Loop Troubleshooting Block Diagram for schematic of A46 Figure 8D 5 A46 7 0 GHz Low Pass Filter Component Location Diagram Scans by HB9HCA and HB9FSX ...

Page 229: ...esistor Assembly see schematics for A28 and ASS A47Ql A47Cl and A47R6 are part of the compound PNP transistor in the voltage to current converter Block B of the ASS YO Driver A47R6 being the sense resistor referred to in the ASS circuit description A47Q2 and A47Rl through S are part of the Current Driver Block H of the A28 SYTM Driver These components are located externally so they will be properl...

Page 230: ...8 312 Model 8340A Service A47W2 Q2 A47W1 A47W3 Figure 8D 6 A47 Sense Resistor Assembly Component Location Diagram Scans by HB9HCA and HB9FSX ...

Page 231: ...chematic Diagram and AB2 Mother board Wiring List for signal source and destination information A62J29 TO M7W1P1 PIN 1 0 Pin Mnemonic A47W1P1 Levels 1 RGND PIN 1 av 2 SR FBK PIN 2 5V TD 17V 3 SR PWR PIN 3 5V TD 17V 4 YDXISTB PIN 4 3aV TD 39V 5 YD COIL PIN 5 4aV TD 2aV Note Refer to A55 YD Driver Schematic Diagram and AB2 Motherboard Wiring List for signal source and destination information 8 313 8...

Page 232: ... optimize this impedance match A48Ul Sampler B A48Ul Sampler contains a step recovery diode SRD circuit to create harmonics of the M N signal which are mixed with the low level 15 dBm signal from the A44 Yig Oscillator via the A46 7 GHz LOW Pass Filter LPF When the YO Loop is phase locked the m1x1ng product of the Nth harmonic of the M N signal and the A44 YO signal is precisely equal to the 20 30...

Page 233: ...d to provide from 5 dB to 20 dB of gain This is used to adjust the IF signal to the proper level for comparison to the 20 30 signal in the A49 YO Phase Detector Output Amplifier G The IF signal is further amplified by output amplifier QS and Ql Gain is approximately 21 dB This provides the proper signal level to drive the 49 YO Phase Detector 8 316 Scans by HB9HCA and HB9FSX ...

Page 234: ...F OUT Model 8340A Service A50C1 3 20V A50C1 1 1 ov At BU1 E1 E2 E3 A50C1 5 1 ov A 2202 1 5 Al 9 J2 M N IN Figure BD 7 A48 YO Loop Sampler Component Location Diagram MPG MPS MPI MPS 8 317 8 318 Scans by HB9HCA and HB9FSX ...

Page 235: ...3 a J2 r AT2 15dB ATTENUATOR 2 3 TO 7 0 GHz 10 5 TO 16 0 dBlll WITH ALL POWER SUPPLIES PRESENT I I L I I __ J1 I COUPLER I 2 3 TO 7 0 GHz 10 0 TO 16 0 dBm 1 i 1 ecrI ONAL W42 I J 1 J 3 I W61 W3 AF OUTPUT FROM A44 YIG T t x __ _ M1g 4 OSCILLATOR J2 I J MODULATOR SPLITTER J2 L_____ _J P O Figure 8D 8 A48 YO Loop Sampler Schematic Diagram ALL SERIALS P O 8 319 8 320 Scans by HB9HCA and HB9FSX ...

Page 236: ...fCMHz LPF Figure 8D 8 NOTES SECTION INTROO JCTION F0 1 REFER TO THE SERVl AGRAM SYMSOLOGY NOTES OETAILED SCHEM TIC N OHMS CAPACITANCE 2 R SLSTANCE VALUES N H u N E IN 1icROHENRIES ICROF AR i E A NOTfD G U LESS OlHI O N WIDE 2 6 rn G 3 STRJr L N INIJUCTORS c B 0 1 iN WIDE i LONG L9 o I lN WIDE TH A 5000n P OBE TYPICAL IF LEVEL ACE WITll NORMA 1 RF HRRl ll TO A 5 ou 1PUT LOAD AT BOARDS ARC l l MB NO...

Page 237: ... from the A36 PLLl VCO The resulting error signal tunes the YO to achieve phase lock The YO frequency is related to the M N Output frequency and the 20 30 MHz reference loop frequency in the following manner Fy o N Fm n F20 30 Where F YO YO output fLequency MHz N N number input to the M N Loop harmonic near th frequency to which the YO Loop is tuned Fm n M N Loop output frequency MHz F20 30 20 30 ...

Page 238: ...signal leads the Sampler IF signal a negative pulse appears at U6 pin 12 TP 3 In each case the other output pin remains at an ECL HIGH level approximately 0 6V If the inputs are in phase one of the detector outputs is an ECL HIGH approximately 0 6v with long narrow negative spikes and the other is an ECL HIGH with short spikes The detector outputs are averaged in a 1 5 MHz low pass filter LS L9 Cl...

Page 239: ...e will be a de offset voltage at the INTG output There is normally a small offset at any given frequency due to non linearities in the YO tracking but the value should vary about zero volts If the average value is different from zero it will limit the capture range of the loop The resistor capacitor combinations of R39 Cl7 R40 Cl8 R41 C30 and R42 C31 are used to provide additional filtering of the...

Page 240: ...H the hold mode is enabled The sample and hold re U3 was chosen for its low droop rate which translates directly into improved YO sweep accuracy R52 is used to allow the IC to operate with the large 2 0 uF hold capacitor C24 CR7 and CRB are used to bypass R52 during large signal operation lock acquisition An on chip current booster charging circuit is also activated at this time C35 is a compensat...

Page 241: ...grator U7 The outputs of these two comparators are wire OR1ed together When the input to the Unlock Detector circuit exceeds approximately 6 lV one of the comparators will pull up to 20V which will pulI HULY up to 4 64V where it is clamped by zener diode VR3 This High Unlock HULY signal is routed via the ASO Loop Interconnect board to the A59 Digital Interface board where the processor is able to ...

Page 242: ... Block H LOW sample HIGH hold YO LOOP DISABLE is an ECL logic signal that is used to disable the YO loop when in the hold mode during sweeps It does this by pulling HIGH the second input of IF Limiter USA Block B causing U8B s output to remain LOW This disables the sampler IF input to the Phase Frequency Detector Block D and causes the output of loop integrator U5 to rail to its 6 9V limit This pr...

Page 243: ...nied by the green LED on the ASO YO Loop Interconnect board turning off This condition is indicated by the Unlocked Detector whenever the YO TUNE voltage at A49J2 goes outside the 6 0 v range using a 3 way connector at A49J2 to keep the YO Loop closed measure YO TUNE If it is not outside the 6 0 v range then troubleshoot the Unlocked Detector Block J Limiters To verify the operation of the Limiter...

Page 244: ... Loop Test below Differential Amplifier and Loop Integrators The bias voltages for Q3 will change with loop conditions The three conditions of interest are 1 Loop Locked 2 Sampler IF frequency less than the 20 30 frequency lag YO TUNE 6 0 V and 3 Sampler IF frequency greater than the 20 30 frequency lead YO TUNE 6 0 V The approximate bias voltages for these three conditions are given in Table 80 2...

Page 245: ...ages on A49Q3 Under Different Loop Conditions OJA QJB Emitter Collector Base Emitter Collector pin 4 pin 1 pin 2 pin 3 pin 6 1 5 v 15 0 v 0 9 v 1 5 v 6 7 v 1 5 v 15 0 v 1 8 v 2 1 v 3 7 v 2 l v 15 0 v 0 8 v 1 5 v 9 9 v Bose pin 5 0 9V 0 8 v 1 8 v 8 323a Scans by HB9HCA and HB9FSX ...

Page 246: ...old Block H sample and Bold With HLEY High Lock Enable Yig Oscillator HIGH and LLEY LOW CW or MANUAL mode the output of the Sample and Hold Block H should track the input verify that HLEY is HIGH and LLEY is LOW then measure the input and output of U3 they should be identical FM Coil Driver If the FM Coil Driver Block I is malfunctioning the YO Loop will acquire phase lock but the residual FM on t...

Page 247: ...10 A5DC9 ASOCll 20 30 MH Z VO FM COIL A50C12 HLEY A50C11 20V Al SJ9 20 30 MH Z OUT HULY 10v a 2v IF OUT D U3 J Q MP1 2 PLACE S TP2 TP3 Figure BD 9 A49 YO Loop Phase Detector Component Location Diagram 8 329 8 330 Scans by HB9HCA and HB9FSX ...

Page 248: ...est points serve two purposes Each test point can be used to monitor the state of the digital signal The level will be somewhat less than the actual signal level due to the resistors on each side of the test points The test point can also be used to force a logic condition to occur by tying it to 5V or ground These features are useful for troubleshooting and to verify circuit operation Also provid...

Page 249: ... 39 5 n I I l_j Q_1 e _J A50W2 081 m J YD LOCK ASDWT A 222 1 45 oxa ox1 oxa c ca c cs c ci a OX5 0X4 B I C11 RJ CC12 TP4 TP il X1 TP2 TP1 0 CCt5 TPS TP5 TP4 TP3 TP2 TP1 HULY 10V HLEY HF L 20V llND Figure 8D 10 A50 YO Loop Interconnec Component Location Diagram Scans by HB9HCA and HB9FSX ...

Page 250: ...YD COii 40V PIN 8 40V 9 20V PIN 9 20V 10 10V PIN 10 lOV 11 lOV PIN 11 10V 12 20V PIN 12 2UV 13 YO COIL 40V PIN 13 1UV 14 15 YO COIL PIN 15 40V TO 20V 16 HULY PIN 1B rn IHIGH TAUEI 17 5 2V PIN 17 5 2V 18 19 GND PIN 19 ov 20 5 2V PIN 20 5 2V Note Refer to A50 YD Loop lnwrconnect Schematic Diagram and A62 Motherboard Wiring List for signal source and destination information 8 333 8 334 Scans by HB9HC...

Page 251: ...G2U 100 IO c2 R32 U I HI 1 0 1620 ___ L j f 2 _ T I 1 i a i 620 9o9o T 01 C2 2 J T 1 0 Ci7 R43 1 22pF I O O llROUNn TRAflSFORMATIO IOVI I NOTE R3fj M llJI til I YD F l I I t O NOTE 6 1 121 2 72 Q UNLOCKED DETECTOR 51 IK 20Vf 111 K i 4640 I U2A 20Vf B _ 1 1 I IO F YO TUNE t 2 JO ASS ro ORlVER IVIA A62 J61 YO FM COil 11 3 7 TO A44J I 9 YO BIAS BOARD J2 NOHS I RHFR TD THE SERVICE SECTION IN7RODUCTION...

Page 252: ...ge and have the affect of temporarily tuning the YO 2 5 GHz below the next lock frequency It provides a voltage VCOMP to the A55 YO Driver which is used to compensate for the YO frequency delay A54 YO PRETUNE DELAY COMPENSATION CIRCUIT DESCRIPTION Pretune Register A Ull and Ul3 latch data bits 1 12 from the 16 bit instrument data bus to set the Pretune voltage The strobe that activates the latch i...

Page 253: ...ombines four signals to give the final Pretune voltage These signals are A voltage corresponding to 2 3 GHz R22 24 The DAC voltage which is proportional to lock frequency minus 2 3 GHz Rl9 R20 The sweep ramp R25 R26 The retrace kick pulse R46 The combined signal is called PRETUNE TP3 and has a YO sensitivity of 2 5 V GHz R22 adjusts for the tolerance of R21 R22 R23 the 10 volt reference and the of...

Page 254: ...he sweep mode and the sweep width is 500 kHz Therefore any slight de offset that might be at the output of the sweep generator when it is reset and supposed to be at zero is added to the PRETUNE voltage while the instrument is acquiring phase lock This offset will not effect the sweep accuracy however as long as it is not great enough to keep the YO from acquiring phase lock YO Delay Compensation ...

Page 255: ...pulse by first writing to the pulse width DAC address 5 Rl WYOKW Write YO Kick Width a number that corresponds to the desired pulse width This write loads Ul5 and resets the pulse circuit through U9 At the appropriate time the processor sends a trigger 3 RO TYOKP Trigger YO Kick Pulse which starts the pulse The circuit then terminates the pulse after the programmed length of time has elapsed The w...

Page 256: ... input itself is bits 1 8 rather than 0 7 the number that appears at the input of Ul5 is the number calculated above divided by two Power Supplies H Ll L5 and Cl CS form standard low pass power supply filters The inductor type was chosen to have a relatively high series resistance while the capacitor was chosen to have a low series resistance This results in a Q of about 2 for the filter formed by...

Page 257: ...n the theory section for Pretune DAC Block B In the sweep mode if the PRETUNE voltage does not ramp check to see that VSWP Pl 26 is present Then see that BLVSX TPl is HIGH 15 volts so that the sweep voltage is summed with the start frequency PRETUNE voltage If there is no retrace kick pulse check LKICK to see that it goes LOW 0 5 volts during the period of the kick If LKICK is not working correctl...

Page 258: ...40A Service ua R26 R25 R2B m U s 3 mu if B 2 e I CID I ca2 I R51 I caa I B lca1I I I R37 I U1S C29 I CB J 000000000000000000 1 P1 18 19 36 C3 U16 In t I A54 YO Pretune Delay Compensation Component Location Diagram R32 COFF R30 CGN 8 343 Scans by HB9HCA and HB9FSX ...

Page 259: ...WEEP XA58P1 97 C F 9 LVSX TTL LOW TRUE XA58P1 68 E 27 VCOMP 26 MHZ VOLT F XA55P1 9 1a 081 TTL XA6aP1 76 A G 28 WCOAC TTL LOW TRUE XA59P1 3a F 11 083 TTL XA6aP1 77 A G 29 082 TTL XA6aP1 21 A G 12 085 TTL XA6aP1 78 A G 3a 084 TTL XA6aP1 22 A G 13 087 TTL XA6aP1 79 A G 31 086 TTL XA6aP1 23 A G 14 089 TTL A F 32 DBS TTL A F G 15 0811 TTL A F 33 0810 TTL A F 16 0813 TTL XA6aP1 82 F 34 0812 TTL A F 17 0...

Page 260: ...l 8 B OB I I 5 I 8 DBl2 6 I 16 I DBl3 7 I 32 _ H DBl4 8 I 04 Pl Z8 H J 0815 9 I 12B l_ O I OATA t IS j l J 7o 32 Pll U14S 60 54 0 RH g D 128 MSB _ _ 1 r l W ___ Ir _ I 11c _ J ronsEn Fal 1 21 VREF cvoun l l _ 1o c o 2 F R l_ 14 I r c o1 1p1 COUP 2 0 68 IK wco c r I 0 CGN ROI NC J VRff OAOO RfBI _IJ _ NC U I A P1 2s_ H I n_ 0 ____ c 9K 21 J H EF RFJ J 15 C Cj l VREF lOUT 1F VSWP 21 6K 23 H NC _l_ I...

Page 261: ...ency The negative feedback for the Discrete OP Amp is taken from the sense resistor A47R6 therefore the voltage present at the inverting input of the Discrete OP Amp will also be present at the sense resistor Since the other end of the sense resistor is connected to ground this voltage defines the current through the sense resistor and thus through the YO coil The voltage at the non inverting inpu...

Page 262: ... SYTM also uses that voltage and has its own independent offset A55 YO DRIVER ASSEMBLY CIRCUIT DESCRIPTION Discrete Op Amp A The Discrete OP Amp is arranged in a standard configuration Q3 provides the differential input with TP4 the input and TP5 the input The Q2 circuitry forms a current source for biasing the input stage Cl is for noise filtering CR2 and CR3 provide temperature stablization CRl ...

Page 263: ...esired C4 C25 and R23 stablize the Compound PNP Transistor Oscillation of this stage is aggravated by the inductance of the leads connecting the on board and off board components R24 provides for a slight bias current through Ql2 and defines the impedance seen by the base of A47Ql C26 bypasses the base emitter junction of QlO and improves the radiated susceptibility performance of the instrument V...

Page 264: ... resistors were used rather than series inductors to provide a wide band low Q impedance for the shunt capacitors to work against A55 YO DRIVER ASSEMBLY ADJUSTMENTS Before the YO Driver adjustments are made the A54 YO Pretune Delay Compensation assembly must first be adjusted Once this is done carry out the following procedure NOTE GAIN Adjust R4 and OFFSET Adjust R47 are interactive With the foll...

Page 265: ... the YO frequency an accuracy of 1 MHz is sufficient As a final check reconnect cable A49Wl between A49J5 and A49J6 and measure YO TUNE A55TP3 in the CW mode over the frequency range of 2 30 to 6 99 GHz The de value should vary about 0 volts The PRETUNE should set the YO within about 5 MHz of the desired frequency The sensitivity of YO TUNE is about 3 MHz volt Therefore YO TUNE should be 2 volts 8...

Page 266: ... TUNE I KHz OFFSET PRETUNE GAIN ADJUST SUMMING AMP 2 TP2 IN I KHz 1 DISCRETE OP AMP A47 I L 40V CURRENT SUMMING NODE COMPLIMENTARY DARLINGTON PNP TRANSISTOR YO COIL Figure BD 14 A55 YO Driver Simplified Diagram YO SENSE RESISTOR Scans by HB9HCA and HB9FSX ...

Page 267: ...TPt TP2 RGND SUM Model 8340A Service MP2 TP3 R47 TP4 TP5 MPt YO TUNE OFFSET SENSE IN R4 GAIN MP3 6 PLACES Figure 8D 15 A55 YO Driver Component Location Diagram 8 353 Scans by HB9HCA and HB9FSX ...

Page 268: ...HZ XA54P1 24 A 23 PRETUNE 25V GHZ OV 2 3 GHZ XA54P1 24 A 9 VCOMP 26 MHZ VOLT XA54P1 27 F 24 YD TUNE ov 6 v E A62J6 SMC CENTER 10 RGND ov STAR GND POINT H 25 RGND ov STAR GND POINT H 11 RGND ov STAR GND POINT H 26 RGND ov STAR GND POINT H 12 SR FBK 5V TO 17V A A62J29 2 27 SR FBK 5V TO 17V A A62J29 2 13 SR PWR 5V TO 17V B A62J29 3 28 SR PWR 5V TO 17V B A62J29 3 14 HCEN TTL HIGH TRUE XA59P1 67 XA55P1...

Page 269: ...Scans by HB9HCA and HB9FSX ...

Page 270: ...o the stop frequency Thus the PRETUNE voltage always corresponds to the YO frequency This type of sweep scheme is called lock and roll When the sweep is contained in two or more multiply bands the 8340A re phase locks the YO and VSWP resets to zero at each bandcrossing Thus in the multi band case VSWP provides the voltage to sweep the YO from the last phase lock frequency start frequency or last b...

Page 271: ...lated to the Sweep Out but since there is other circuitry between the Ramp Generator Block K and Sweep Out the Ramp Generator output is called Marker Ramp On the A58 Sweep Generator board the Marker Ramp is fed through the summing Amplifier Block L and sweep Width DAC Block M to give the 20 30 SWP ramp that sweeps the 20 30 Loop for narrow instrument sweeps YO sweep width less than 5 MHz This volt...

Page 272: ... say the sweep time of the instrument is the time during which the instrument is actually sweeping and does not include the re phase lock time at each bandcrossing Figure 8D 18 shows a typical Marker Ramp in the single and multi band cases 8 359 Scans by HB9HCA and HB9FSX ...

Page 273: ... I I I I I I I I I I I I I I I 1VSWP I I I HET FUNDAMENTAL BAND BAND t I t I A3 I 11 S3 u 1 11 84 I I I I I I I I I I I I IJ I S4 I I I A4 I I I I 83 I A3 I I I I I I I I I I I I I I I I I I I I I 1 l 4 3 I 2nd 3rd 4th HARMONIC HARMONIC HARMONIC ov I I I 10V ov ov Figure 8D 17 Marker Ramp and VSWP Waveforms S SLOPE U A2 A3 A4 A6 10V Scans by HB9HCA and HB9FSX ...

Page 274: ...This is a current output DAC It is referenced to the 7V Voltage Reference Block D and its output goes to the Summing Amplifier Block L Rl Rl9 and R20 set the gain of the DAC Cl9 provides DAC compensation This block can be checked out by setting the instrument to any single band sweep and stopping it at the end of the sweep by using the SHIFT XTAL function This will stop the Marker Ramp at 10 volts...

Page 275: ...ce MARKER RAMP SINGLE BAND CASE 10 VOLTS 0 1 4 Instrument Sweep Time MARKER RAMP MULTI BAND CASE IO VOLTS 0 f T2 i f T3 I Tl T2 T3 T4 Instrument Sweep Time Figure 8D J8 Typical Marker Ramp Waveforms Scans by HB9HCA and HB9FSX ...

Page 276: ...the switches in the SWP Width Range Attenuator Block N for every value of VSWP sweep Time DAC G U2 and Ul take the digital input from the Sweep Time Register Block A and convert it to the appropriate voltage R39 provides a fixed trim for the gain of U2 C22 is for op amp stablization The voltage at TPl should be 10 volts when all the input bits to U2 are HIGH This will occur whenever the selected s...

Page 277: ...rtual Ground test point VGNO TP3 It does this by varying the voltage at the gate of Q5 This varies the resistance of that FET and therefore varies the voltage drop across it The voltage across C30 Ramp Generator Block K is always negative and the conventional current flow is always into the source and out of the drain of Q5 CR2 and CR3 are low leakage diodes used for current steering Ramp Generato...

Page 278: ...odel 8340A Service Q VIRTUAL GROUND AMPLIFIER CR2 CURRENT 52 SHUNT U35B 15V RESET AMPLIFIER 1 CE RAMP GENERATOR R4 6 SI Q6 MKR RMP Figure 8D 19 Simplified Ramp Generator 8 365 Scans by HB9HCA and HB9FSX ...

Page 279: ... directed into C30 This constant current into a constant capacitance gives rise to a voltage across C30 that increases linearly The output of the Ramp Generator Block K MKR RMP will increase linea iy from O to 10 volts where the sweep will be stopped At this point the voltage across C30 will have increased become less negative to a value that is dependent upon the gain from C30 to the output of U9...

Page 280: ...particular lock point the instrument processor knows what value the Marker Ramp voltage should be The processor then programs the Reset DAC Block C to sink a current that is subtracted from the current generated by Marker Ramp RS and R9 This drives the output of U6 toward zero Since the Reset DAC has finite resolution it is also necessary to provide analog circuitry to bring the output of U6 to ex...

Page 281: ...ensation capacitor To check out this DAC use the SHIFT XTAL function in a single band sweep to stop the sweep with Marker Ramp at 10 volts The voltage at TP2 RST RMP in summing Amplifier Block L should also be at 10 volts Now the sweep Width DAC can be programmed directly and the output voltage at TP8 20 30 SWP in Sweep Width DAC Block M observed A digital input of zero should give zero volts out ...

Page 282: ...is 4 GHz but the YO sweep width is 1 GHz This is because the fourth harmonic of the YO is being used For YO sweep widths less than 500 kHz in MANUAL or CW modes VSWP is turned off This is done by turning on Qll which grounds the input of the buffer Ul7 This keeps any noise from the Sweep Generator from getting to the Pretune DAC and degrading the phase noise performance sweep Buffer o Ul8 simply i...

Page 283: ...es HIGH turning off the front panel sweep LED At the appropriate time the instrument processor asserts LRSP Low Reset sweep TPll which causes LRESET Low Reset TP13 to go LOW This allows Reset Amplifier 1 Block R to pull the output of U9 to ground LRESET going LOW causes LHLD to go HIGH turning off the Current Shunt During the re phase lock sequence the instrument processor releases LBX and LRSP Th...

Page 284: ...W ENABLE RESET AMP2 LRSP LRESET LHLD LSPLD Model 8340A Service END OF SWEEP SEQUENCE END OF SWEEP START OF SWEEP ___J START OF SWEEP I I CD BANDCROSS SEQUENCE Figure 8D 20 Sweep Control Logic Timing Diagram Scans by HB9HCA and HB9FSX ...

Page 285: ...ts U33A pin 3 U33D pin 11 will be the opposite TTL level That is if one is HIGH the other will be LOW and vice v rsa It would seem that U32D which is used as an inverter could be eliminated by connecting U33A pin 3 to U32D pin 2 However when the instrument is in the CW or MANAL mode LBX and HSP are HIGH while LRSP is LOW This causes both outputs of the flip flop to be HIGH Hence the need for U32D ...

Page 286: ...f Ul3 is LOW Ul3 is in the sample mode This closes the loop and forces the output of U6 pin 6 in the Summing Amplifier Block L to be at ground When pin 14 of Ul3 goes HIGH Ul3 goes into the hold mode and the loop is opened As the sweep progresses and the output of U6 ramps up the output of Ul3 will not change There is a guard trace around the node containing the sample and hold capacitor and Ul3 p...

Page 287: ...low pass configuration The particular L and C components were chosen to have a low Q self resonance R48 provides a reference ground for the board in the event that the connection between reference ground and chassis ground on the instrument is broken Ql4 and tBe associated components create a 15V supply referenced to RGND This supply is used to provide symetrical 15V supplies R49 and R50 divide th...

Page 288: ... 9 77 volts If you now press SINGLE SWEEP and then vary the sweep time from 10 to 99 msec the voltage at this test point should go from 9 77 to 0 977 volts varations from these voltages by several tenths of a volt will affect the sweep time accuracy but not the board s ability to sweep Return to the continuous sweep mode with a sweep time of 10 msec Look at the VGND test point TP3 It should be at ...

Page 289: ...O write a O to channel 1 sub channel O by pressing this key sequence SHIFT GHz 1 Hz SHIFT MHz 0 Hz SHIFT KHz O Hz Check the digital input to Ull pins 4 15 they should all be LOW TPB should be at ground Now write a 4095 to the same strobe using the following key sequence 4 O 9 5 Hz This should make all the digital inputs to Ull HIGH The voltage at TPB should now be the opposite of the voltage at TP...

Page 290: ...g at TP2 write 1023 to Reset DAC US as follows SHIFT GHz 1 Hz SHIFT MHz 2 Hz SHIFT KHz 1 O 2 3 Hz This should cause the voltage at TP2 to go to zero By turning the RPG slowly and decreasing the number from 1023 to 0 the voltage at TP2 should decrease smoothly from zero to 10 volts With zero written to US all the digital inputs to US should be LOW With 1023 written all inputs should be HIGH 8 376 S...

Page 291: ... MP7 C R2 a MP10 2 PL C i MPll 2 PL C i bAc HlG LD OETAIL SEE DETAii A MP9 TPS I TP I Tl IO I TPI I TP 2 TPl a Figure 8D 21 A58 Sweep Generator Component Location Diagram 8 377 8 378 Scans by HB9HCA and HB9FSX ...

Page 292: ... NOT USED 70 GND PLANE ov INSTRUMENT GROUND V 16 SIOB TIL LOW TRUE XA60P1 16 NOT USED 71 GND PLANE ov INSTRUMENT GROUND V 17 ADRO m XA60P1 17 NOT USED 72 HFILYD TIL HIGH TRUE XA59P1 72 NOT USED 18 ADR2 m XA60P1 18 NOT USED 73 ADR1 m XA60P1 73 NOT USED 19 ADR4 m XA60P1 19 NOT USED 74 ADR3 m XA60P1 74 NOT USED A single letter in the source or destination column refers to a function block on this ass...

Page 293: ... 83 0815 m XA60P1 83 NOT USED 29 WRDAC TIL LOW TRUE XA59P1 29 8 s 84 WSPAT TIL LOW TRUE XA59P1 84 E 30 TYO KP TIL LOW TRUE XA59P1 100 NOT USED 85 LRSP TIL LOW TRUE XA59P1 85 p 31 86 32 87 33 88 34 GND PLANE ov INSTRUMENT GROUND V 89 GND PLANE ov INSTRUMENT GROUND V 35 20V 20V XA52P1 16 40 V 90 20V 20V XA52P1 16 40 V 36 5 2V 5 2V XA52P1 17 18 41 42 V 91 12V 12V XA52P1 9 33 NOT USED 37 5 2V 5 2V XA5...

Page 294: ... INSTRUMENT GROUND V 45 GND PLANE ov INSTRUMENT GROUND V 100 LCHNG TIL LOW TRUE NOT USED 46 GND PLANE ov INSTRUMENT GROUND V 101 GND PLANE ov INSTRUMENT GROUND V 47 HFILYO TIL HIGH TRUE XA59P1 72 NOT USED 102 48 103 49 104 50 105 51 106 52 107 53 108 HXREF TIL HIGH TRUE A62J31 17 NOT USED 54 LSRQ TIL LOW TRUE NOT USED 109 55 GND PLANE ov INSTRUMENT GROUND V 110 GND PLANE ov INSTRUMENT GROUND V A s...

Page 295: ...IK R52 TPIO ISllP 1 2V 1Hhl 0 5 p ll 10 200 SEC STD3t _rf 1 w I C22 H5VA I 1aoo s o B100 Pi 35 9 20V POWER SUPPLIES LI OD tc 0 1 A 511 RBO 1 BK l6 7R V E a 0 1 L2 R A 4 i3 3K 20Vf t 1 4VF A50 1000 Q14 D t5VR 5 ii K C 10D t 0 6 8 1 C O Q _______ 5VR A 37 92 svr I lcso 0 r j 9 94 10 C Ol 1rC B 0 10VF t B B O i R R ts a 1 1 HiVF B B Q 0 1 fPS R R RSND P1 42 43 lA AGND I j5 4 g9 __ _ 2L5 99 mm D R 1 0...

Page 296: ...Scans by HB9HCA and HB9FSX ...

Page 297: ...N Output Reference MIN Motherboard RecHfiei PLL1 VCO Voltage Controlled Osc PLL1 Divider PLL1 IF PLL3 Upconverter PLL2 VGO Voltage Controlled Osc PLL2 Phase Detector PLL2 Divider PLL2 Discriminator YIG Oscillator YO Directional Coupler 7 GHzLow Pass Filter 28 27 26 25 24 12 13 14 15 15 5 4 36 37 38 39 40 41 42 _43 18 18 18 A47 Sense ResistorAssembly YO circuit 47 SYTM circuit 47 VO Loop Sampler A4...

Page 298: ...MOTHERBOARD WIRING LIST E INTRODUCTION List of Assemblies Covered A62 MOTHERBOARD DESCRIPTION A62 MOTHERBOARD TROUBLESHOOTING REPAIR PROCEDURES MOTHERBOARD WIRING LIST Scans by HB9HCA and HB9FSX ...

Page 299: ...ar to be routed to the A62 Motherboard but are not actually discussed in detail in this section Some of these items include the A47 Sense Resistor Assembly the A51 Reference Oscillator Assembly various mechanical parts and certain casting assemblies Refer to the following to determine which assemblies are covered and which are not covered in this section Reference Guide to Service Documentation lo...

Page 300: ...ployed on the A62 Motherboard STAR GND STAR GND is the single ground reference point for analog circuitry in all major assemblies Each assembly block is referenced to STAR GND via individual traces this minimizes ground noise crosstalk between major assemblies STAR GND is a screw terminal located between the A62XA57 Marker Bandcross and A62J3 connectors and is visible with the instrument top cover...

Page 301: ...8 390 ANALOG SIGNALS 111111 DIGITAL GROUND PLANE DIGITAL SIGNALS DIGITAL SIGNALS DIGITAL GROUND PLANE ANALOG SIGNALS Figure 8E 1 A62 Motherboard Cross Section Scans by HB9HCA and HB9FSX ...

Page 302: ...R GND and is used as a low current reference for integrated circuits cable shields etc where a very clean reference is desired MISCELLANEOUS GROUND PLANES A The ground plane under the 20 30 Loops aluminum casting completes a radio frequency interference RFI box comprised of the casting assembly covers and the 20 30 loops ground plane This ground plane is connected to STAR GND via a GND trace and t...

Page 303: ... 8E 2 A62 Motherboard Component Location Diagram to determine the signal source and its location Ensure that the signal source circuitry is functioning properly and if so isolate the source by removing destination assemblies where possible In most cases the trouble will occur on other assemblies rather than on the Motherboard itself Visually inspect the Motherboard for possible loose hardware stra...

Page 304: ...dures of those assemblies for specific removal instructions To remove a component heat one side of the component pad from either side of the board and carefully lift that lead out of the hole Repeat the procedure with the remaining lead and after the component has been removed reheat each pad and use solder wick or an anti static solder removing tool vacuum type to remove the solder from each hole...

Page 305: ...nector contacts then reheat each pad and remove the old solder Insert the new connector and hold it straight and flush against the Motherboard while another person solders all connector pins Single and dual in line connectors having the prefix J with the exception of J31 may be successfully removed by heating each connector pin and using a solder removing tool to remove the old solder If necessary...

Page 306: ...board replacement should be directed to your nearest HP Sales and service Center for more specific instructions Refer to the HP Sales And Service Offices listing at the end of the Service section in this manual 8 397 8 398 Scans by HB9HCA and HB9FSX ...

Page 307: ... XA43 Model 8340A Service A62 MOTHERBOARD COMPONENT SIDE PC TRACES XA34P2 x MP4 J2 PC TRACES XA34PI MP5 MPIO MP8 J3 MP9 XA57 XA58 XA59 XA60 XA61 MP7 MOUNT FAR SIDE 2 PLACES G Figure 8E 2 A62 Motherboard Component Location Diagram I of2 8 399 Scans by HB9HCA and HB9FSX ...

Page 308: ...P2 HEAT SINK O UI i 0 o o 0 Q3 10 J 04 i l o SI J4 J5 J6 Qtl J Model 8340A Service A62 MOTHERBOARD SOLDER SIDE STAR GND Jll Jl3 Jl5 Jl4 Jl6 JIO J25 J26 ru s Figure 8E 2 A62Motherboard Component Location Diagram 2of2 MPll 9 PLACES LI 9 Scans by HB9HCA and HB9FSX ...

Page 309: ...rvice A62 MOTHERBOARD SOLDER SIDE STAR GND Jll Jl3 Jl5 0 Ja J9 Gl J27 LJ Jl4 Jl6 JIO J25 J26 0 i L5 Figure 8E 2 A62 Motherboard Component Location Diagram f2 of2 MPll 9 PLACES LI g REPLACEMENT PAGE SERIAL PREFIX 2519A 8 400a 8 400b 1 5 1 6 Scans by HB9HCA and HB9FSX ...

Page 310: ... XA25P1 32 DET S H t DETECTOR SAMPLE HOLD CONTROL DIGITAL 4 5V t 3 5V XA21P1 3 DET S H DETECTOR SAMPLE HOLD CONTROL DIGITAL J 5V 4 5V XA21P1 21 DIV N2 500 KHZ DIVIDED OUTPUT FROM PLL2 DIVIDER DIGITAL TIL ILOW TRUE XA42P1 27 19 27 DI01 IEEE 488 1 0 DATA BUS BIT 1 DIGITAL TIL XA60P1 57 0102 IEEE 488 1 0 DATA BUS BIT 2 DIGITAL TIL XA60P1 68 DI03 IEEE 488 l O DATA BUS BIT 3 DIGITAL TIL XA60P1 59 DI04 ...

Page 311: ... 43 XA57P1 99 A62 STAR GND CONNECTED TO REAR PANEL INSTRUMENT GROUND XA21P1 1 XA59P1 67 XA28P1 18 XA59P1 72 XA26P1 42 XA21Pl 36 XA26P1 33 XA27P1 46 XA27P1 16 XA27P1 47 XA59P1 51 XA59P1 53 XA57P1 2 12 XA26P1 13 XA53P1 17 XA56P1 1 16 A62J3 3 XA26P1 2 SEE AB1 CKT DESCRIPTION XA52P1 46 XA57P1 105 XA57P1 13 XA59P1 66 XA60P1 45 A62J19 16 XA34P1 8 XA34P2 14 A62J2 16 XA37P1 2 1 XA39P1 1 16 XA41P1 4 A62J31...

Page 312: ...L DIGITAL OV TO 22V A62J1 20 LSOB STAY OFF BUSS SIGNAL DIGITAL TTL LOW TRUE XA60P1 46 LSPLD SWEEP L E D CONTROL OFF ON DIGITAL TTL XA58P1 67 67 LSSP STEP SWEEP DIG OPEN COLL TTL LOW TRUE XA57P1 107 LSRQ SERVICE REOUEST DIG OPEN COLL TTL LOW TRUE NOTE 9 54 LSTEPUP STEP UP FOR E XTERNAL FOOT SWITCH DIGITAL TTL LOW TRUE A62J31 14 LSTP PROCESSOR STOPPED DIGITAL TTL LOW TRUE XA59P1 65 LUNLVL INSTRUMENT...

Page 313: ...A62J26 CENTER PLS IN RTN EXTERNAL PULSE GROUND RETURN GROUND ov NOTE 10 PMOD RTN PU u LiRvu _ ov XA21P1 35 PRETUNE YO PRETUNE ANALOG 2 5V GC 0 2GC XA54P1 24 24 8 23 PWR ON LEO s VAC 2 THROUGH CR1 ANO R1 TO OSI POWER SUPPLY 78V ANODE ON A62R1 018 TRANSISTOR 01 BASE ANALOG XA53 4 01E TRANSISTOR 01 EMITTER ANALOG XA53 7 8 26 26 02B TRANSISTOR 02 BASE ANALOG XA53P1 21 02E TRANSISTOR 02 EMITTER ANALOG ...

Page 314: ...W TRUE XA59P1 99 WYTMCTL YTM CONTROL SIGNALS STROBE 11 R1 DIGITAL TTL LOW TRUE XA27P1 14 WYTMSLP YTM DRIVE SLOPE OAC DATA STROBE 11 R1 DIGITAL TTL LOW TRUE XA27P1 44 W11R2 EXTRA 1 0 STROBE 11 R2 DIGITAL TTL LOW TRUE XA27P1 15 YO COIL POSITIVE INPUT TO YO COIL ANALOG 40V TO 20V XA55P1 15 30 YO COIL NEGATIVE INPUT TO YO COIL POWER SUPPLY 40V A62J2 8 13 YO TUNE LOW FREQ PHASE LOCK TO YO DRIVER ANALOG...

Page 315: ...LE CONNECTOR TO XA23 XA23P1 36 A62J12 SHIELD EXTRA SHIELDED CABLE CONNECTOR TO XA23 XA23P1 35 A62J17 CENTER EXTRA SHIELDED CABLE CONNECTOR TO XA23 XA23P1 18 A62J17 SHIELD EXTRA SHIELDED CABLE CONNECTOR TO XA23 XA23P1 17 A62J21 CENTER EXTRA SHIELDED CABLE CONNECTOR TO XA22 XA22P1 11 A62J21 SHIELD EXTRA SHIELDED CABLE CONNECTOR TO XA22 XA22P1 29 A62J22 CENTER EXTRA SHIELDED CABLE CONNECTOR TO XA22 X...

Page 316: ...ted to this pin from A62J5 through W48 to A62Jll 7 Vswp is routed to this pin from A62J27 through W47 to A62J4 8 Reserved for future expansion 9 Open collector bus multiple sources 10 Multiple sources 11 The mnemonics in this table exist on the A62 Motherboard assembly Other mnemon ics contained only within other assemblies such as the YO Loop MIN Loop and Front Panel assemblies are not shown to l...

Page 317: ...7 A38 PLL1 IF 38 I Top View A39 PLL Upcqnverter 39 A40 Mvqo Voltage qontrolled osi 40 Ml PLL2Phase Detector 41 A42 ji L2Divider 42 A 43 M Qlsl niiiinator 43 A44 VIG Oscillator YO 18 A45 DirectionalCoupler 18 A46 7 GHz Low Pass Fiiter 18 _____ A47 Sense Resistor Assembly YO circuit 47 Ms YO LliopSainplei SYTM circuit 17 18 A49 YO loopPha eJoetector 1t A50 YOLoopJnterco nnect 17 A51 Refeoioce Oscill...

Page 318: ... 00 nEMOTE SRO FAULT ov EXTR F UNL CJr 0 M C I J1 J2 J3 J4 RP1 J5 RF OUTPUT J9 S2 FL1 J15 Line Module J10 J16 REAR PANEL J11 J18 J17 Fan Assembly Figure BF 1 Front and Rear Panels J19 J20 Option 004 and 005 only J21 HP IB Connector 8 415 Scans by HB9HCA and HB9FSX ...

Page 319: ...8 416 A1 ALPHA DISPLAY A LOWER KEYBOARD Model 8340A Service A2 DISPLAY DRIVER RPG Figure 8F 2 Front Panel Assemblies A3 DISPLAY PROCESSOR A6 KEYBOARD INTERFACE Scans by HB9HCA and HB9FSX ...

Page 320: ...Scans by HB9HCA and HB9FSX ...

Page 321: ...Scans by HB9HCA and HB9FSX ...

Page 322: ...Scans by HB9HCA and HB9FSX ...

Page 323: ...Scans by HB9HCA and HB9FSX ...

Page 324: ...Scans by HB9HCA and HB9FSX ...

Page 325: ...Scans by HB9HCA and HB9FSX ...

Page 326: ...Scans by HB9HCA and HB9FSX ...

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