HP 8340A, Service Manual

Page: 147 / 326

Model 8340A - Service
in synch with the output pulse (TP13). The low-to-high transition
of TP7 will clock Ul5B and leave it in the RESET state. Ul5B pin
15, LOW SWALLOW ENABLE is connected to the reset of Ul4B. As long
as LOW SWALLOW ENABLE is HIGH, HSWALLOW will be forced LOW
independently of its clock changing. But if the rate multipliers
Ul and U2 cause a pulse on TP7, LOW SWALLOW ENABLE will be left
LOW, and HSWALLOW will be allowed to go HIGH when the next output
pulse (TP13) occurs.
The only time that states can potentially change in the swallow
Control is when there is an output pulse. The swallow Control
must decide to do one of two things for the subsequent output
pulse (TP13); either divid� by N or N+l. To divide by N+l, the
HSWALLOW line is clocked HIGH for only one input clock pulse. To
divide by N, the Divide-By-N block is left uninterrupted. The
decision to swallow an input pulse is made by considering two
things; whether the rate multipliers Ul and U2 outpu.t a pulse,
and the state of LOW SWALLOW ENABLE prior to the output pulse
(TP13). All four possible combinations are diagrammed in Figure
8C-14.
The things to notice in Figure 8C-14 are:
�
Whenever LOW SWALLOW ENABLE was HIGH prior to the output pulse
(TP13), HSWALLOW always remained LOW throughout the sequence,
and no input pulse was swallowed.
�
Whenever the rate multipliers Ul and U2 did output a pulse,
LOW SWALLOW ENABLE was left in the LOW state, regardless of
the previous state of the line.
The definition of these lines can then be stated:
�
LOW SWALLOW ENABLE - When LOW, an input pulse will be
swallowed during the next output pulse (TP13) sequence.
�
HSWALLOW - When HIGH, causes Ul2 to hold its count. This will
only be HIGH for a period of 1 input clock pulse, and will be
timed such that the counter is never loading and holdi�g at
the same time.
RlO and Cll are important for the proper operation of State # 2
as shown in Figure 8C-14. Since the rate multipliers Ul and U2
did NOT output a pulse in this state, the LOW SWALLOW ENABLE line
must be left in the HIGH state after the sequence is over to
prevent a pulse from being swallowed next time. There would be a
potential race condition occurring at the inputs to Ul5B if it
were not for RlO and Cll. Ul4A pin 2 HSWALLOW is going LOW, and
is also clocking Ul5B through U3A NOR gate. Ul5B pin 10 is also
changing and an illegal setup violation would occur. Instead, RlO
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Scans by HB9HCA and HB9FSX