HP 8340A, Service Manual

Page: 160 / 326

Model 8340A - Service
The SET inputs to both flip-flops are tied together and are
driven by the output of the NOR gate U6A. Whenever the non­
inverted outputs of the flip-flops are both low the SET lines on
both flip-flops are asserted and the non-inverted outputs of the
flip-flops will both go high.
As can be seen in Figure 8C-20, when one of the clock inputs goes
high, the corresponding non-inverting output will go low and
remain low until the other clock input goes high which sends the
other non-inverting input low. Once both non-inverting outputs
are low, the SET inputs will be asserted as previously described
and both non-inverting outputs will go high until the next clock
pulse is received.
When the inputs are out of phase the non-inverting outputs will
differ. The non-inverting output with the longer negative going
pulse corresponds to the input that is leading in phase. When the
inputs are locked together the non-inverting outputs will both be
high with low narrow pulses coincident with the input rising
edge. The width of the narrow pulses correspond to the
propogation delays of the NOR gate (U6A) and the flip-flops.
LOOP AMPLIFIER F
The phase detector differential outputs are the inputs to the
LOOP AMPLIFIER. Each of the differential inputs is passed through
identical low-pass filters (RS, R9, C2, R6, RlO, and C3). C9,
Rl6, C8, and Rl7 provide a large de gain for the loop amplifier
while insuring that each of the differential inputs see the same
impedance over all frequencies. Rl4, Rl5 and C7 form an ac
voltage divider which sets the loop bandwidth to about 10 KHz and
limits the amount of noise introduced by U2.
The output of the divider goes to the varactor diode (CR3 in
Block
D)
and tunes the vco.
Rl8, CR4 and CRS reduce the charging time of C7 whenever the
frequency is abruptly changed.
•
If the vco is tuned to a frequency that is lower than the 160 MHz
reference frequency (Block A) , the mixer output frequency still
is equal to the difference of the two input frequencies but the
loop will provide positive feedback instead of negative feedback
and will drive the .VCO to the low end of its frequency range. UlB
prevents the vco tune voltage from latching at a positive value
by sensing when the voltage goes above 0 volts. When this occurs,
the output of UlB pulls the tune voltage down to the proper lock
range. Rl3 provides hysteresis to allow time for the loop to
lock. CR2 prevents the output of UlB from interfering with the
VCO when it is tuned to the correct side of 160 MHz.
8-219
Scans by HB9HCA and HB9FSX