HP 8340A, Service Manual

Page: 137 / 326

Model 8340A - Service
The output of the differential integrator is fed through a
programmable ac voltage divider formed by R31, R32, R33, R34, R35
with R36 and C36. Following this is a 40kHz low pass filter which
has two notches that are tuned to reject 50kHz generated by the
fractional division used in PLLl divider.
VRl and R37 conduct when large currents are required to charge
C22. During locked conditions, VRl should always be off.
Since there are upper AND lower sidebands generated by the PLLl
IF mixer, it is possible that the VCO could be disturbed by the
presence of both sidebands. While it is impossible for the loop
to actually lock onto the wrong sideband, due to the inversion in
loop gain, the
vco
would be tuned to an endpoint. The out of
range corrector prevents this from happening by monitoring the de
tune voltage and forcing the
vco
in the opposite direction should
it attempt to exceed its normal range. U6B compares the de tune
·
voltage across C36 to +17.SV. If the tune voltage exceeds this,
U6B output goes LOW, turning on CRS, and pulling the
non-inverting input to the differential integrator LOW. This
forces the
vco
tune voltage to decrease until it reaches about
+5V, at which point the hysteresis around U6B (due to R24) causes
U6B to return to its inactive HIGH state.
A mode exists where the
vco
may be OFF, and when programmed ON
will remain disabled due to noise driving the phase detector and
loop amplifier such that the
vco
is continually driven to its OFF
state. To ensure that the
vco
will always oscillate, the
vco
range limiter clamps the lower end of the tune voltage to about
+3V. This should always be lower than the minimum tuned voltage
in normal operation, so Q2 should never be·on when phase-locked.
Q2 functions as a clamp due to its base being biased at about
+4.4V by RlO and R7. If the tune voltage drops to a low enough
voltage, Q2 and CR7 will conduct, and clamp the tune line to two
diode drops below +4.4V (+3V).
·
GAIN SWITCH B
US latches the four most significant bits of the programming of
PLLl divider (N=3 to 13). These are level translated by U4 which
drives four FET switches. By activating combinations of FET's, a
programmable resistance is placed in parallel with R31, changing
the amount of attenuation. As the digital divider changes
numbers, the loop gain directly follows it. By increasing the
amount of gain in the loop amplifier, switching the FETs in or
out, a constant loop bandwidth of 5 kHz is approximated. A table
of the states of the FET's is shown in Table 8C-3.
8-186
Scans by HB9HCA and HB9FSX