HP 8340A, Service Manual

Page: 130 / 326

Model 8340A - Service
PLLl OVERALL DESCRIPTION
INTRODUCTION
PLLl (Phase Locked Loop 1) is part of the 20-30 Loop Synthesizer.
It consists of the following assemblies:
mi
A36 PLL 1 VCO
�
A37 PLLl DIVIDER
181
A38 PLLl IF
DESCRIPTION
The PLLl and PLL3 phase-lock loops are only used when in CW Mode
or in swept frequency modes with YO sweep widths less than 100
kHz.
PLLl functions as a programmable frequency translator. The input
to the translator is the PLL3 output (160.15 to 166 MHz}. The
PLLl VCO frequency is offset by a programmable amount from the
PLL3 output. As the PLL3 output changes frequency (ie. as it
tracks a sweeping PLL2) the offset frequency between the PLL3
output and the PLLl VCO output will remain constant. The offset
frequency, PLLl IF output, is determined by the value of
programmable divider
Nl and is constant throughout the sweep. The
result is that the precision sweeps and high resolution of the
PLL2 Loop are effectively tra ' nsf e rred up in frequency to the PLLl
vco.
A simplified diagram of the PLLl Loop is shown in Figure.SC-6.
The phase/frequency detector for PLLl, which resides on the A37
PLLl DIVIDER assembly, operates at 5 MHz. One of the phase
detector inputs comes from a 10 MHz (A29 Reference Phase
Detector) reference which is divided by two on the A37 assembly.
The second phase detector input is the PLLl IF output, after
passing through a divide-by-two and a fractional divider. The
fractional divider uses pulse-swallowing techniques to divide by
numbers between 3.60 and 13.97.
When the loop is locked, both phase detector inputs will be equal
in frequency. The PLLl IF output is then described by; Fl
=
Nl
*
10 MHz, where Fl is the PLLl IF output frequency MHz and
Nl
is
the fractional divide number (3.60 to 13.97}.
The A38 PLLl IF assembly's primary function is to mix the output
of PLLl vco with the output of the PLL3 Loop (Fpll3). The
frequency relationships at the mixer are; Fl
=
F2 - Fpll3, where
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Scans by HB9HCA and HB9FSX