HP 8340A, Service Manual

Page: 182 / 326

Model 8340A - Service
non-integer divide numbers. The fractional counter block contains
rate multipliers U5 and U6 and one shot multivibrator Ull. The
rate multipliers produce Ml M2 pulses (Ml M2 is a two digit BCD
number) for 100 pulses input, or the frequency out is ·(Ml M2 /
100) times the frequency in. So if Ml=3 and M2=2 then 32 pulses
will come out for every 100 pulses input. The rate multipliers
are enabled through U2D and the control line HLE2. A HIGH on HLE2
causes the rate multipliers to be enabled. The rate multipliers
have as their clock inputs the Divided Output signal. The output
of this block is the STOP SWALLOW EARLY line which when HIGH
causes the SYNCHRONIZER to bypass the normal routing of the
integer counter output and forces the LSWALLOW line HIGH one
clock pulse earlier than it normally would have. So for the
particular cycle that STOP SWALLOW EARLY is HIGH one less input
pulse is required to produce the same output pulse. The one shot
Ull holds the STOP SWALLOW EARLY line HIGH for about 1.6
microseconds (when triggered by rate multiplier U5) so that the
SYNCHRONIZER will properly respond to it. Assume the rate
multipliers have been set to 32. Therefore 32 output pulses are
produced for every 100 input pulses. So 32 out of 100 cycles the
prescaler is ''swallowing'' one less pulse than it normally would
have, causing the input frequency to decrease (the output
frequency is fixed because of phase lock) . In fact the amount of
decrease is (32/100)
X
500 kHz or 160 kHz. In terms of pulses and
using the previous example of divide by 215 we would have 32
cycles of divide by 214 and 100-32 or 68 cycles of divide by 215.
Adding things up we have:
32 x 214
+
68 x 215 = 21,468
So we have 21,468 input pulses for 100 output pulses or a divide
number of 21,468/100= 214.68 and the input frequency should be
500 kHz
X 214.68 = 107.34 MHz because of phase lock.
SYNCHRONIZER G
The SYNCHRONIZER controls the state of the LSWALLOW line based on
two inputs, the STOP SWALLOW line and the STOP SWALLOW EARLY
line. The LRESET line going LOW causes U3A pin 6 to go HIGH and
U3B pin
9
(LSWALLOW) to go HIGH forcing the prescaler to the
divide by 10 mode. The next CLOCK pulse after LRESET goes HIGH
(LRESET is LOW for 2 CLOCK pulses) causes the U3A pin 6 output
through U2B to change the state of U3B , forcing the LSWALLOW
line LOW. Thus every cycle starts (one CLOCK pulse after LRESET)
with LSWALLOW LOW and the prescaler in the divide by 11 mode. U2A
and U2B serve to route the STOP SWALLOW signal around U3A when
the STOP SWALLOW EARLY line is HIGH thereby causing U3B pin 9 to
go HIGH one clock pulse earlier than normal.
8-252
Scans by HB9HCA and HB9FSX