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Holtek HT85F2260 Manual Download Page 95

Rev. 1.00 

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Standard 8051 8-Bit Flash MCU

HT85F2260/HT85F2270/HT85F2280

Interrupts

Interrupts

IRCON Register 

SFR Address: C0h

Bit

7

6

5

4

3

2

1

0

Name

EXF�

TF�

IEX6

IEX�

IEX4

IEX3

IEX�

—

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

—

POR

0

0

0

0

0

0

0

—

Bit 7 

 EXF2:

 Timer 2 external reload interrupt request flag

0: No request

1: Interrupt request

The EXF2 bit will be set high by a negative transition on the T2EX pin. This bit must 

be cleared using the application program. The EXF2 bit will be invalid in the Timer 2 

Timer/Counter mode.

Bit 6

 TF2:

 Timer 2 overflow interrupt request flag

0: No request

1: Interrupt request

This bit must be cleared using the application program.

Bit 5

 IEX6:

 External interrupt 6 interrupt request flag

0: No request

1: Interrupt request

This bit is triggered by rising edge of external interrupt INT6. The IEX6 flag also will 

be set high when Timer 2 compare mode is enabled and counter value (TH2, TL2) 

is equal to Compare/Capture register 3 (CCH3, CCL3). Once the program into the 

interrupt subroutine, the IEX6 flag will be cleared by hardware automatically.

Bit 4

 IEX5:

 External interrupt 5 interrupt request flag

0: No request

1: Interrupt request

This bit is triggered by rising edge of external interrupt INT5. The IEX5 flag also will 

be set high when Timer 2 compare mode is enabled and counter value (TH2, TL2) 

is equal to Compare/Capture register 2 (CCH2, CCL2). Once the program into the 

interrupt subroutine, the IEX5 flag will be cleared by hardware automatically.

Bit 3

 IEX4:

 External interrupt 4 interrupt request flag

0: No request

1: Interrupt request

This bit is triggered by rising edge of external interrupt INT4. The IEX4 flag also will 

be set high when Timer 2 compare mode is enabled and counter value (TH2, TL2) 

is equal to Compare/Capture register 1 (CCH1, CCL1). Once the program into the 

interrupt subroutine, the IEX4 flag will be cleared by hardware automatically.

Bit 2

 IEX3:

 External interrupt 3 interrupt request flag

0: No request

1: Interrupt request

This bit is triggered by falling or rising edge of external interrupt INT3. The IEX3 flag 

also will be set high when Timer 2 compare mode is enabled and counter value (TH2, 

TL2) is equal to Compare/Reload/Capture register (CRCH, CRCL). Once the program 

into the interrupt subroutine, the IEX3 flag will be cleared by hardware automatically.

Bit 1

 IEX2:

 External interrupt 2 interrupt request flag

0: No request

1: Interrupt request

This bit is triggered by falling or rising edge of external interrupt INT2. This bit will be 

cleared by hardware automatically.

Bit 0 

Unimplemented, read as "0"

Summary of Contents for HT85F2260

Page 1: ...Standard 8051 8 Bit Flash MCU HT85F2260 HT85F2270 HT85F2280 Revision V1 00 Date January 15 2015 ...

Page 2: ...lectrical Characteristics 26 11 DAC Electrical Characteristics 26 12 Comparator Electrical Characteristics 27 13 Power on Reset Electrical Characteristics 28 14 System Architecture 28 15 Program Counter 29 16 Stack 29 17 Arithmetic and Logic Unit ALU 30 18 Flash Program Memory 31 Structure 31 Special Vectors 31 In Circuit Programming ICP 32 On Chip Debug Support OCDS 32 In Application Programming ...

Page 3: ...Control Register 54 Program Status Word 56 20 Oscillators 57 System Oscillator Overview 57 System Clock Configuration 57 External High Speed Crystal Oscillator HXT 57 Internal High Speed RC Oscillator HIRC 58 External Low Speed Crystal Oscillator LXT 58 Internal Low Speed RC Oscillator LIRC 59 21 Operating Modes and System Clocks 60 System Clocks Description 60 Phase Locked Loop PLL 64 Changing th...

Page 4: ...esets 83 SRST Register Software Reset 83 WDTCR Register Software Reset 84 LVRCR Register Software Reset 84 ROM Code Check Reset 85 Reset Initial Conditions 85 25 Interrupts 91 Interrupt Registers 91 Interrupt Operation 103 Interrupt Priority 106 Priority Levels 106 Priority Control Registers 108 External Interrupt 111 Comparator Interrupt 112 A D Converter Interrupt 113 Timer Counter Interrupt 113...

Page 5: ... 126 Timer Event Counter Summary 126 28 Timer Event Counters 0 1 3 127 Introduction 127 Timer 0 Timer 1 Timer 3 Register Description 128 Mode 0 13 bit Counter Timer Mode Operation 135 Mode 1 16 bit Counter Timer Mode Operation 135 Mode 2 8 bit Auto reload Counter Timer Mode Operation 136 Mode 3 Two 8 Bit Timers Counters Mode Operation Timer 0 Only 137 29 Timer 2 with Additional 4 channel PCA 138 I...

Page 6: ...siderations 162 A D Transfer Function 162 31 Digital to Analog Converter DAC 163 DAC Register Description 163 DAC Operation 165 DAC Reference Voltage Source 166 Programming Considerations 166 32 Voltage Reference Generator 167 Voltage Reference Generator Operation 167 33 Comparators 169 Comparator Operation 169 Comparator Registers 170 Comparator Interrupt 175 Comparator Reset Function 175 Program...

Page 7: ...UART0 Operating Description 199 UART0 External Pin Interfacing 199 UART0 Register Description 200 UART0 Operating Modes 204 UART0 Multiprocessor Communication 208 UART0 Baud Rate Setup 208 UART1 Operating Description 209 UART1 External Pin Interfacing 209 UART1 Register Description 210 UART1 Operating Modes 213 UART1 Multiprocessor Communication 215 UART1 Baud Rate Setup 215 37 Instruction Set 216...

Page 8: ...ta RAM 20H 2FH Bit Address Map 50 Special Function Register Bit Addresses Map 51 Special Function Register Map 52 DPS Register Data Pointer Select Register 54 DPC Register Data Pointer Control Register 55 PSW Register Program Status Word Register 56 Crystal Recommended Capacitor Values 58 32768Hz Crystal Recommended Capacitor Values 59 System Clock Control Register SCCR 62 High Speed Oscillator Co...

Page 9: ...w byte of Interrupt Priority Register 1 IP1 110 High byte of Interrupt Priority Register 1 IP1H 110 Low byte of Interrupt Priority Register 2 IP2 111 High byte of Interrupt Priority Register 2 IP2H 111 Low byte of Interrupt Priority Register 3 IP3 111 How byte of Interrupt Priority Register 3 IP3H 112 External Interrupt Trigger Type 112 CPICR Register 113 TBCR Register 115 I O Port Function Summar...

Page 10: ...9 Timer 2 with PCA Modules I O Pins 139 Timer 2 Register List 143 CCEN Register 143 T2CON Register 144 T2CON1 Register 145 A D Converter Register List 154 A D Data Registers 154 ADCR0 Register 155 ADCR1 Register 156 ADCR2 Register 157 ADPGA Register 158 A D Clock Period Examples 159 A D Converter Voltage Reference Select 160 DAH Register 164 DAL Register 164 DACTRL Register 164 DAC Converter Volta...

Page 11: ...ol register 202 S0RELL Register UART0 Reload Low Register 203 S0RELH Register UART0 Reload High Register 203 SPPRE Register UART Clock Prescaler Register 203 SBRCON Register 204 PCON Register 204 UART0 Operating Modes 205 Mode 0 205 UART1 Register List 211 S1BUF Register UART1 Data register 211 S1CON Register UART1 Control register 212 S1RELL Register UART1 Reload Low Register 213 S1RELH Register ...

Page 12: ...8 Interrupt Structure 105 Interrupt Flowchart 106 Time Base Clock Source Select 114 Quasi bidirectional I O Structure 124 Push pull Output Structure 125 Open drain Output Structure 125 Input Only Structure 125 Mode 0 and Mode 1 Block Diagram Timer 0 1 3 136 Mode 2 Block Diagram Timer 0 1 3 137 Mode 3 Block Diagram Timer 0 138 Timer 2 with PCA Modules Block Diagram 140 Capture Modes Block Diagram 1...

Page 13: ...ram 184 Single SPI Master and single Slave Connection 190 SPI Interface Block Diagram 191 SPI Master Mode Timing 195 SPI Slave Mode Timing CPHA 0 196 SPI Slave Mode Timing CPHA 1 196 SPI Transfer Control Flowchart 197 Basic UART Data Transfer Diagram 199 UART 0 Block Diagram 200 UART0 Mode 0 Timing Diagram 205 UART0 Mode 1 Timing Diagram 206 UART0 Mode 2 Timing Diagram 207 UART0 Mode 3 Timing Diag...

Page 14: ...z system clock at VDD 5V 8051 compatible instruction set Flexible Power down and wake up functions to reduce power consumption Oscillator types External high frequency crystal Internal high frequency RC External low frequency crystal Internal low frequency RC Multi mode operation Normal Idle and Power Down Modes Fully integrated internal 3 6864MHz oscillator requires no external components Interna...

Page 15: ...rial SPI Interface I2 C Interface Dual UART Interfaces Dual Comparator functions Up to 48 bidirectional I O lines 16 bit Programmable Counter Array with 5 Capture Compare Modules 16 bit Programmable Counter Array Single Time Base functions for generation of fixed time interrupt signal Internal Temperature Sensor Low voltage reset function Low voltage detect function Package types 48 LQFP and 64 LQ...

Page 16: ... Voltage Detector and excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments A full choice of both internal and external high and low speed oscillators are provided with the internal oscillators requiring no external components for its implementation A fully internal Phase Locked Loop and the ability to operate and switch dynamic...

Page 17: ...ble summarises the main features of each device Part No VDD Program Memory Data Memory I O Ext Interrupt 16 bit Timer 16 bit PCA Time Base HT85F2260 2 2V 5 5V 16K 8 1280 8 32 7 4 CCU 4 1 HT85F2270 2 2V 5 5V 32K 8 2304 8 48 7 4 CCU 4 1 HT85F2280 2 2V 5 5V 64K 8 2304 8 48 7 4 CCU 4 1 Part No A D D A Comparator I2 C SPI UART Temp Sensor package HT85F2260 12 bit 7 12 bit 1 2 1 48LQFP HT85F2270 12 bit ...

Page 18: ... 00 18 of 225 January 15 2015 Standard 8051 8 Bit Flash MCU HT85F2260 HT85F2270 HT85F2280 Block Diagram 4 Block Diagram The following block diagram illustrates the main functional blocks 32768Hz I 3 6864MHz ...

Page 19: ...5F2280 Pin Assignment 5 Pin Assignment Note 1 If the pin shared pin functions have multiple outputs simultaneously its pin names at the right side of the sign can be used for higher priority 2 For both the 48 LQFP A and 64 LQFP A packages both real IC and OCDS EV IC share the same package ...

Page 20: ...d wake up SSN ST SPI Slave select Input P0 3 SCK P0 3 P0M0 P0M1 P0WAKE ST CMOS General purpose I O Register selected I O mode and wake up SCK ST CMOS SPI Clock P0 4 MISO P0 4 P0M0 P0M1 P0WAKE ST CMOS General purpose I O Register selected I O mode and wake up MISO ST CMOS SPI Master In Slave Out pin P0 5 MOSI P0 5 P0M0 P0M1 P0WAKE ST CMOS General purpose I O Register selected I O mode and wake up M...

Page 21: ...MOS General purpose I O Register selected I O mode RXD0 ST UART0 Receive Data Input P3 1 TXD0 P3 1 P3M0 P3M1 ST CMOS General purpose I O Register selected I O mode TXD0 CMOS UART0 Transmit Data Output P3 2 INT0 P3 2 P3M0 P3M1 ST CMOS General purpose I O Register selected I O mode INT0 ST External Interrupt 0 Input P3 3 INT1 P3 3 P3M0 P3M1 ST CMOS General purpose I O Register selected I O mode INT1...

Page 22: ...purpose I O Register selected I O mode XT2 LXT Low Frequency Crystal Oscillator P5 7 DAC P5 7 P5M0 P5M1 ST CMOS General purpose I O Register selected I O mode DAC CMOS DAC Output CP0 CP0 CP0 AN Comparator 0 Inverting Input CP0 AN Comparator 0 Non Inverting Input CP1 CP1 CP1 AN Comparator 1 Inverting Input CP1 AN Comparator 1 Non Inverting Input OSC1 OSC1 HXT High Frequency Crystal Oscillator OSC2 ...

Page 23: ...ge High Frequency Internal RC OSC fOSC fSYS 3 6864MHz PLL disabled 2 2 5 5 V VDD2 Operating Voltage Crystal OSC fOSC fSYS 8MHz PLL disabled 2 2 5 5 V VDD3 Operating Voltage PLL fOSC 4MHz Crystal OSC fSYS 12MHz PLL 3 2 7 5 5 V VDD4 Operating Voltage PLL fOSC 4MHz Crystal OSC fSYS 16MHz PLL 4 3 3 5 5 V VDD5 Operating Voltage PLL fOSC 4MHz Crystal OSC fSYS 24MHz PLL 6 4 5 5 5 V IDD1 Operating Current...

Page 24: ...40 μA 3 3V 80 5 0V 160 IIL Logical 0 input current Ports 0 1 2 3 4 5 quasi bidirection mode 5V VIN 0 4V 50 μA ITL Logical 1 to 0 transition Current Ports 0 1 2 3 4 5 quasi bidirection mode 5V VIN 2 4V 950 μA ILI Input Leakage current Ports 0 1 2 3 input mode 5V 0 45V VIN VDD 0 3 10 μA VBG Bandgap reference with buffer voltage for A D type MCU Tiny Power IP 3 1 1 3 V IBG Additional Power Consumptio...

Page 25: ...scillator 3V Ta 25 C 3 3 6864 3 MHz 5V Ta 25 C 3 3 6864 3 fTIMER Timer Input Frequency T0 T3 2 2V 5 5V fSYS 8MHz 0 2 MHz 2 7V 5 5V fSYS 12MHz 0 3 4 5V 5 5V fSYS 24MHz 0 6 tRES External Reset Minimum Low Pulse width 1 3 3 5 μs tSST System start up timer period Power up or wake up from Power Down mode when the main oscillator is off or system clock is switching between HXT and HIRC fSYS HXT or HIRC ...

Page 26: ...5V VREF AVDD tADCK 1μs 4 4 LSB IADC Additional Power Consumption if A D Converter is used 3V No load tADCK 0 5μs 1 00 1 40 mA 5V 1 30 2 00 mA tADCK A D Converter Clock Period 0 5 10 μs tADC A D Conversion Time Include Sample and Hold Time 12 bit ADC 16 tADCK tADS A D Converter Sampling Time 4 tADCK tON2ST ADC on to ADC start 2 μs 11 DAC Electrical Characteristics VDD 3V AV 3 0V VREF 2 4V no output...

Page 27: ...resis 1 5V CP n HP 1 0 00b 0 1 mV VHP2 Positive Hysteresis 2 5V CP n HP 1 0 01b 3 6 10 mV VHP3 Positive Hysteresis 3 5V CP n HP 1 0 10b 6 13 20 mV VHP4 Positive Hysteresis 4 5V CP n HP 1 0 11b 12 25 40 mV VHN1 Negative Hysteresis 1 5V CP n HN 1 0 00b 0 1 mV VHN2 Negative Hysteresis 2 5V CP n HN 1 0 01b 3 6 10 mV VHN3 Negative Hysteresis 3 5V CP n HN 1 0 10b 6 13 20 mV VHN4 Negative Hysteresis 4 5V...

Page 28: ...scheme is implemented in such a way that instruction fetching and instruction execution are overlapped hence most instructions are effectively executed in one clock cycle with the exception of branch or call instructions Compared with classic MCU architecture the 8051 based core runs at a much higher speed and with greatly reduced power consumption An 8 bit wide ALU is used in practically all oper...

Page 29: ...ated level is indexed by the Stack Pointer SP and is neither readable nor writeable At a subroutine call or interrupt acknowledge signal the contents of the Program Counter are pushed onto the stack At the end of a subroutine or an interrupt routine signaled by a return instruction RET or RETI the Program Counter is restored to its previous value from the stack After a device reset the Stack Point...

Page 30: ...instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register As these ALU calculation or operations may result in carry borrow or other status changes the status register will be correspondingly updated to reflect these changes The ALU supports the following functions Arithmetic operations ADD ADDC SUBB DA MUL DIV Logi...

Page 31: ...ield programming and updating Structure The Program Memory has a capacity from 16K 8 to 64K 8 The Program Memory is addressed by the Program Counter and also contains data table information and interrupt entries Table data which can be setup in any location within the Program Memory is addressed by a separate table pointer register Special Vectors Within the Program Memory certain locations are re...

Page 32: ...ith an additional line for the clock Two additional lines are required for the power supply The technical details regarding the in circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature The Flash Program Memory Read Write function is implemented using a series of registers On Chip Debug Support OCDS An EV chip HT85V2280 is provided ...

Page 33: ...data operations using the address and data registers and the control registers The address registers are named FMAR0 FMAR1 and FMAR2 the data register is named FMDR and the three control registers are named FMKEY FMCR and FMSR As these registers are located in Special Function Register area they can be directly accessed in the same was as any other Special Function Register Program Memory Register...

Page 34: ...ory Address Register 2 SFR Address FCh Bit 7 6 5 4 3 2 1 0 Name INBLK FADDR22 FADDR21 FADDR20 FADDR19 FADDR18 FADDR17 FADDR16 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 INBLK Flash memory access block selection 0 Main Flash program memory area 1 Information block area Bit 6 0 Flash Program Memory address Flash Program Memory address bit 22 bit 16 FMDR Register Flash Program Memo...

Page 35: ...yte 0xFF within a page a write operation is allowed But for those written bytes except for 0xFF a re write operation is prohibited to avoid Flash errors The writing time is shorter 1 Before the main program executes a byte write operation a page erase operation is automatically executed Any location within the page is then rewritable but the write time is longer Note that the security bytes 00h 1F...

Page 36: ...e program memory at all times FMSR Register Flash Program Memory Status Register SFR Address E2h Bit 7 6 5 4 3 2 1 0 Name UNLOCK FMPF FMSEF FMBF FMBUSY R W R R R R R POR 0 0 0 0 0 Bit 7 UNLOCK Flash memory Control Registers Unlock flag 0 Indicated Flash Memory Controller is locked 1 Indicated Flash Memory Controller is unlocked Bit 6 4 Unimplemented read as 0 Bit 3 FMPF Flash Memory Controller Pro...

Page 37: ...Flash Memory Unlocking the Flash Memory Before writing data to the Flash Memory it must first be unlocked This is implemented by writing a correct data sequence to the Flash Memory Unlock key register FMKEY It is recommended to write the data sequence to the FMKEY register in 4 consecutive instructions The following flowchart illustrates the unlock procedure START FMKEY 0x FMKEY 0xAA FMKEY 0x00 FM...

Page 38: ...unction is selected by the control bit FMCR 2 in the FMCR register Setting the FMCR 7 bit high will start the Page Erase procedure When the procedure has finished the MCU will continue to run automatically The following flowchart illustrates the Page Erase procedure START END Write FMAR2 Write FMAR1 Write FMAR0 MCU waits for page erasing finished Then MCU continues to run Flash memory controller m...

Page 39: ...y Page Read function is selected by the control bit FMCR 1 in the FMCR register When the FMCR 7 bit is set high the Byte Read procedure will be initiated When the procedure is ready the MCU will continue to run automatically The following flowchart illustrates the Byte Read procedure START END Write FMAR2 Write FMAR1 Write FMAR0 Flash memory controller must be In unlocked state FMCR Bit 1 1 This w...

Page 40: ...he boundary has been reached or there is no more data then set the FMCR 0 bit to high to enable the Byte Write function When the FMCR 7 bit is set high the Byte Write procedure will be executed When the procedure is ready the MCU will continue to run automatically The following flowchart illustrates the Byte Write procedure START MCU waits for memory dump finished and then MCU continues to run Fla...

Page 41: ...ory controller must be In unlocked state Write FMAR2 Write FMAR1 Write FMAR0 FMCR Bit 0 1 and FMCR Bit 6 1 Enter memory dump procedure Write next page if desired MCU waits for byte writing finished and then MCU continues to run FMCR Bit 7 1 Update the Page Buffer By writing FMDR FMARx reach the page boundary More Data No Yes No Yes Check FMSR Bit 1 1 Yes No Byte Write Flowchart FMCR 0 1 FMCR 6 1 ...

Page 42: ... page 0 If a value with the exception of 0FFH is written into these bytes the sectors corresponding to SECURITY1 0 15 cannot be programmed erased or read by the ICP For the IAP program when in the OCDS mode any sector N with a security mechanism can be protected from being programmed erased or read by the OCDSINSTR instruction But when in the main program all sector N with security or not can be p...

Page 43: ...X X N A 1 N Erase All IAP OCDS 5 X 3 X X 4 N Erase All Main Program X 3 X X 4 N Erase All M O V C OCDS 5 N A 2 X 4 N Erase All Main Program N A 2 X 4 N Erase All Note 1 N A means no path to read ROM code 2 N A means none of these functions 3 X stands for inhibited O stands for enabled 4 If a read operation is inhibited reading to the Flash will return a fixed Flash code of 00H 5 When in the OCDS m...

Page 44: ...x88 0x8F Reserved 0x90 0x97 Reserved 0x98 0x9F Reserved 0xA0 0xEF Reserved 0xF0 0xFF Reserved HT85F2280 Program Memory Contents The HT85F2280 program memory is divided into 16 sectors each with a capacity of 4k bytes Page Address Description 0 0x00 0x0F SECURITY1 0 SECURITY1 15 0x10 0x1F SECURITY2 0 SECURITY2 15 0x20 0x6F Reserved 0x70 0x7F Reserved 1 0x80 0x8F Reserved 0x90 0x9F Reserved 0xA0 0xE...

Page 45: ...is not protected Can be erased and programmed Can be read by flash control registers related to the IAP and OCDS note and the MOVC instructions 0FFH Other values except 0FFH Sector N is inhibited from Programming Erasing Can not be erased and programmed by the ICP or flash control registers related to the OCDS note Can be erased and programmed by flash control registers related to the IAP Can be r...

Page 46: ...accessed using indirect addressing methods The upper section 128 byte RAM has an address range of 80H to FFH and is assigned to both the General Purpose memory and the Special Function Registers Although the address range is identical these two RAM sections are physically separate they are distinguished by their different addressing methodology Using direct addressing instructions will point to th...

Page 47: ...ose RAM 00H 7FH 8 bit Register Bank 0 Register Bank 1 Register Bank 2 Register Bank 3 08H 10H 18H 20H Bit Addressable Space 30H Upper 128 Bytes General Purpose RAM Indirect Access 80H FFH Special Function Registers Direct Access Both direct and indirect access Upper Section 128 bytes Lower Section 128 bytes Internal Data Memory Structure ...

Page 48: ...Rev 1 00 48 of 225 January 15 2015 Standard 8051 8 Bit Flash MCU HT85F2260 HT85F2270 HT85F2280 RAM Data Memory RAM 2048 bytes 0000H 07FFH 8 bit FFFFH RESERVED 0800H HT85F2270 HT85F2280 XDATA ...

Page 49: ...Rev 1 00 49 of 225 January 15 2015 Standard 8051 8 Bit Flash MCU HT85F2260 HT85F2270 HT85F2280 RAM Data Memory RAM 1024 bytes 0000H 03FFH 8 bit FFFFH RESERVED 0400H HT85F2260 XDATA ...

Page 50: ...ption for General Purpose Data RAM 20H 2FH Using the bit operational instruction such as SETB or CLR on the bit address can implement operations on the corresponding bit of the register For example SETB 00H Set the bit 0 of the register location 20H to 1 SETB 07H Set the bit 7 of the register location 20H to 1 CLR 25H Clear the bit 5 of the register location 24H to 0 CLR 7FH Clear the bit 7 of the...

Page 51: ...ss 0H 1H 2H 3H 4H 5H 6H 7H F8h FMCR 0 FMCR 1 FMCR 2 FMCR 6 FMCR 7 F0h B 0 B 1 B 2 B 3 B 4 B 5 B 6 B 7 E8h SPCON 0 SPCON 1 SPCON 2 SPCON 3 SPCON 4 SPCON 5 SPCON 6 SPCON 7 E0h ACC 0 ACC 1 ACC 2 ACC 3 ACC 4 ACC 5 ACC 6 ACC 7 D8h I2CCON 2 I2CCON 3 I2CCON 4 I2CCON 5 I2CCON 6 D0h PSW 0 PSW 1 PSW 2 PSW 3 PSW 4 PSW 5 PSW 6 PSW 7 C8h T2CON 0 T2CON 1 T2CON 2 T2CON 3 T2CON 4 T2CON 5 T2CON 6 C0h IRCON 1 IRCON...

Page 52: ...Special Function Register Map High 5 bit Address Low 3 bit Address 0H 1H 2H 3H 4H 5H 6H 7H F8h FMCR FMKEY FMAR0 FMAR1 FMAR2 FMDR T2CON1 RSTSRC F0h B ADCR0 ADCR1 ADCR2 ADPGA ADRL ADRH SRST E8h SPCON I2CLK LVRCR LVDCR SCCR PLLCR LSOCR HSOCR E0h ACC SPSTA FMSR SPDAT IP1 IP1H IP2 IP2H D8h I2CCON P5 I2CDAT I2CADR SBRCON I2CSTA CP0CR CP1CR D0h PSW C8h T2CON IEN3 CRCL CRCH TL2 TH2 IP3 IP3H C0h IRCON CCEN...

Page 53: ... This causes the stack to begin at location 08H It is used to store the return address of the main program before executing interrupt routines or subprograms The SP is incremented before executing a PUSH or CALL instruction and it is decremented after executing a POP RET or RETI instruction DPL DPH DPL1 DPH1 Registers Data Pointer Registers The Data Pointer DPTR registers DPL DPH DPL1 and DPH1 alt...

Page 54: ...his register is used to control whether the DPTR auto increment auto decrement has a value of either 1 or 2 and auto switching between active DPTRs functions The auto switching active DPTR function is controlled by the DPC3 bit in the DPC register The content of this bit will be loaded to the DPS register after a MOVX DPTR instruction is executed The auto modification function is controlled by the...

Page 55: ...n a different value pointing to itself so that the auto switching does not occur with default reset values Bit 2 DPC2 Auto modification size 0 Modified size by 1 1 Modified size by 2 The current DPTR will be automatically modified by size selected by the DPC2 bit after each MOVX DPTR instruction when DPC0 1 Bit 1 DPC1 the current DPTR Auto modification direction 0 Automatically incremented 1 Autom...

Page 56: ...operations and accumulator for Boolean operations Bit 6 AC Auxiliary flag 0 No auxiliary carry 1 An operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble on subtraction Bit 5 F0 General Purpose Flag 0 This bit is used as a general purpose flag by the application program Bit 4 3 RS1 RS0 Select Data Memory Banks 00 Bank 0 01 Bank 1 10 B...

Page 57: ...T1 XT2 Internal Low Speed RC LIRC WDT and Time Base Clock 32kHz System Clock Configuration There are four oscillators two high speed oscillators and two low speed oscillators The high speed oscillators are the external crystal HXT and the internal RC oscillator HIRC which are used as the system oscillators The two low speed oscillators are the external 32768Hz oscillator LXT and the internal 32kHz...

Page 58: ...re minimised The internal RC oscillator frequency can be multiplied from 1 to 8 times using the internal PLL If the HIRC oscillator is used as the system oscillator then the OSC1 and OSC2 pins should be left unconnected External Low Speed Crystal Oscillator LXT The external low speed crystal oscillator LXT is used as the clock source for the Watchdog Timer and the Time Base functions When the micr...

Page 59: ...ning on chip RC oscillator used as a clock source for the Watchdog Timer and the Time Base functions When the microcontroller enters the IDLE Mode the CPU clock is switched off to stop microcontroller activity and to conserve power however the LIRC oscillator will continue to run and can maintain WDT and Time Base operation if it is selected as their clock source The LIRC oscillator has a typical ...

Page 60: ...umption As Holtek has provided these devices with a range of oscillators and a PLL function the user can optimise the system clock frequency to achieve the best performance power ratio In addition to the two high frequency system oscillators two low frequency 32kHz oscillators are also provided as clock sources for the WDT and Time Base The MCU system clock is sourced from the high speed external ...

Page 61: ...Oscillato HXT Inte nal RC Oscillato HIRC Inte nal RC Oscillato LIRC Exte nal C stal Oscillato LXT Watchdog Time WDTCS 3 k SCKS 1 0 M U X M U X M U X M U X Time Base PLLM 0 fSYS M U X TBCK 1 0 fWDT fTB IDL bit enable disable CPU clock PD bit enable disable selected oscillato s HXTEN bit enable disable HIRCEN bit enable disable fSYS 16 fSYS 4 o fSYS 1 8 System Clock Configurations ...

Page 62: ...be changed later by the application program There are two additional internal 32kHz low frequency clocks for the peripheral circuits These are the external crystal LXT oscillator and the internal LIRC oscillators The selection is implemented using the LSOSEL bit in the LSOCR register There is a low frequency oscillator status bit LSORDY to indicate the ready or not status of the low frequency osci...

Page 63: ... if the HIRC oscillator is stable or not This bit will be cleared to zero by hardware when the HIRC function is disabled After power on if the HIRC oscillator is enabled the bit will change to a high level when the internal high frequency oscillator is stable Bit 3 2 Unimplemented read as 0 Bit 1 HXTEN HXT control bit 0 Disable 1 Enable Bit 0 HIRCEN HIRC control bit 0 Disable 1 Enable After power ...

Page 64: ...he PLL is enabled and is being used as the system clock its frequency can be changed dynamically by the application program by programming the PLLM0 PLLM2 bits in the PLLCR register However the program must execute this operation in a specific way to ensure stable frequency switching There are a total of eight different PLL frequency multiplier selections however during dynamic PLL frequency chang...

Page 65: ...is bit is used to indicate when the PLL is locked and ready for use This bit will be initially cleared to zero by hardware when the device is powered on The bit will be cleared to zero if the PLL is in use and is then disabled but will not be cleared if the PLL changes frequency Bit 5 Unimplemented read as 0 Bit 4 PLLSRC PLL Clock Source Select 0 HIRC clock source 1 HXT clock source Note that if t...

Page 66: ...ff Low Frequency Internal RC Oscillator LIRC On LSOSEL 0 Off On LSOSEL 0 Off Off High Frequency XTAL Oscillator HXT On HXTEN 1 Off On HXTEN 1 Off Off High Frequency Internal RC Oscillator HIRC On HIRCEN 1 Off On HIRCEN 1 Off Off Note Peripheral Clock is the clock for Timer 0 Timer 1 Timer 2 Timer 3 PCA UART0 UART1 I2 C SPI ADC and DAC NORMAL Mode As the name suggests this is the main operating mod...

Page 67: ...he PD bit is set high to enable the Power Down Mode then the condition of the IDL bit will be overridden Standby Current Considerations As the main reason to stop the oscillators is to keep the current consumption of the MCU to as low a value as possible perhaps only in the order of several micro amps there are other considerations which must also be taken into account by the circuit designer if t...

Page 68: ...tuations may occur The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full in which case the program will resume execution at the instruction following the control bits settings In this situation the interrupt which woke up the device will not be immediately serviced but will rather be serviced later when the related interrupt is finally enabled or wh...

Page 69: ...nown locations or entering endless program loops due to certain uncontrollable external events such as electrical noise Its basic structure is a 16 bit timer which when it overflows will execute an MCU reset operation The accompanying diagram illustrates the basic operational block diagram 16 fSYS WDTCS WDTL 16 WDTH WDT Software Reset Watchdog Counter Registers WDTREL Latch WDT SWDT LXT LIRC LSOSE...

Page 70: ...6 D5 D4 D3 D2 D1 D0 WDTCR WE4 WE3 WE2 WE1 WE0 WDTCS IP0 WDTS PT2 PS0 PT1 PX1 PT0 PX0 Note The bit and flag names in brackets are used to manage other functions and not related to the WDT control IEN0 Register SFR Address A8h Bit 7 6 5 4 3 2 1 0 Name EAL WDT ET2 ES0 ET1 EX1 ET0 EX0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 EAL Master interrupt global enable Described elsewhere B...

Page 71: ...by hardware automatically This bit is always read as 0 Bit 5 ET3 Timer 3 overflow interrupt enable Described elsewhere Bit 4 ECMP Comparator overall interrupt enable Described elsewhere Bit 3 EX6 External interrupt 6 enable Described elsewhere Bit 2 EX5 External interrupt 5 enable Described elsewhere Bit 1 EX4 External interrupt 4 enable Described elsewhere Bit 0 EX3 External interrupt 3 enable De...

Page 72: ...be enabled after any reset takes place For more details regarding the reset operation refer to the Reset section IP0 Register SFR Address B8h Bit 7 6 5 4 3 2 1 0 Name WDTS PT2 PS0 PT1 PX1 PT0 PX0 R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 Bit 7 Unimplemented read as 0 Bit 6 WDTS Watchdog timer reset indication flag 0 No Watchdog timer reset 1 Watchdog timer reset Bit 5 PT2 Timer 2 Interrupt...

Page 73: ...he user in which case the Watchdog Timer will overflow and reset the device There are five bits WE4 WE0 in the WDTCR register to enable disable the Watchdog Timer The WE4 WE0 bits must be set to a specific value of 10101 to disable the WDT A value of 01010 will enable the WDT while any other value will execute an MCU reset Using this methodology enhanced device protection is provided After power o...

Page 74: ...260 HT85F2270 HT85F2280 Watchdog Timer WDT running Program sets WDT bit Must not insert other instructions here Program sets SWDT bit H W auto Clear WDT bit H W auto Clear SWDT bit WDT continues running WDT loaded with WDTREL register value Watchdog Timer Refresh Operation ...

Page 75: ...a certain amount of power it may be desirable to switch off the circuit when not in use an important consideration in power sensitive battery powered applications LVDCR Register SFR Address EBh Bit 7 6 5 4 3 2 1 0 Name LVDEN LVDS2 LVDS1 LVDS0 R W R W R W R W R W POR 0 0 0 0 Bit 7 LVDEN LVD Function Control 0 Disable 1 Enable Bit 6 3 Unimplemented read as 0 Bit 2 0 LVDS2 LVDS0 Select LVD Voltage 00...

Page 76: ...nternal registers will be set to defined states before the program instructions commence execution One of these registers is the Program Counter which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address The devices provide several reset sources to generate the internal reset signal providing extended MCU protection The different types...

Page 77: ... and can therefore not be cleared by the application program after one of the relevant reset occurs After one of these reset occurs and the relevant bit is high to indicate its occurrence the bit can only be cleared by hardware when another different reset type occurs RSTSRC Register SFR Address FFh Bit 7 6 5 4 3 2 1 0 Label LRF WRF CMP0F LVRF XRSTF PORF R W R R R R R R POR 0 0 0 x 0 1 Bit 7 Unimp...

Page 78: ... does not stabilise quickly at power on the internal reset function may be incapable of providing proper reset operation For this reason it is recommended that an external RC network is connected to the RESET pin whose additional time delay will ensure that the RESET pin remains low for an extended period to allow the power supply to stabilise During this time delay normal operation of the microco...

Page 79: ...1μF 10kΩ 0 01μF Enhanced Reset Circuit This type of reset occurs when the microcontroller is already running and the RESET pin is forcefully pulled low by external hardware such as an external switch In this case as in the case of other resets the Program Counter will reset to zero and program execution initiated from this point Note that during the power up sequence the reset circuit should make ...

Page 80: ...ister If the LVS7 LVS0 bits are changed to some certain values by the environmental noise the LVR will reset the device after 2 3 LIRC clock cycles When this happens the LRF bit in the RSTSRC register will be set to 1 After power on the register will have the value of 01010101B Note that the LVR function will be automatically disabled when the device enters the power down mode LVRCR Register SFR A...

Page 81: ...n When a Watchdog Reset occurs the WDTS bit in the IP0 register will be set to indicate the reset source Note that this bit must be reset by the application program IP0 Register SFR Address B8h Bit 7 6 5 4 3 2 1 0 Name WDTS PT2 PS0 PT1 PX1 PT0 PX0 R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 Bit 7 Unimplemented read as 0 Bit 6 WDTS Watchdog timer reset indication flag 0 No Watchdog timer rese...

Page 82: ... generates the reset The CMP0F bit in the RSTSRC register is used to indicate the Comparator 0 reset source CP0CR Register SFR Address DEh Bit 7 6 5 4 3 2 1 0 Label CP0ON CP0POL CP0OUT CP0OS CP0RSTL CP0RST R W R W R W R R W R W R W POR 0 0 0 1 0 0 Bit 7 Unimplemented read as 0 Bit 6 CP0ON Comparator 0 on off bit Described elsewhere Bit 5 CP0POL Comparator 0 output polarity Described elsewhere Bit ...

Page 83: ...10101 00110011 011001 or 10101010 SRST Register Software Reset A software reset will be generated after two consecutive instructions to write a high value to the SRSTREQ bit in the SRST register The same bit can be used to identify the reset source SRST Register SFR Address F7h Bit 7 6 5 4 3 2 1 0 Label SRSTREQ R W R W POR 0 Bit 7 1 Unimplemented read as 0 Bit 0 SRSTREQ Software reset request Writ...

Page 84: ...ister will be set Bit 2 1 Unimplemented read as 0 Bit 0 WDTCS Watchdog clock fWDT select Described elsewhere LVRCR Register Software Reset An LVRCR software reset will be generated when a value other than 01010101 00110011 10011001 and 10101010 exist in the LVRCR register The LRF bit in the RSTSRC register will be set high when this occurs thus indicating the generation of an LVRCR software reset ...

Page 85: ...FFH 0xFE 32H FFH 0xFF 10H FFH Reset Initial Conditions The different types of reset described affect the reset flags in different ways The following table indicates the way in which the various components of the microcontroller are affected after a power on reset occurs Item Condition After RESET Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Clear after reset WDT beg...

Page 86: ...0101_0 0b 0101_0 0b 0101_0 ub 0101_0 0b S0CON 0000_0000b 0000_0000b 0000_0000b 0000_0000b S0BUF 0000_0000b 0000_0000b 0000_0000b 0000_0000b IEN2 _ 0 0 0 b _ 0 0 0 b _ 0 0 0 b _ 0 0 0 b S1CON 0 00_0000b 0 00_0000b 0 00_0000b 0 00_0000b S1BUF 0000_0000b 0000_0000b 0000_0000b 0000_0000b S1RELL 0000_0000b 0000_0000b 0000_0000b 0000_0000b P0M0 0000_0000b 0000_0000b 0000_0000b 0000_0000b P0M1 0000_0000b...

Page 87: ... 0000_0000b 0000_0000b 0000_0000b CRCH 0000_0000b 0000_0000b 0000_0000b 0000_0000b TL2 0000_0000b 0000_0000b 0000_0000b 0000_0000b TH2 0000_0000b 0000_0000b 0000_0000b 0000_0000b IP3 _0000b _0000b _0000b _0000b IP3H _0000b _0000b _0000b _0000b PSW 0000_0000b 0000_0000b 0000_0000b 0000_0000b I2CCON 000_00 b 000_00 b 000_00 b 000_00 b P5 1111_1111b 1111_1111b 1111_1111b 1111_1111b I2CDAT 0000_0000b ...

Page 88: ... Reset LVR Reset LVRCR Reset Comparator0 Reset Program Counter 0000h 0000h 0000h 0000h P0 1111_1111b 1111_1111b 1111_1111b 1111_1111b SP 0000_0111b 0000_0111b 0000_0111b 0000_0111b DPL 0000_0000b 0000_0000b 0000_0000b 0000_0000b DPH 0000_0000b 0000_0000b 0000_0000b 0000_0000b DPL1 0000_0000b 0000_0000b 0000_0000b 0000_0000b DPH1 0000_0000b 0000_0000b 0000_0000b 0000_0000b WDTREL 0000_0000b 0000_00...

Page 89: ... 00b 000 _ 00b 000 _ 00b DAL 0000_ b 0000_ b 0000_ b 0000_ b DAH 1000_0000b 1000_0000b 1000_0000b 1000_0000b P3M0 0000_0000b 0000_0000b 0000_0000b 0000_0000b P3M1 0000_0000b 0000_0000b 0000_0000b 0000_0000b IP0 000_0000b 000_0000b 000_0000b 000_0000b IP0H 00_0000b 00_0000b 00_0000b 00_0000b S0RELH _ 11 b _ 11 b _ 11 b _ 11 b S1RELH _ 11 b _ 11 b _ 11 b _ 11 b CPHCR 0000_0000b 0000_0000b 0000_0000b...

Page 90: ...1b 0001_1001b 0001_1001b 0001_1001b LVRCR 0101_0101b uuuu_uuuub 0101_0101b 0101_0101b LVDCR 0 _ 000b 0 _ 000b 0 _ 000b 0 _ 000b SCCR _ 0 0 b _ 0 0 b _ 0 0 b _ 0 0 b PLLCR 00 0_ 000b 00 0_ 000b 00 0_ 000b 00 0_ 000b LSOCR 1 _ 0 b 1 _ 0 b 1 _ 0 b 1 _ 0 b HSOCR 01_ 01b 01_ 01b 01_ 01b 01_ 01b B 0000_0000b 0000_0000b 0000_0000b 0000_0000b ADCR0 0110_0000b 0110_0000b 0110_0000b 0110_0000b ADCR1 00 0_00...

Page 91: ...idual interrupt can be enabled or disabled Also when an interrupt occurs the corresponding request flag will be automatically set by the microcontroller The global enable control bit if cleared to zero will disable all interrupts Overall interrupt control which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the...

Page 92: ...R MODF CPICR CP1IF CP1IEN CP1P1 CP1P0 CP0IF CP0IEN CP0P1 CP0P0 I2CCON ENSI STA STO SI AA Note The bits in brackets are used to manage other functions and not related to the interrupt control IEN0 Register SFR Address A8h Bit 7 6 5 4 3 2 1 0 Name EAL WDT ET2 ES0 ET1 EX1 ET0 EX0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 EAL Master interrupt global enable 0 Disable 1 Enable Bit 6 ...

Page 93: ...errupt enable 0 Disable 1 Enable Bit 4 ECMP Comparator overall interrupt enable 0 Disable 1 Enable Bit 3 EX6 External interrupt 6 enable 0 Disable 1 Enable Bit 2 EX5 External interrupt 5 enable 0 Disable 1 Enable Bit 1 EX4 External interrupt 4 enable 0 Disable 1 Enable Bit 0 EX3 External interrupt 3 enable 0 Disable 1 Enable IEN2 Register SFR Address 9Ah Bit 7 6 5 4 3 2 1 0 Name ES1 ELVD EX2 R W R...

Page 94: ...dress C9h Bit 7 6 5 4 3 2 1 0 Name ETB EADC EI2C ESPI R W R W R W R W R W POR 0 0 0 0 Bit 7 4 Unimplemented read as 0 Bit 3 ETB Time Base interrupt enable 0 Disable 1 Enable Bit 2 EADC ADC interrupt enable 0 Disable 1 Enable Bit 1 EI2C I2 C interrupt enable 0 Disable 1 Enable Bit 0 ESPI SPI interrupt enable 0 Disable 1 Enable ...

Page 95: ...triggered by rising edge of external interrupt INT5 The IEX5 flag also will be set high when Timer 2 compare mode is enabled and counter value TH2 TL2 is equal to Compare Capture register 2 CCH2 CCL2 Once the program into the interrupt subroutine the IEX5 flag will be cleared by hardware automatically Bit 3 IEX4 External interrupt 4 interrupt request flag 0 No request 1 Interrupt request This bit ...

Page 96: ...st flag 0 No request 1 Interrupt request This bit will be cleared by hardware automatically Bit 2 TBF Time Base interrupt request flag 0 No request 1 Interrupt request This bit will be cleared by hardware automatically Bit 1 CMPF Comparator overall interrupt request flag 0 No request 1 Interrupt request This bit will be cleared by hardware automatically Bit 0 IADC ADC interrupt request flag 0 No r...

Page 97: ...0 Multiprocessor communication enable control Described elsewhere Bit 4 REN0 UART 0 serial data reception enable Described elsewhere Bit 3 TB80 UART 0 Ninth Transmit bit assignment Described elsewhere Bit 2 RB80 UART 0 Ninth Receive bit assignment Described elsewhere Bit 1 TI0 UART 0 transmit interrupt flag 0 No request 1 Interrupt request This bit must be cleared using the application program Bit...

Page 98: ...0 Bit 5 SM21 Multiprocessor communication enable control Described elsewhere Bit 4 REN1 UART 1 serial data reception enable Described elsewhere Bit 3 TB81 UART 1 Ninth Transmit bit assignment Described elsewhere Bit 2 RB81 UART 1 Ninth Receive bit assignment Described elsewhere Bit 1 TI1 UART 1 transmit interrupt flag 0 No request 1 Interrupt request This bit must be cleared using the application ...

Page 99: ...ontrol Described elsewhere Bit 5 TF0 Timer 0 interrupt request flag 0 No request 1 Interrupt request This bit will be cleared by hardware automatically Bit 4 TR0 Timer 0 Run control Described elsewhere Bit 3 IE1 External interrupt 1 request flag 0 No request 1 Interrupt request This bit will be cleared by hardware automatically Bit 2 IT1 External interrupt 1 type control 0 Falling Edge 1 Low Level...

Page 100: ...pt When Timer 2 is selected as compare mode 0 the I3FR bit is recommended to be set high by firmware Bit 5 I2FR Active edge selection for external interrupt INT2 0 Falling edge 1 Rising edge Bit 4 3 T2R1 T2R0 Timer 2 reload mode selection Described elsewhere Bit 2 T2CM Timer 2 Compare mode selection Described elsewhere Bit 1 0 T2I1 T2I0 Timer 2 input selection Described elsewhere T3CON Register SF...

Page 101: ...the SPDAT register during a data transfer operation An SPI interrupt will occur if the SPI interrupt function is enabled This write operation will be ignored if data is being transferred It must be cleared using the application program Bit 5 SSERR Synchronous Serial Slave Error Flag 0 No error 1 Error This bit is set by hardware when the SSN pin input is selected to disable the Slave device status...

Page 102: ...P1IEN Comparator 1 Output Transition Interrupt Enable 0 Disable 1 Enable Bit 5 4 CP1P1 CP1P0 Comparator 1 Output Transition Setting for interrupt request 00 Interrupt disabled 01 High to low 10 Low to high 11 High to low or low to high Bit 3 CP0IF Comparator 0 Output Transition Interrupt Request Flag 0 No request 1 Interrupt request This bit should be cleared using the application program Bit 2 CP...

Page 103: ...pens if the interrupt enable bit is set then the Program Counter which stores the address of the next instruction to be executed will be transferred onto the stack The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector The microcontroller will begin then fetch its next instruction from this interrupt vector The instruction at this v...

Page 104: ...o ECMP EAL SSERR SPI IADC ADC EADC TBF Time Base ETB EAL EAL IE1 INT1 Pin EX1 TF1 Time 1 ET1 13H 1BH RI1 TI1 UART 1 ES1 EAL 93H 6BH EAL TF3 Time 3 ET3 Low P io it High Vector Req est Flags Enable Bits Maste Enable Inte pt Name 3BH 43H 4BH IEX INT CCU EX EAL 3H EAL EAL EAL SI I C EI C IEX3 INT3 CCU0 EX3 IEX4 INT4 CCU1 EX4 IEX6 INT6 CCU3 EX6 EAL BH 83H EAL IEX INT Pin EX LVDF LVD ELVD EAL 8BH xxx Re...

Page 105: ...the program is already in another interrupt service routine the EAL bit should be set after entering the routine to allow interrupt nesting If the stack is full the interrupt request will not be acknowledged even if the related interrupt is enabled until the Stack Pointer is decremented If immediate service is desired the stack must be prevented from becoming full When an interrupt request is gene...

Page 106: ...vels by setting or clearing bits in the interrupt priority registers IP0 IP1 IP2 IP3 IP0H IP1H IP2H and IP3H IP0 IP1 IP2 and IP3 hold the low order priority bits and IP0H IP1H IP2H and IP3H hold the high priority bits for each interrupt If the priority level is the same for different groups then an internal polling sequence determines which interrupt request is serviced The polling sequence is bas...

Page 107: ...pheral Interface Interrupt 0033H 6 PSPIH IP3H 0 PSPI IP3 0 I2 C Interrupt 003BH 7 PI2CH IP3H 1 PI2C IP3 1 External Interrupt 3 INT3 or CCU0 Interrupt 0043H 8 PX3H IP1H 0 PX3 IP1 0 External Interrupt 4 INT4 or CCU1 Interrupt 004BH 9 PX4H IP1H 1 PX4 IP1 1 External Interrupt 5 INT5 or CCU2 Interrupt 0053H 10 PX5H IP1H 2 PX5 IP1 2 External Interrupt 6 INT6 or CCU3 Interrupt 005BH 11 PX6H IP1H 3 PX6 IP...

Page 108: ... PT0 Timer 0 Interrupt priority low Low order bit for Timer 0 interrupt priority level Bit 0 PX0 External interrupt 0 priority low Low order bit for External Interupt 0 interrupt priority level High byte of Interrupt Priority Register 0 IP0H SFR Address B9h Bit 7 6 5 4 3 2 1 0 Name PT2H PS0H PT1H PX1H PT0H PX0H R W R W R W R W R W R W R W POR 0 0 0 0 0 0 Bit 7 6 Unimplemented read as 0 Bit 5 PT2H ...

Page 109: ...terrupt 4 interrupt priority level Bit 0 PX3 External interrupt 3 priority low Low order bit for External Interupt 3 interrupt priority level High byte of Interrupt Priority Register 1 IP1H SFR Address E5h Bit 7 6 5 4 3 2 1 0 Name PT3H PCMPH PX6H PX5H PX4H PX3H R W R W R W R W R W R W R W POR 0 0 0 0 0 0 Bit 7 6 Unimplemented read as 0 Bit 5 PT3H Timer 3 Interrupt priority high High order bit for ...

Page 110: ... W R W POR 0 0 0 Bit 7 3 Unimplemented read as 0 Bit 2 PS1H UART 1 priority high High order bit for UART 1 interrupt priority level Bit 1 PLVDH LVD Interrupt priority high High order bit for LVD interrupt priority level Bit 0 PX2H External interrupt 2 priority high High order bit for External Interupt 2 interrupt priority level Low byte of Interrupt Priority Register 3 IP3 SFR Address CEh Bit 7 6 ...

Page 111: ... an input by setting the corresponding bits in the port mode register Any pull high resistor settings will also remain valid when the pin is used as an external interrupt pin When the interrupt is enabled the stack is not full and a falling edge a rising edge or a high to low level transition appears on the external interrupt pin a subroutine call to the external interrupt vector will take place W...

Page 112: ... by the CPICR control register Note that the comparator overall request flag CMPF will be automatically cleared however the individual comparator interrupt request flags CPnIF must be cleared by the application program The EAL bit must be cleared by the application program to disable other interrupts when in the interrupt routine CPICR Register SFR Address BEh Bit 7 6 5 4 3 2 1 0 Name CP1IF CP1IEN...

Page 113: ...is serviced the timer interrupt request flag TFn n 0 1 3 will be automatically reset while the TF2 bit must be cleared by the application program and the EAL bit must also be cleared using the application program to disable other interrupts Time Base Interrupts The function of the Time Base Interrupt is to provide a regular time signal in the form of an internal interrupt It is basically a simple ...

Page 114: ...92 fTBC 110 16384 fTBC 111 32768 fTBC default setting I2 C Interface Interrupt An I2 C Interrupt request will take place when the I2 C Interrupt request flag SI is set which occurs when one of the 25 possible I2 C states takes place To allow the program to branch to its respective interrupt vector address the global interrupt enable bit EAL and the I2 C Interface Interrupt enable bit EI2C must fir...

Page 115: ...t request will take place when the UARTn Interrupt request flags RIn or TIn is set which occurs when a byte of data has been received or transmitted by the UARTn interface To allow the program to branch to its respective interrupt vector address the global interrupt enable bit EAL and the UART Interrupt enable bit ESn must first be set When the interrupt is enabled the stack is not full and a byte...

Page 116: ...de The interrupt enable bits have no effect on the interrupt wake up function Programming Considerations By disabling the interrupt enable bits a requested interrupt can be prevented from being serviced however once an interrupt request flag is set it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the ap...

Page 117: ...e Special Function Registers table All of these I O ports can be used for both input and output operations the data for which is stored in Port Data Registers Ports P0 P3 can be setup using Port Mode Registers to operate in a series of different modes Ports 4 and 5 can only operate in the traditional 8051 type quasi bidirectional mode The Port P0 provides register controlled wake up function as we...

Page 118: ...P2M1 5 P2M1 4 P2M1 3 P2M1 2 P2M1 1 P2M1 0 P3 P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 P3M0 P3M0 7 P3M0 6 P3M0 5 P3M0 4 P3M0 3 P3M0 2 P3M0 1 P3M0 0 P3M1 P3M1 7 P3M1 6 P3M1 5 P3M1 4 P3M1 3 P3M1 2 P3M1 1 P3M1 0 P4 P4 7 P4 6 P4 5 P4 4 P4 3 P4 2 P4 1 P4 0 P5 P5 7 P5 6 P5 5 P5 4 P5 3 P5 2 P5 1 P5 0 SRCR SRCR 5 SRCR 4 SRCR 3 SRCR 2 SRCR 1 SRCR 0 Each Port has its own data register known as P0 P1 P2 P3 P4 ...

Page 119: ... R W POR 1 1 1 1 1 1 1 1 P5 Register SFR Address D9h Bit 7 6 5 4 3 2 1 0 Name P5 7 P5 6 P5 5 P5 4 P5 3 P5 2 P5 1 P5 0 R W R W R W R W R W R W R W R W R W POR 1 1 1 1 1 1 1 1 Bit 7 0 I O Port bit 7 bit 0 Input Output Data Control During reading and writing of data to these registers what actually happens is dependent upon whether the corresponding pin is setup as an output or input Register Write O...

Page 120: ...Control P0M0 Register SFR Address 9Eh Bit 7 6 5 4 3 2 1 0 Name P0M0 7 P0M0 6 P0M0 5 P0M0 4 P0M0 3 P0M0 2 P0M0 1 P0M0 0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 P0M1 Register SFR Address 9Fh Bit 7 6 5 4 3 2 1 0 Name P0M1 7 P0M1 6 P0M1 5 P0M1 4 P0M1 3 P0M1 2 P0M1 1 P0M1 0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Port 1 Mode Control P1M0 Register SFR Address A6h Bit 7 6 ...

Page 121: ...it 7 6 5 4 3 2 1 0 Name P3M0 7 P3M0 6 P3M0 5 P3M0 4 P3M0 3 P3M0 2 P3M0 1 P3M0 0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 P3M1 Register SFR Address B7h Bit 7 6 5 4 3 2 1 0 Name P3M1 7 P3M1 6 P3M1 5 P3M1 4 P3M1 3 P3M1 2 P3M1 1 P3M1 0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 These registers operate as pairs for example P0M0 and P0M1 to select the operating mode for each ...

Page 122: ...specially suitable for applications that can be woken up via external switches The P0 wake up pins can be selected individually to have this wake up feature using the P0WAKE register SRCR Register Slew Rate Control SRCR Register SFR Address A4h Bit 7 6 5 4 3 2 1 0 Label SRCR 5 SRCR 4 SRCR 3 SRCR 2 SRCR 1 SRCR 0 R W R W R W R W R W R W R W POR 0 0 0 0 0 0 Bit 7 6 Unimplemented read as 0 Bit 5 SRCR ...

Page 123: ...urned on whenever the I O port registers associated with the I O pins contain a high level When the I O port registers has a high level and the corresponding I O pins stay at high level as well the Weak pull high resistor will be turned on However if the I O port registers are high and the corresponding I O pins are pulled low by the external devices then the Weak pull high resistor will be disabl...

Page 124: ... input Input Data Q Port Register Data VCC Strong Port Pin Push pull Output Structure Open drain Output Ports 0 3 Only This I O structure is an open drain type structure with a Schmitt Trigger input Usually an external pull high resistor is needed for such applications Input Data Q Port Register Data Port Pin Open drain Output Structure Input Only Ports 0 3 Only This Input Only structure is a Schm...

Page 125: ...If any pins are setup to be used as A D input pins then it is important to ensure that the I O Port Mode registers setup the pins as inputs which are essentially high impedance inputs In this way the I O logic circuits will have a minimal influence on the A D input impedance When using these bit control instructions a read modify write operation takes place The microcontroller must first read in t...

Page 126: ...has a different structure and is also known as a Programmable Counter Array or PCA for short and has functions such as Compare Reload and Capture functions so called CRC as well a programmable clock output function All timers have a clock divider which provides additional range to the timers Various Timer control registers determine how each Timer is operated The clock sources for the Timers can c...

Page 127: ...only The registers THn and TLn are special function registers located in the Special Function Registers and is the place where the actual timer value is stored This register pair are each 8 bit wide and can be cascaded into 13 bit or 16 bit wide using mode options The value in the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the...

Page 128: ...e control bits Timer0 Timer1 Timer3 Register List Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IEN0 EAL WDT ET2 ES0 ET1 EX1 ET0 EX0 IEN1 EXEN2 SWDT ET3 ECMP EX6 EX5 EX4 EX3 IRCON EXF2 TF2 IEX6 IEX5 IEX4 IEX3 IEX2 TMOD GATE1 C T1 T1M1 T1M0 GATE0 C T0 T0M1 T0M0 TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 T3CON GATE3 C T3 T3M1 T3M0 TF3 TR3 TLn D7 D6 D5 D4 D3 D2 D1 D0 THn D15 D14 D13 D12 D11 D10 D9 D...

Page 129: ...Bit 7 6 5 4 3 2 1 0 Name D12 D11 D10 D9 D8 D7 D6 D5 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 TH0 TIMER0 Counter High Byte Register bit 12 bit 5 TL1 Register SFR Address 8Bh 16 bit Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 TL1 TIMER1 Counter Low Byte Register bit 7 bit 0 13 bit Bit 7 6 5 4 3 2 1 0 Name D4 ...

Page 130: ...Bit 7 6 5 4 3 2 1 0 Name D12 D11 D10 D9 D8 D7 D6 D5 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 TH1 TIMER1 Counter High Byte Register bit 12 bit 5 TL3 Register SFR Address A2h 16 bit Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 TL3 TIMER3 Counter Low Byte Register bit 7 bit 0 13 bit Bit 7 6 5 4 3 2 1 0 Name D4 ...

Page 131: ...0 0 0 0 Bit 7 GATE1 Timer 1 Gate Control 0 Disable 1 Enable This bit is used to enable the Timer 1 Gate function When the GATE1 bit is set high and Timer 1 is enabled to run using the TR1 bit and when the INT1 pin is input high then the Timer 1 Counter will increment one on every falling edge on the T1 input pin Bit 6 C T1 Timer 1 Counter Timer selection 0 Timer 1 Counter Bit 5 4 T1M1 T1M0 Timer 1...

Page 132: ... IE0 IT0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 TF1 Timer 1 interrupt request flag 0 No request 1 Interrupt request This bit will be cleared by hardware automatically Bit 6 TR1 Timer 1 Run control 0 Stop 1 Run Bit 5 TF0 Timer 0 interrupt request flag 0 No request 1 Interrupt request This bit will be cleared by hardware automatically Bit 4 TR0 Timer 0 Run control 0 Stop 1 Run...

Page 133: ... Timer 3 is enabled to run using the TR3 bit and when the INT3 pin is input high then the Timer 3 Counter will increment one on every falling edge on the T3 input pin Bit 6 C T3 Timer 3 Counter Timer selection 0 Timer 1 Counter Bit 5 4 T3M1 T3M0 Timer 3 mode selection 00 Mode 0 13 bit Timer Counter 01 Mode 1 16 bit Timer Counter 10 Mode 2 8 bit Auto Reload Timer Counter 11 Mode 3 Timer Stopped Bit...

Page 134: ... R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 T3PRE1 T3PRE0 Timer 3 Clock Frequency selection 00 fSYS 12 01 fSYS 6 10 fSYS 4 11 fSYS Bit 5 4 T2PRE1 T2PRE0 Timer 2 Clock Frequency selection 00 fSYS 12 01 fSYS 6 10 fSYS 4 11 fSYS Bit 3 2 T1PRE1 T1PRE0 Timer 1 Clock Frequency selection 00 fSYS 12 01 fSYS 6 10 fSYS 4 11 fSYS Bit 1 0 T0PRE1 T0PRE0 Timer 0 Clock Frequency selection 00...

Page 135: ...e 1 16 bit Counter Timer Mode Operation To select this mode bits TnM1 and TnM0 should be set to 01 respectively The 16 bits of data are stored in the TLn and THn registers The C Tn bit is used to select the timer or counter function The Counter Timer Run or Stop is controlled by TRn bit If the Counter function is selected the TRn and GATEn bits can be used to manage the external INTn input to coun...

Page 136: ...ge the external INTn input to count edge transitions or measure pulse widths The timer counter clock source is decided by the TnPRE0 and TnPRE1 registers in the TMPRE register When the values in the TLn register overflows the TLn value will be auto reloaded with the data in the THn register and an interrupt will take place if the interrupt is enabled Note that the value of THn register should be i...

Page 137: ...he Counter function is selected the TR0 and GATE0 bits can be used to manage the external INT0 input to count external edge transitions or to measure input pulse widths If the TL0 counter overflows an interrupt will be generated and the interrupt request flag TF0 will be set high The timer counter clock source is decided by the T0PRE0 and T0PRE1 bits in the TMPRE register In addition to TL0 the ot...

Page 138: ...le 3 Each module can be operated as a Compare and Capture function while Module 0 can also be operated as a Compare Reload Capture known as CRC and Programmable Clock Output functions The accompanying tables and diagram illustrate the PCA modules functional compare table timer I O pin list and basic operational block diagram Timer 2 with PCA Modules Operating Modes Summary Module Compare Capture R...

Page 139: ...CL CRCH Comparator Comparator T PRE 1 0 T2 T I 1 0 TH2 TL2 Module 1 CCL1 CCH1 Comparator Module 2 CCL2 CCH2 I O Cont ol CC0 P1 0 Comparator Module 3 CCL3 CCH3 CC1 P1 1 CC2 P1 2 CC3 P1 3 Latch Capt e Capt e Capt e Capt e Match Match Match Match Reload Ove flow TF Inte pt Req est T2EX EXEN EXF Inte pt Req est T ansition Detecto Reload Timer 2 with PCA Modules Block Diagram ...

Page 140: ...n To select this function bits T2I1 and T2I0 in the T2CON register should be set to 10 respectively The value in the Timer 2 registers TL2 and TH2 increases by one each time a falling edge occurs on the external timer pin T2 When the timer counter is overflowed an interrupt will take place and the interrupt request flag TF2 will be set to high The maximum count rate is 1 4 of the system clock freq...

Page 141: ...de 1 the Capture function is triggered by writing data to the CCLn or CRCL registers Once the Capture function is enabled and triggered the Timer 2 data in the TL2 and TH2 registers will be captured into the respective CCLn CCHn or CRCL CRCH registers Refer Capture modes for details In the Reload mode the timer counter registers TH2 and TL2 are located in the Special Function Registers and is the ...

Page 142: ...13 D12 D11 D10 D9 D8 T2CON I3FR I2FR T2R1 T2R0 T2CM T2I1 T2I0 T2CON1 T2OI T2OE CCEN COCAH3 COCAL3 COCAH2 COCAL2 COCAH1 COCAL1 COCAH0 COCAL0 CCEN Register SFR Address C1h Bit 7 6 5 4 3 2 1 0 Name COCAH3 COCAL3 COCAH2 COCAL2 COCAH1 COCAL1 COCAH0 COCAL0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 COCAH3 COCAL3 Compare Capture mode select for Module 3 CC3 register 00 Disable 01 Cap...

Page 143: ...e PCA Module 0 Capture mode input triggered edge Once the compare mode is enabled the PCA interrupt will replace the external interrupt When Timer 2 is selected as compare mode 0 the I3FR bit is recommended to be set high by firmware Bit 5 I2FR Active edge selection for external interrupt INT2 Described elsewhere Bit 4 3 T2R1 T2R0 Timer 2 reload mode selection 00 Reload function disabled 01 Reload...

Page 144: ...2OI Timer 2 output initial state control 0 T2 pin initial output Low 1 T2 pin initial output High The Timer 2 output initial state can be selected by the T2OI bit before enable the Timer 2 programmable clock output function Bit 2 T2OE Timer 2 output enable bit 0 Disable 1 Enable The Timer 2 output is enabled by setting the T2OE bit high When the Timer 2 output is disabled this pin can be used as t...

Page 145: ... for CC1 CC3 and Write to CRCL is for CC0 Capture Modes Block Diagram Capture On Edge Mode To select this mode bits COCAHn and COCALn in the CCEN register should be set to 01 respectively In this mode Modules 1 3 will capture the Timer 2 counter on the rising edge of an external signal applied on the CC1 CC3 pins Module 0 will capture the Timer 2 counter contents on a rising or falling edge applie...

Page 146: ...s control applications Compare Mode 0 In Mode 0 if the Timer 2 counter data is the same as the Compare registers the compare output will be set from low to high and the Timer 2 counter overflow will clear the respective output pins CCn to low In addition the Module 0 can select the output rising or falling edge interrupt trigger by the I3FR bit in the T2CON register The accompanying diagrams illus...

Page 147: ... Additional 4 channel PCA CRCH CRCL Comparator TH2 TL2 CC0 Compare Match Overflow 1 0 Interrupt Interrupt I3FR Compare Mode 0 Module 0 Figure below illustrates the operation of compare mode 0 CRC CCn Contents of Timer 2 Reload value CCn Output Compare interrupt Overflow interrupt Compare Mode 0 Timing Diagram ...

Page 148: ...pins CCn and the Timer 2 counter overflow will not affect the Compare output In addition the Module 0 can select the output rising or falling edge interrupt trigger by the I3FR bit in the T2CON register The accompanying diagrams illustrate the Basic application blocks CCHn CCLn Comparator TH2 TL2 CCn Compare Match Overflow Interrupt Interrupt Note n 1 3 I O Control Register Compare Mode 1 Module1 ...

Page 149: ...5F2260 HT85F2270 HT85F2280 Timer 2 with Additional 4 channel PCA Figure below illustrates the operation of compare mode 1 CRC or CCn Contents of Timer2 Reload value CCn Output Compare Match CCn Output Output register P1 I O Control register Compare Mode 1 Timing Diagram ...

Page 150: ...2CON register In Reload Mode 0 the Reload enable is controlled by the Timer 2 overflow which is an auto reload and a Timer 2 interrupt will take place In Reload Mode 1 a falling edge at the T2EX input pin will reload the data from CRCH CRCL registers to TH2 TL2 registers When the external reload interrupt control bit EXEN2 and the Timer 2 interrupt control bit ET2 are both set high a Timer 2 inter...

Page 151: ...ycle clock ranging from 61HZ to 4MHz when the system clock is selected as 16MHz To configure the Timer Counter 2 as a clock generator the T2I1 and T2I0 bits in the T2CON register must be set as 0 and 1 respectively to start the timer and the T2OE bit in the T2CON1 register must be set as well The clock out frequency depends on the system frequency and the reload value of Timer 2 capture registers ...

Page 152: ...uts Programmable Gain Amplifier Temperature Sensor Input Internal Voltage Reference Source External Reference Voltage Input Programmable Clock Speed A D Converter Interrupt All functions are controlled using dedicated ADC control registers for setup and dynamic control The following block diagram shows the overall structure of the converter together with its relative control bits A D Converter P4 ...

Page 153: ...bits Any unused bits will be read as zero A D Data Registers ADRFS ADRH ADRL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A D Converter Control Registers ADCR0 ADCR1 ADCR2 ADPGA To control the function and operation of the A D converter four control registers known as ADCR0 ADCR1 ADCR2 and ADPGA are provided These 8...

Page 154: ...s the power to the A D internal function This bit should be cleared to zero to enable the A D converter If the bit is set high then the A D converter will be switched off reducing the device power consumption As the A D converter will consume a limited amount of power even when not executing a conversion this may be an important consideration in power sensitive battery powered applications Bit 4 A...

Page 155: ... controls the internal temperature sensor function to the A D converter When the bit is set high the temperature sensor can be used by the A D converter Bit 5 Unimplemented read as 0 Bit 4 VREFAS ADC reference voltage select 0 VCCA3 pin 1 Externally supplied on VREF pin or internal voltage reference generator This bit is used to select the reference voltage for the A D converter If the bit is high...

Page 156: ...P4 7 A D input select 0 Logic I O 1 A D input AIN 7 Bit 6 ACE6 P4 6 A D input select 0 Logic I O 1 A D input AIN 6 Bit 5 ACE5 P4 5 A D input select 0 Logic I O 1 A D input AIN 5 Bit 4 ACE4 P4 4 A D input select 0 Logic I O 1 A D input AIN 4 Bit 3 ACE3 P4 3 A D input select 0 Logic I O 1 A D input AIN 3 Bit 2 ACE2 P4 2 A D input select 0 Logic I O 1 A D input AIN 2 Bit 1 ACE1 P4 1 A D input select ...

Page 157: ...lied from either the positive power supply pin VCCA3 internal voltage reference or from an external reference sources supplied on pin VREF The desired selection is made using the VREFAS and VREFIS bits The START bit in the ADCR0 register is used to start and reset the A D converter When the microcontroller sets this bit from low to high and then low again an analog to digital conversion cycle will...

Page 158: ... ADCK2 ADCK1 ADCK0 110 fSYS 64 ADCK2 ADCK1 ADCK0 111 1MHz 1μs 2μs 4μs 8μs 16μs 32μs 64μs Undefined 2MHz 500ns 1μs 2μs 4μs 8μs 16μs 32μs Undefined 4MHz 250ns 500ns 1μs 2μs 4μs 8μs 16μs Undefined 8MHz 125ns 250ns 500ns 1μs 2μs 4μs 8μs Undefined 12MHz 83ns 167ns 333ns 667ns 1 33μs 2 67μs 5 33μs Undefined 16MHz 62 5ns 125ns 250ns 500ns 1μs 2μs 4μs Undefined 32MHz 31 25ns 62 5ns 125ns 250ns 500ns 1μs 2...

Page 159: ... process The ADC temperature sensor input channel is selected by the ACS4 bit The TSEN bit in the ADCR1 register controls the temperature sensor enable disable function When the function is disabled the temperature sensor defaults to an unknown state and any A D conversion performed on the sensor will generate undefined data A D Reference Voltage Source The A D can obtain its reference voltage fro...

Page 160: ... ACE7 ACE0 bits in the ADCR2 register Step 5 If the interrupts are to be used the interrupt control registers must be correctly configured to ensure the A D converter interrupt function is active The master interrupt control bit EAL and the A D converter interrupt bit EADC must both be set high to do this Step 6 The analog to digital conversion process can now be initialised by setting the START b...

Page 161: ...involved in an analog to digital conversion process and its associated timing After an A D conversion process has been initiated by the application program the microcontroller internal hardware will begin to carry out the conversion during which time the program can continue with other functions The time taken for the A D conversion is 16 tADCK where tADCK is equal to the A D clock period A D Conv...

Page 162: ...power consumption A D Transfer Function As the converted data is 12 bit wide its full scale converted digitised value is equal to FFFH Since the full scale analog input value is equal to the VCCA3 or VREF voltage this gives a single bit analog input value of VCCA3 or VREF divided by 4096 1 LSB VCCA3 or VREF 4096 The A D Converter input voltage value can be calculated using the following equation A...

Page 163: ...RL controls the attenuation level reference voltage select and enable disable control DAH Register SFR Address B5h Bit 7 6 5 4 3 2 1 0 Name D11 D10 D9 D8 D7 D6 D5 D4 R W R W R W R W R W R W R W R W R W POR 1 0 0 0 0 0 0 0 Bit 7 0 D11 D4 DAC output data bit 11 4 DAL Register SFR Address B4h Bit 7 6 5 4 3 2 1 0 Name D3 D2 D1 D0 R W R W R W R W R W POR 0 0 0 0 Bit 7 4 D3 D0 DAC output data bit 3 0 Bi...

Page 164: ...6 010 D11 D11B D11B D11B D11B D11B D10 D9 D8 D7 D6 D5 011 D11 D11B D11B D11B D11B D10 D9 D8 D7 D6 D5 D4 100 D11 D11B D11B D11B D10 D9 D8 D7 D6 D5 D4 D3 101 D11 D11B D11B D10 D9 D8 D7 D6 D5 D4 D3 D2 110 D11 D11B D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 111 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Bit 4 2 Unimplemented read as 0 Bit 1 VREFDS DAC reference voltage select bit 0 VCCA2 external power supply pin 1 Ex...

Page 165: ...OL0 VOL2 bits in the DACTRL register providing an 8 level attenuation control These bits rotate the digital DAC value thus providing a divide or multiply by two functions for each shift left or right If the DAC circuit is not enabled any DAH DAL values will be invalid The VREFDS and VREFIS bits select if the DAC reference is to be sourced from VCCA2 VREF pin or the internal reference voltage Bits ...

Page 166: ... Voltage Reference Select VREFIS VREFDS Reference Source 0 0 VCCA2 pin 0 1 Externally supplied on VREF pin 1 0 VCCA2 pin 1 1 Internal Voltage Reference Generator Programming Considerations Note that data written to the two DAC registers must be implemented in a specific way Any data written into the DAH register will load both the data into the DAL and DAH registers simultaneously and influence th...

Page 167: ...r will be disabled thus conserving power Internal Voltage Reference Enable Disable Control ADC DAC Voltage Reference Disabled Disabled Disabled Enabled Disabled Enabled Disabled Enabled Enabled Enabled Enabled Enabled The internal Voltage Reference Generator output is pin VREF and can be used as a reference source for other circuits if loaded lightly A suitable capacitor should be connected to thi...

Page 168: ...tage Reference DAC Voltage Reference VCCA2 0 0 1 1 A D Enable D A Enable Enable Disable Control OR Voltage Reference Generator Block Diagram The A D converter and DAC reference voltage is selected by the VREFIS VREFAS and VREFDS control bits When the VREFIS bit is enabled the internal voltage reference will be routed to pin VREF and can be selected for use by the A D converter or DAC using the VRE...

Page 169: ...rator functions include output polarity hysteresis functions and power down control Any pull high resistors connected to the shared comparator input pins will be automatically disconnected when the comparator is enabled As the comparator inputs approach their switching level some spurious output signals may be generated on the comparator output due to the slow rising or falling nature of the input...

Page 170: ...rs settings for the Comparator 0 and Comparator 1 while the CPHCR register is used to manage the hysteresis selection for these two comparators In addition the CPICR register control the comparators interrupt settings The accompanying register table illustrates the control registers list Comparator Registers List Register Name Bit 7 6 5 4 3 2 1 0 CP0CR CP0ON CP0POL CP0OUT CP0OS CP0RSTL CP0RST CP1C...

Page 171: ... condition of the comparator If the bit is high the comparator CP0OUT bit will be inverted Bit 4 CP0OUT Comparator 0 output bit CP0POL 0 0 CP0 CP0 1 CP0 CP0 CP0POL 1 0 CP0 CP0 1 CP0 CP0 This bit stores the comparator 0 output bit The polarity of the bit is determined by the voltages on the comparator 0 inputs and by the condition of the CP0POL bit Bit 3 CP0OS Comparator 0 output path select 0 C0OU...

Page 172: ... is the comparator 1 polarity bit If the bit is zero then the CP1OUT bit will reflect the non inverted output condition of the comparator If the bit is high the comparator CP1OUT bit will be inverted Bit 4 CP1OUT Comparator 1 output bit CP1POL 0 0 CP1 CP1 1 CP1 CP1 CP1POL 1 0 CP1 CP1 1 CP1 CP1 This bit stores the comparator 1 output bit The polarity of the bit is determined by the voltages on the ...

Page 173: ... 0 0 0 Bit 7 6 CP1HP1 CP1HP0 Comparator 1 Positive Hysteresis voltage level Control bits 00 Disabled 01 3mV 10 6mV 11 12mV Bit 5 4 CP1HN1 CP1HN0 Comparator 1 Negative Hysteresis voltage level Control bits 00 Disabled 01 3mV 10 6mV 11 12mV Bit 3 2 CP0HP1 CP0HP0 Comparator 0 Positive Hysteresis voltage level Control bits 00 Disabled 01 3mV 10 6mV 11 12mV Bit 1 0 CP0HN1 CP0HN0 Comparator 0 Negative H...

Page 174: ...parator transition output from high to low will cause an interrupt 10 Comparator transition output from low to high will generate an interrupt 11 Comparator transition output from low to high or high to low will generate an interrupt Bit 3 CP0IF Comparator 0 Output Transition Interrupt Request Flag 0 Not request 1 Interrupt request Note that this flag should be cleared using the application progra...

Page 175: ...ode Each of the comparators has the compare output transition settings to decide the interrupt request conditions There are three options compare output rising falling or both rising and falling conditions decided by the CPnP1 and CPnP0 bits in the CPICR register Comparator Reset Function Comparator 0 has the ability to reset the device The reset function of Comparator 0 can be enabled or disabled...

Page 176: ... together on the same bus their outputs are both open drain types For this reason it is necessary that external pull high resistors are connected to these outputs Note that no chip select line exists as each device on the I2 C bus is identified by a unique address which will be transmitted and received on the I2 C bus When two devices communicate with each other on the bidirectional I2 C bus one i...

Page 177: ...egister Name Bit 7 6 5 4 3 2 1 0 I2CCON ENS1 STA STO SI AA I2CLK I2CLK 7 I2CLK 6 I2CLK 5 I2CLK 4 I2CLK 3 I2CLK 2 I2CLK 1 I2CLK 0 I2CSTA IICS7 IICS6 IICS5 IICS4 IICS3 I2CDAT D7 D6 D5 D4 D3 D2 D1 D0 I2CADR IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 GC I2CCON Register SFR Address D8h Bit 7 6 5 4 3 2 1 0 Name ENS1 STA STO SI AA R W R W R W R W R W R W POR 0 0 0 0 0 Bit 7 Unimplemented read as 0 Bit 6 E...

Page 178: ...A 1 an acknowledge will be returned under the following conditions The own slave address has been received The general call address has been received while the GC bit in the I2CADR register was set A data byte has been received while the I2 C was in the master receiver mode A data byte has been received while the I2 C was in the slave receiver mode When AA 0 a not acknowledge will be returned unde...

Page 179: ...CA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 GC R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 1 IICA6 IICA0 I2 C slave address IICA6 IICA0 is the I2 C slave address bit 6 bit 0 When a master device which is connected to the I2 C bus sends out an address which matches the slave address in the I2CADR register the slave device will be selected Bit 0 GC General Call Address Acknowledge cont...

Page 180: ...face Data Bus I2CADR Address Register Address Comparator I2CDAT Shift Register Arbitration And Synchronization Logic Serial Clock Generator I2CCON Control Register I2CSTA Status Register I2 C Interrupt Timer1 Overflow Input Filter Output SCL N Open drain Open drain ACK Input Filter Output SDA N I2 C Block Diagram ...

Page 181: ...s of the I2CSTA register to determine the interrupt source originating condition The SI bit is set by hardware when one of 25 out of 26 possible I2 C states is entered The only state that does not set the SI bit is the state F8H which indicates that no relevant state information is available The SI bit must be cleared by the application program During a data transfer note that after the 7 bit slav...

Page 182: ... the completion of a data byte transfer When a slave address is matched the device must be placed in either the transmit mode and then data written to the I2CDAT register or in the receive mode where it must implement a dummy read from the I2CDAT register to release the SCL line Refer to the I2 C Status Code section for details I2 C Bus Read Write Signal The Read Write bit so called as R W bit is ...

Page 183: ...first write the data to be transmitted into the I2CDAT register If setup as a receiver the slave device must read the transmitted data from the I2CDAT register The AA bit in the I2CCON register bit indicates the type of acknowledge returned during the acknowledge cycle on the SCL pin If this bit is cleared to zero a not acknowledge high level on SDA is returned during the acknowledge cycle If the ...

Page 184: ...eived Load data byte 0 0 0 X Data byte will be transmitted ACK will be received No action 1 0 0 X Repeated START will be transmitted No action 0 1 0 X STOP condition will be transmitted the STO flag will be reset No action 1 1 0 X STOP condition followed by a START condition will be transmitted the STO flag will be reset 20H SLA W has been transmitted not ACK has been received Load data byte 0 0 0...

Page 185: ... has been transmitted ACK has been received No action 0 0 0 0 Data byte will be received not ACK will be returned No action 0 0 0 1 Data byte will be received ACK will be returned 48H SLA R has been transmitted not ACK has been received No action 1 0 0 X Repeated START condition will be transmitted No action 0 1 0 X STOP condition will be transmitted the STO flag will be reset No action 1 1 0 X ST...

Page 186: ...sly addressed with own SLA DATA byte has been received not ACK returned Read data byte 0 0 0 0 Switched to not addressed slave mode no recognition of own slave address or general call address Read data byte 0 0 0 1 Switched to not addressed slave mode own slave address or general call address will be recognized Read data byte 1 0 0 0 Switched to not addressed slave mode no recognition of own slave...

Page 187: ... STO SI AA A8H Own SLA R has been received ACK has been returned Load data byte X 0 0 0 Last data byte will be transmitted and ACK will be received Load data byte X 0 0 1 Data byte will be transmitted ACK will be received B0H Arbitration lost in SLA R W as master own SLA R has been received ACK has been returned Load data byte X 0 0 0 Last data byte will be transmitted and ACK will be received Loa...

Page 188: ...tion of own slave address or general call address START condition will be transmitted when the bus becomes free No action 1 0 0 1 Switched to not addressed slave mode own slave address or general call address will be recognized START condition will be transmitted when the bus becomes free I2 C Status Miscellaneous States Status Code Status of the I2 C Application software response Next action take...

Page 189: ...onous serial data link The SPI interface is disabled or enabled using the SPEN bit in the SPCON register which configures the functionally shared pins as SPI pins and disables their logic I O function The SPI interface is a slave master type where the device can be either master or slave decided by the MSTR bit in the SPCON register It is a four line interface with pin names MOSI MISO SCK and SSN ...

Page 190: ...S bit MSTR bit WCOL SPIF SSERR MODF Stat s Flags MISO pin MOSI pin fs s SPR0 SPR1 SPR MSTR bit SPI Interface Block Diagram SPI Features The SPI function in the devices have the following features Full duplex synchronous data transfer Three wire synchronous transfers Dual Master and Slave modes Seven SPI Master baud rates Slave Clock rate up to fSYS 8 Serial clock with programmable polarity and pha...

Page 191: ...s received from the SPI bus the device can read the data from the SPDAT register Any transmission or reception of data from the SPI bus must be made via the SPDAT register SPDAT Register SFR Address E3h Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 There are also two control registers for the SPI interface SPCON and SPSTA Register SPCON is...

Page 192: ...e will be disabled and all the functionally shared pins will have a logical I O function Bit 5 SSDIS SSN pin disable control 0 Enable 1 Disable SSN pin floating When this bit is cleared to zero the SSN input is enabled in both Master and Slave modes When set high the SSN input is disabled in both Master and Slave modes In the Slave mode this bit has no effect if CPHA 0 When the bit is high no MODF...

Page 193: ...n to the SPDAT register during a data transfer operation A SPI interrupt will occur if the SPI interrupt function is enabled This writing operation will be ignored if data is being transferred It must be cleared using the application program Bit 5 SSERR Synchronous Serial Slave Error Flag 0 No error 1 Error This bit is set by hardware when the SSN pin input is selected to disable the Slave device ...

Page 194: ...automatically but must be cleared using the application program In the Slave Mode when the clock signal from the master has been received any data in the SPDAT register will be transmitted and any data on the MISO pin will be shifted into the SPDAT register The master should output an SSN signal to enable the slave device before a clock signal is provided The slave data to be transferred should be...

Page 195: ...Rev 1 00 195 of 225 January 15 2015 Standard 8051 8 Bit Flash MCU HT85F2260 HT85F2270 HT85F2280 Serial Interface SPI SPI Slave Mode Timing CPHA 0 SPI Slave Mode Timing CPHA 1 ...

Page 196: ...Rev 1 00 196 of 225 January 15 2015 Standard 8051 8 Bit Flash MCU HT85F2260 HT85F2270 HT85F2280 Serial Interface SPI SPI Transfer Control Flowchart ...

Page 197: ...es and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission The UART functions possesses their own internal interrupt which can be used to indicate when a data reception operation has occurred or when a data transmission operation has terminated UART0 Features The integrated UART0 function contains the following features Full duplex s...

Page 198: ...n LSB first to the Receiver Shift Register at a rate controlled by the Baud Rate Generator When the shift register is full the data will then be transferred from the shift register to the internal received register where it is buffered and can be manipulated by the application program Only the received register is mapped onto the MCU Data Memory the Receiver Shift Register is not mapped and is the...

Page 199: ...ial interface the UART0 has two external pins known as TXD0 and RXD0 The UART0 provides four operating modes which can be categorised into two transmitter receiver methods so called Synchronous and Asynchronous In Synchronous communication the MCU must be the master device and the TXD0 pin is used to provide the shift clock while the RXD0 pin is used as the data transmitter receiver pin In Asynchr...

Page 200: ...ved on the serial interface is managed through the S0BUF data register The SMOD bit in the PCON register is used to double the baud rate clock UART0 Register List Register Name Bit 7 6 5 4 3 2 1 0 S0CON SM0 SM1 SM20 REN0 TB80 RB80 TI0 RI0 S0RELL S0REL 7 S0REL 6 S0REL 5 S0REL 4 S0REL 3 S0REL 2 S0REL 1 S0REL 0 S0RELH S0REL 9 S0REL 8 S0BUF D7 D6 D5 D4 D3 D2 D1 D0 SPPRE S1PRE1 S1PRE0 S0PRE1 S0PRE0 SBR...

Page 201: ...e 3 9 bit UART Variable Asynchronous Note that the SP0CLK is described in the UART0 Baud Rate Setup section Bit 5 SM20 Multiprocessor communication enable control 0 Disable 1 Enable Refer to the UART0 Multiprocessor Communication section for details Bit 4 REN0 UART0 serial data reception enable control 0 Disable 1 Enable Bit 3 TB80 Ninth Transmit bit assignment 0 Low 1 High This bit is only availa...

Page 202: ...3 2 1 0 Name S0REL 9 S0REL 8 R W R W R W POR 1 1 The UART0 Reload registers S0RELL and S0RELH are used to setup the UART0 baud rate generation The UART0 baud rate setup range is 10 bit wide consisting of 8 bits in S0RELL and 2 bits in S0RELH SPPRE Register UART Clock Prescaler Register SFR Address A5h Bit 7 6 5 4 3 2 1 0 Name S1PRE1 S1PRE0 S0PRE1 S0PRE0 R W R W R W R W R W POR 1 1 1 1 Bit 7 4 Unim...

Page 203: ...SRELL and SRELH registers combine to form a 10 bit reload register pair for the Baud rate generator Bit 6 BD1 UART1 internal Baud rate generator enable control only available on HT85F2280 2270 0 Disable 1 Enable Bit 5 0 Unimplemented read as 0 PCON Register SFR Address 87h Bit 7 6 5 4 3 2 1 0 Name SMOD GF0 PD IDL R W R W R R W R W R W POR 0 1 0 0 0 Bit 7 SMOD UART0 double baud rate select 0 Not do...

Page 204: ...K 32 or SP0CLK 64 Asynchronous 1 Start 1 Stop Mode 3 9 bit UART Variable Asynchronous 1 Start 1 Stop Mode 0 Mode 0 is an integrated half duplex synchronous serial communication interface The 8 bits of data are communicated via the RXD0 pin while the TXD0 pin provides the shift clock for this communication The data will then be transferred to the Transmit Shift Register from where it will be shifte...

Page 205: ...he SBRCON register to be either sourced from the Timer1 overflow or to be setup by the S0RELL S0RELH registers In addition the Baud rate can be doubled using the SMOD bit in the PCON register Data transmission is started by writing to the S0BUF register The TXD0 pin outputs the serial data The first bit transmitted is a start bit always 0 then 8 bits of data after which a stop bit always 1 is tran...

Page 206: ...value of SP0CLK 32 or SP0CLK 64 depending on the setting of the SMOD bit in the PCON register Data transmission is started by writing to the S0BUF register The TXD0 pin outputs the serial data The first bit transmitted is a start bit always 0 then 9 bits of data where the 9th bit is taken from the TB80 bit of the S0CON register after which a stop bit always 1 is transmitted Data to be received by ...

Page 207: ...s selected by the BD bit in the SBRCON register to be either sourced from the Timer1 overflow or to be setup by the S0RELL S0RELH registers In addition the Baud rate can be doubled using the SMOD bit in the PCON register Data transmission is started by writing to the S0BUF register The TXD0 pin outputs the serial data The first bit transmitted is a start bit always 0 then 9 bits of data where the ...

Page 208: ... In this way there are reduced program overheads to distinguish the target slave MCU UART0 Baud Rate Setup The UART0 operating Modes1 and 3 have a variable baud rate setup using the UART0 Baud rate generator The clock source can be selected to be either the Timer 1 overflow or the system clock decided by the BD bit in the SBRCON register The baud rate generator can be controlled by the S0RELH and ...

Page 209: ...e Shift Register Input Latch S1BUF TXD1 MCU Data Bus UART1 Block Diagram UART1 External Pin Interfacing To communicate with an external serial interface the internal UART1 each has two external pins known as TXD1 and RXD1 The UART1 provides two operating modes both of which use Asynchronous communication The TXD1 pin is used to transmit data while the RXD1 pin is used as the data reception pin The...

Page 210: ...aud rate The actual data to be transmitted and received on the serial interface is managed through the S1BUF data register UART1 Register List Register Name Bit 7 6 5 4 3 2 1 0 S1CON SM SM21 REN1 TB81 RB81 TI1 RI1 S1RELL S1REL 7 S1REL 6 S1REL 5 S1REL 4 S1REL 3 S1REL 2 S1REL 1 S1REL 0 S1RELH S1REL 9 S1REL 8 S1BUF D7 D6 D5 D4 D3 D2 D1 D0 SPPRE S1PRE1 S1PRE0 S0PRE1 S0PRE0 S1BUF Register UART1 Data re...

Page 211: ...mmunication enable control 0 Disable 1 Enable Refer to the UART1 Multiprocessor Communication section for details Bit 4 REN1 UART1 serial data reception enable control 0 Disable 1 Enable Bit 3 TB81 Ninth Transmit bit assignment 0 Low 1 High This bit is only available in Mode A It is not effective in Mode B The bit is assigned using the application program Bit 2 RB81 Ninth Receive bit assignment 0 ...

Page 212: ...3 2 1 0 Name S1REL 9 S1REL 8 R W R W R W POR 1 1 The UART1 Reload registers S1RELL and S1RELH are used to setup the UART1 baud rate generation The UART1 baud rate setup range is 10 bit wide consisting of 8 bits in S1RELL and 2 bits in S1RELH SPPRE Register UART Clock Prescaler Register SFR Address A5h Bit 7 6 5 4 3 2 1 0 Name S1PRE1 S1PRE0 S0PRE1 S0PRE0 R W R W R W R W R W POR 1 1 1 1 Bit 7 4 Unim...

Page 213: ... provides the data transmit for this communication The data will then be transferred to the Transmit Shift Register from where it will be shifted out onto the TXD1 pin by the UART1 Baud rate generator The internal Baud rate generator is enabled disabled by the BD1 bit of the SBRCON register The S1RELL S1RELH registers must be used to setup the Baud rate generator Data transmission is started by wr...

Page 214: ...he SBRCON register The S1RELL S1RELH registers must be used to setup the Baud rate generator Data transmission is started by writing data to the S1BUF register The TXD1 pin outputs data The first bit transmitted is a start bit always 0 then 8 bits of data after which a stop bit always 1 is transmitted Data to be received by the UART1 is accepted on the external RXD1 pin When reception starts UART1...

Page 215: ...d byte with their network address If there is a match the addressed slave clears its SM21 flag and the rest of the message is transmitted from the master with the 9th bit set to low The other slaves keep their SM21 set high so that they ignore the rest of the message sent by the master In this way there are reduced program overheads to distinguish the target slave MCU UART1 Baud Rate Setup The UAR...

Page 216: ...te operand data 16 16 bit constant included as bytes 2 and 3 of instruction immediate operand bit One of 128 software flags located in internal RAM or any flag of bit addressable Special Function Registers including I O pins and status word A Accumulator Notes on Program Addressing Modes Symbol Description addr16 Destination address for LCALL or LJMP can be anywhere within the 64 Kbyte page of pro...

Page 217: ...ulator with carry flag 0X34 2 2 SUBB A Rn Subtract register from Accumulator with borrow 0X98 0X9F 1 1 SUBB A direct Subtract directly addressed data from Accumulator with borrow 0X95 2 2 SUBB A Ri Subtract indirectly addressed data from Accumulator with borrow 0X96 0X97 1 2 SUBB A data Subtract immediate data from Accumulator with borrow 0X94 2 2 INC A Increment Accumulator 0X04 1 1 INC Rn Increm...

Page 218: ...L A data OR immediate data to Accumulator 0X44 2 2 ORL direct A OR Accumulator to directly addressed location 0X42 2 3 ORL direct data OR immediate data to directly addressed location 0X43 3 4 XRL A Rn Exclusive OR register to Accumulator 0X68 0X6F 1 1 XRL A direct Exclusive OR directly addressed data to Accumulator 0X65 2 2 XRL A Ri Exclusive OR indirectly addressed data to Accumulator 0X66 0X67 ...

Page 219: ...ssed location 0X75 3 3 MOV Ri A Move Accumulator to indirectly addressed location 0XF6 0XF7 1 1 MOV Ri direct Move directly addressed data to indirectly addressed location 0XA6 0XA7 2 2 MOV Ri data Move immediate data to indirectly addressed location 0X76 0X77 2 2 MOV DPTR data16 Load data pointer with a 16 bit immediate 0X90 3 3 MOVC A A DPTR Load Accumulator with a code byte relative to DPTR 0X9...

Page 220: ...rel Jump if directly addressed bit is set 0X20 3 4 5 1 JNB bit rel Jump if directly addressed bit is not set 0X30 3 4 5 1 JBC bit direct rel Jump if directly addressed bit is set and clear bit 0X10 3 4 5 1 CJNE A direct rel Compare directly addressed data to Accumulator and jump if not equal 0XB5 3 4 5 1 CJNE A data rel Compare immediate data to Accumulator and jump if not equal 0XB4 3 4 5 1 CJNE ...

Page 221: ...or internal RAM modify it and rewrite it back are called Read Modify Write instructions When the destination is an I O port P0 P3 or a Port bit these instructions read the output latch rather than the pin Below table is RMW instruction set Mnemonic Description Code Bytes Cycles ANL direct A AND accumulator to direct 0x52 2 3 ANL direct data AND immediate data to direct 0x53 3 4 ORL direct A OR acc...

Page 222: ...ation may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package information Additional supplementary information with regard to packaging is listed below Click on the relevant section to be transferred to the relevant website page Further Package Information include Outline Dimensions Product Tape and Reel Specifications Packing Mete...

Page 223: ...nsions in inch Min Nom Max A 0 354 BSC B 0 276 BSC C 0 354 BSC D 0 276 BSC E 0 020 BSC F 0 007 0 009 0 011 G 0 053 0 055 0 057 H 0 063 I 0 002 0 006 J 0 018 0 024 0 030 K 0 004 0 008 α 0 7 Symbol Dimensions in mm Min Nom Max A 9 00 BSC B 7 00 BSC C 9 00 BSC D 7 00 BSC E 0 50 BSC F 0 17 0 22 0 27 G 1 35 1 40 1 45 H 1 60 I 0 05 0 15 J 0 45 0 60 0 75 K 0 09 0 20 α 0 7 ...

Page 224: ...imensions in inch Min Nom Max A 0 354 BSC B 0 276 BSC C 0 354 BSC D 0 276 BSC E 0 016 BSC F 0 005 0 007 0 009 G 0 053 0 055 0 057 H 0 063 I 0 002 0 006 J 0 018 0 024 0 030 K 0 004 0 008 α 0 7 Symbol Dimensions in mm Min Nom Max A 9 0 BSC B 7 0 BSC C 9 0 BSC D 7 0 BSC E 0 4 BSC F 0 13 0 18 0 23 G 1 35 1 40 1 45 H 1 60 I 0 05 0 15 J 0 45 0 60 0 75 K 0 09 0 20 α 0 7 ...

Page 225: ...mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise Holtek s products are not authorized for use as critical components in life support devices or...

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