A
A
B
B
C
C
D
D
E
E
4
4
3
3
2
2
1
1
LCLK
50MHz
Osc.
Power Regulators
JTAG
PEX 8311-AA66BCF
337 BGA 21 X 21 mm
+2.5 V
+1.5 V
Table Of Contents
Block Diagram
1: Cover Page
2: PEX8311 PCI Express Bus
3: PLX8311 Local Bus
4: CPLD JTAG/6130 Inputs
5: HI-6130
7: PEX8311 NC Balls
PCI Express X1
Card-Edge Connector
AT25640A
SPI EEPROM
(PCIE Config.)
32bit, 50 MHz PLX Local Bus
Holt HI-6130
MIL-STD 1553
BC, RT, MT
Terminals
93C56B
u-Wire EEPROM
(Local Bus Config.)
XFER
XFER
6: CPLD - POWER
3.3V
RESET
9 PIN DF CONN.
12V 3.3V
Lattice LCMX1200C3FTN245I
17 x 17 mm
Address decoder
Chip Selects
RD WR Strobes
6130 RD WR Access LED indicators
Status and DIP SW inputs
Date
Changes
9/19/2013
Rev A
12V
12V to 5V
DC-DC
3V3
HI-6130, PEX8311
Title
Size
Document Number
R e v
Date:
Sheet
o f
A
HI-PCIe_6130
Holt Integrated Circuits
23351 Madero, Mission Viejo, CA 92691
B
1
7
Thursday, September 19, 2013
www.holtic.com
Title
Size
Document Number
R e v
Date:
Sheet
o f
A
HI-PCIe_6130
Holt Integrated Circuits
23351 Madero, Mission Viejo, CA 92691
B
1
7
Thursday, September 19, 2013
www.holtic.com
Title
Size
Document Number
R e v
Date:
Sheet
o f
A
HI-PCIe_6130
Holt Integrated Circuits
23351 Madero, Mission Viejo, CA 92691
B
1
7
Thursday, September 19, 2013
www.holtic.com
