AN-6130PCIe
HOLT INTEGRATED CIRCUITS
12
HI-6130 Functional Block Diagram
RT1
Message
Processor
BC
Message
Processor
MT
Message
Processor
RT2
Message
Processor
Bus B
Manchester
Encoder
Bus B
Manchester
Decoder
Bus A
Manchester
Encoder
Bus A
Manchester
Decoder
Reset &
Initialization
Logic
Memory
and
Register
Access
Control
Address
Data
Control
Discrete
Signal
Inputs
Configuration
Option
Logic
Test
Logic
BUS
BUSB
BUSB
TXINHB
TXINHA
VCCP
MCLK
TTCLK
INTERNAL
CLOCKS
GND
VCC
LOGIC POWER
TRANSCEIVER
POWER
TEST
MODE
RT2SSF
ACKIRQ
RT1SSF
MR
RT2A4 - 0
AUTOEN
RT2AP
EECOPY
BENDI
RAMEDC
RT1LOCK
MTTCLK
RT1A4 - 0
RT1AP
MTSTOFF
RT2LOCK
RT1ENA
RT2ENA
BCENA
MTENA
Host Bus
Interface
HI-6130
Only
IRQ
MTPKRDY
READY
ACTIVE
CE
R /
or
W
W E
STR
OE
or
A0 / LB
WAIT or WAIT
D15: 0
A15: 1
BTYPE
BWID
WPOL
RT1MC8
RT2MC8
Discrete
Signal
Outputs
Host
Interface
SPI
HI-6131
Only
SCK
SI
SO
CE
Address
Data
Control
A
ddr
es
s
Dat
a
Cont
ro
l
Static RAM
and
Registers
A
ddr
ess
Dat
a
Cont
ro
l
Serial
Peripheral
Interface
(SPI) to
EEPROM
OPTIONAL
SERIAL EEPROM
(AUTO-CONFIG)
E
CS
ESC
K
MO
SI
MI
SO
A
ddr
es
s
Dat
a
Cont
ro
l
Tx
1553
W
or
ds
Rx
1553
W
or
ds
A
ddr
es
s&
Cont
ro
l
Wo
rd
s
BCTRI G
BUS
BUSA
BUSA
H
I-
6130 O
nl
y
H
I-
6131 O
nl
y
