Hitachi SH7760 Solution Engine2 Overview Download

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5.5

Sound Generator

5.5.1

Block Description

Figure 5.8 shows the sound generator control block. As shown in Figure 5.8, this control block contains an

SH7760 internal serial sound interface (SSI) and an audio CODEC (UDA1342TS from Phillips) so that sound can

be output to headphones connected to an output mini-jack (CN9) or it can be input to earphones connected to an

I/O mini-jack (CN10). In addition, headphone output takes place with the quality of stereo output while earphone

I/O takes place with the quality of monaural I/O that uses only the Rch.

This control block is connected to an electronic volume so that sound output volume can be controlled via the

generator. The electronic volume is controlled by the power supply controller. For details, refer to 6. “Power

Supply Controller.” In addition, Solution Engine2 has the following characteristics for microphone input and

headphone output:

- Microphone input

Impedance: 2.2KO

Sensitivity: -51dB/Pa

- Headphone output

Impedance: 32O

For more details, refer to the pertinent SH7760 Hardware Manual and Phillips UDA1342TS Manual.

Phillips Homepage: http://www.semiuconductors.phillips.com

Figure 5.8 Sound Generator Control Block

SH7760

Audio CODEC

(UDA1342TS)

DATAO

BCK

DATAI

SYSCLK

L3CLOCK

L3DATA

IIS Ch0

SDATA

SCK

CLK

22.5792MHz

OSC4

Rch output
Lch output

Rch input

Amplifier

Electronic

volume

Power supply controller

(H8/3048F-ONE)

Rch

Lch

Sound
output

mini-jack

(CN9)

Sound I/O

mini-jack

(CN10)

SCL

SDA

I2C Ch0

IIS Ch1

SDATA

SCK

CLK

Summary of Contents for SH7760 Solution Engine2

Page 1: ...SH7760 Solution Engine2 Overview MS7760CP01P 1st Edition Hitachi ULSI Systems Co Ltd MS7760CP01P M ...

Page 2: ...sible for damage due to the use of information product or circuit or infringement of property rights or other rights 3 This manual does not grant users the property rights and other rights of the third party or Hitachi ULSI Systems 4 No part of this manual may be transcribed or duplicated without the written permission of Hitachi ULSI Systems 5 The appearance of the product shown in this manual ma...

Page 3: ......

Page 4: ...sing Solution Engine2 Solution Engine2 Components Confirm that the following components are all contained after unpacking Product model MS7760CP01P Solution Engine2 main unit CPU board LCD board debug board and I O board AC adapter RS 232C cable CD ROM Software Solution Engine2 User s Manual This Manual Big endian monitor EPROM Software License Agreement User Registration Card ...

Page 5: ...id a risk of electric shock or fire Don t fall objects line or solder scrap onto Solution Engine2 If an object is dropped into it disconnect the AC adapter immediately from the receptacle turn off Solution Emgine2 and remove the object from the inside of the board to avoid a risk of electric shock or fire Use a dedicated AC adapter that comes standard with Solution Engine2 to avoid a risk of elect...

Page 6: ...jury if skin touches it for a long time Don t use or store Solution Engine2 in a place subject to direct sunlight or near the heater to prevent Solution Engine2 from being deformed due to heat Don t store Solution Engine2 in a dusty or humid place Turn off the power before connecting cables or equipment When this caution is ignored a fault may occur with Solution Engine2 When connecting the AC ada...

Page 7: ... period of free guarantee System malfunctions due to natural disasters System modification by users System malfunction due to incorrect use Solution Engin2 is specifically designed to serve various evaluation purposes prior to product development Don t incorporate it into the product itself We do not guarantee the performance of Solution Engine2 when used inside a product Others The product names ...

Page 8: ...arance 10 1 4 Solution Engine2 Specification 14 2 Installation 16 2 1 Host System Connection 16 2 2 AC Adapter Connection 18 2 3 Turning ON or OFF Solution Engine2 19 2 4 Using the Debug Board 20 3 Description of Switches 23 3 1 CPU Board Switch 23 3 2 LCD Board Switch 25 4 Memory Map 26 4 1 Memory Map for T Engine Only 26 4 2 Memory Map during Debug Board Connection 27 ...

Page 9: ...mmunication between the SH7760 and Power Supply Controller 49 6 3 RTC Real time Clock Function 55 6 4 Touch Panel Function 65 6 5 Key Switch Control 85 6 6 Power Supply Control 93 6 7 LED Control 95 6 8 LCD Front Light Control 96 6 9 Reset Control 97 6 10 Infrared Remote Control 98 6 11 Serial EEPROM Control 104 6 12 Electronic Volume Control 106 6 13 Initial Values in thePower Supply Control Regi...

Page 10: ...on Slot Signals 112 9 Daughter Board Design Guide 113 9 1 Daughter Board Dimensions 113 9 2 Daughter Board Power Supply 113 9 3 Daughter Board Stack 114 9 4 Daughter Board WAIT Output 114 9 5 Extension Slot AC Timing 115 10 Monitor Program Usage 117 10 1 Monitor Program Usage 117 10 2 List of Monitor Program Fubctions 126 10 3 Command Description 127 ...

Page 11: ...tor etc so that application systems can be developed taking advantage of them 4 This board contains two SH7760 buses address bus and data bus and one extension slot subject to control signal output so that users can connect user specific hardware 1 2 Solution Engine2 Configuration Figure 1 1 shows a Solution Engine2 system configuration and Figure 1 2 a Solution Engine2 block diagram Besides Solut...

Page 12: ...d USB IIS CPG UART 2Ch PCMCIA BSC 3 3V 1 5V CLK Card 5V SIM 5 6V IIC INTC LCD board interfce SIM H HP MIC LCD1 LCD2 Serial AC adapter Sound Generator chip UDA1342TS H8 3048B RTC SROM Supply voltage generation Power supply control Address decoder LCDC Flash Memory Bus Buffer Extension bus interface USBH ...

Page 13: ...four boards CPU LCD debug and I O Figure 1 3 is an external view of the Solution Engine2 Figures 1 4 to 1 7 show the appearances of the respective boards CPU LCD debug and I O boards Figure 1 3 Solution Engine External View LCD Board CPU Board I O Board Debug Board ...

Page 14: ...ontrast control volume LCD interface connector1 LCD interface connector2 LCD interface connector3 CPU board interface connector2 CPU board interface connector1 Rear view LCD Front view Infrared remote control reception Push button switch3 Cursor switch1 Push button switch2 ...

Page 15: ...nector I O board interface connector1 SIM card connector I O board interface connector2 Rear view Earphones microphones connection connector Headphones connection connector LCD board interface connector1 LCD board interface connector2 Power on switch Reset switch NMI switch AC adapter connection connector USB HOST interface connector Front view Note The CN15 connector is used to test the board pri...

Page 16: ...ebug Board External View Figure 1 7 I O Board External View J1 TP1 TP2 TP3 EPROM 8 bit LED 16 bit LED Extension slot EPROM connection jumper switch H UDI connector CN2 CN1 CN11 CN3 CN10 CN9 CN8 CN6 CN7 CN5 CN4 CN1 CN2 ...

Page 17: ... SSOC Earphone microphone 1ch Headphone output 1ch Microphone input Impedance 2 2O Sensitivity 51dB Pa Headphone output Impedance 32O The SH7760 internal SSI is used to transfer data The SH7760 internal SSI used to set a mode USB Host 1ch Controller SH7760 internal USB host TFT color LCD module Model name NL2432DR22 02V NEC Display color 262 144 colors Display area 240 H x 320 V Controller SH7760 ...

Page 18: ... power supply USB bus power Extension slot 3 3V 250mA PCMCIA card power supply Extension slot Notes 1 Table 1 2 shows the maximum dissipation current of T Engine comprising the CPU board LCD board debug board and I O board without external devices 2 Table 1 3 shows the sum of permissible current in all the powered devices on Solution Engine2 Accordingly when a current of 100mA is used for the PCMC...

Page 19: ...an RS 232C cross cable accessory Figure 2 1 shows a host system connection method Figure 2 2 shows the pins of a serial interface connector Table 2 1 shows the signals of the serial interface connector Figure 2 1 Host System Connection Method Figure 2 2 Serial Interface Connector Pin Layout Solution Engine2 Host system RS 232 cross cable accessory 1 15 CN1 ...

Page 20: ...RT 4 GND 5 RTS O RTSB UART 6 CTS I CTSB UART 7 GND 8 Reserved ISP TCK 9 Reserved GND 10 Reserved ISP TMS 11 Reserved ISP Plug 12 Reserved ISP BScan 13 Reserved ISP TDI 14 Reserved ISP TDO 15 Reserved Vcc 3 3V These pins are only used to test the board when it is shipped from the factory Don t use these pins for other purposes ...

Page 21: ...ic shock don t allow the AC adapter cord to be damaged or modified 2 Don t unplug the AC adapter cord with wet hand to avoid a risk of electric shock When unplugging the cord grasp and pull the plug instead of the cord Don t pull the AC adapter cord to avoid a risk of cord damage electric shock or fire 3 When connecting the AC adapter to the receptacle check the polarity and connection beforehand ...

Page 22: ... be implemented 1 Run the program stored in the EPROM on the debug board to refresh the flash memory on the Solution Engine2 or the H8 3048 ONE firmware For details of refreshing refer to 10 Flash Memory Refresh 2 All 8 bit LEDs on the debug board can be turned on or off from the SH7760 board The software execution state can be monitored by controlling the ON OFF state of these LEDs 3 The settings...

Page 23: ...e2 board Figure 2 4 Debug Board Connection Notes When connecting the debug board or detaching the EPROM turn off Solution Engine2 in advance When attaching the EPROM again check the connecting direction Figure 2 5 EPROM Connection Solution Engine2 Extension slot CN2 Connection Extension slot CN1 TP1 J1 CN2 CN1 TP2 TP3 EPROM EPROM TP1 J1 CN2 CN1 TP2 TP3 ...

Page 24: ...h 00400000 to h 007FFFFF The 16 bit LEDs mounted on the debug board are assigned to an address range from h 00800000 to h 00BFFFFF The flash memory of Solution Engine2 is assigned to an address range from h 01000000 to h 017FFFFF J1 Debug board resources are assigned to area 0 on the SH7760 board as shown below The flash memory of Solution Engine2 is assigned to an address range from h 00000000 to...

Page 25: ... ON 2 4 6 H UDI Debugger Connection The debug board allows the H UDI debugger to be connected to the pin 36 CN2 of the H UDI Hitachi User Debug Interface connector Connect the H UDI and AUD pins of the SH7760 board to the H UDI connector Figure 2 4 shows a method for connecting the H UDI debugger Connect an H UDI debugger cable to the H UDI connector CN2 of the debug board Note that the following ...

Page 26: ...t devices other than the H8 3048 ONE press this switch To reset and restart Solution Engine2 release this switch In this case the values of H8 3048 ONE internal registers are not initialized Among the control registers the values of those that can be accessed by SH7760 are initialized but the others are not i e their values are retained For more details refer to 6 13 Initial Values of the Power Su...

Page 27: ... SW5 8 switch is connected to SH7760 s pin MD5 The SW5 8 switch is used to set the type of endian for SH7760 operation ON The MD5 pin goes Low to set the big endian for SH7760 operation OFF The MD5 pin goes High to set the little endian for SH7760 operation Factory setting Figure 3 2 Setting the 8 bit DIP Switch 5 System Reset Switch SW4 The system reset switch controls the hardware reset for Solu...

Page 28: ... 3 2 LCD Board Switch The states of the cursor switch SW1 and push button switches SW2 and SW3 are signaled to the SH7760 through the power supply controller For details refer to 6 Power Supply Controller ...

Page 29: ...0C000000 h 0FFFFFFF SDRAM area 64MB EDS2516APTA 75 ELPIDA x 2 CS4 area 8 16 32bit h 10000000 h 13FFFFFF Extension area CS4 64MB Extension slot CS4 area Extension slot CS4 assert CS5 area 8 16 32bit h 14000000 h 17FFFFFF Extension area CS5 64MB Extension slot CS5area Extension slot CS5 assert CS6 area 16bit h 18000000 h 19FFFFFF PCMCIA area Card controller Model name MR SHPC 01 V2T Marubun This dev...

Page 30: ...sed area CS1 area 16bit h 04000000 h 07FFFFFF Board control register area 16B Board control register CS2 area 8 16 32bit h 08000000 h 0BFFFFFF Extension area CS2 64MB Extension slot CS2 area Extension slot CS2 assert CS3 area 32bit h 0C000000 h 0FFFFFFF SDRAM area 64MB EDS2516APTA 75 ELPIDA x 2 CS4 area 8 16 32bit h 10000000 h 13FFFFFF Extension area CS4 64MB Extension slot CS4 area Extension slot...

Page 31: ...sion slot CS2 assert CS3 area 32bit h 0C000000 h 0FFFFFFF SDRAM area 64MB EDS2516APTA 75 ELPIDA x 2 CS4 area 8 16 32bit h 10000000 h 13FFFFFF Extension area CS4 64MB Extension slot CS4 area Extension slot CS4 assert CS5 area 8 16 32bit h 14000000 h 17FFFFFF Extension area CS5 64MB Extension slot CS5 area Extension slot CS5 assert CS6 area 16bit h 18000000 h 19FFFFFF PCMCIA area Card controller Mod...

Page 32: ...tep read write buffer Endian internal control circuit Support for 5 0V 3 3V cards External buffer not required Internal interrupt steering function Power down function Internal suspend function There are four kinds of controller interrupts SIRQ3 to SIRQ0 Inputs to the H7760 are made by the IRL codes For details refer to Marubun s MR SHPC 01 V2 Manual Marubun Homepage http www2 marubun co jp Figure...

Page 33: ...t 13 A13 I Address bit 13 14 A14 I Address bit 14 A14 I Address bit 14 15 WE I Write enable WE I Write enable 16 READY O Ready IREQ O Interrupt request 17 Vcc Supply voltage Vcc Supply voltage 18 VPP1 Programmed supply voltage VPP1 Programmed supply voltage 19 A16 I Address bit 16 A16 I Address bit 16 20 A15 I Address bit 15 A15 I Address bit 15 21 A12 I Address bit 12 A12 I Address bit 12 22 A7 I...

Page 34: ...it 20 A20 I Address bit 20 50 A21 I Address bit 21 A21 I Address bit 21 51 Vcc Supply voltage Vcc Supply voltage 52 VPP2 Programmed supply voltage VPP2 Programmed supply voltage 53 A22 I Address bit 22 A22 I Address bit 22 54 A23 I Address bit 23 A23 I Address bit 23 55 A24 I Address bit 24 A24 I Address bit 24 56 A25 I Address bit 25 A25 I Address bit 25 57 VS2 O V oltage sense VS2 O V oltage sen...

Page 35: ...FEA H 0000 Interrupt factor register H B83FFFEC H 0000 Interrupt control register H B83FFFEE H 0000 Card voltage control register 1 H B83FFFF0 H 07FC Memory window 0 Control register 1 H B83FFFF2 H 07FC Memory window 1 Control register 1 H B83FFFF4 H 07FC I O window Control register 1 H B83FFFF6 H 0000 Memory window 0 Control register 2 H B83FFFF8 H 0000 Memory window 1 Control register 2 H B83FFF...

Page 36: ...the USB Version 1 1 Providing a route hub function Supporting the low speed 1 5Mbps and full speed 12MB modes Supporting the overcurrent detection function Supporting up to 127 end points Enabling the entire SDRAM area of area 3 connected to the CPU to be used for transfer data and descriptors For more details refer to the pertinent SH7760 Hardware Manual Figure 5 2 USB Host Control Block USB_PENC...

Page 37: ...PeriodCurrentED register H FE340020 H 00000000 HcControlHeadED register H FE340024 H 00000000 HcControlCurrentED register H FE340028 H 00000000 HcBulkHeadED register H FE34002C H 00000000 HcBulkCurrentED register H FE340030 H 00000000 HcDonrHeadED register H FE340034 H 00002EDF HcFmInterval register H FE340038 H 00000000 HcFrameRemaining register H FE34003C H 00000000 HcFmNumber register H FE34004...

Page 38: ... communicate with the power supply controller H8 3048F ONE Because channel B is connected to a 15 pin RS 232C connector CN1 it can be used as a debug interface if it is connected to a PC In addition channel A INTA inputs the controller interrupts to the SH7760 IRL9 and channel B INTB inputs them to the SH7760 IRL11 For more details refer to EXAR s ST16C2550 Manual EXAR Homepage http www exar com F...

Page 39: ...0000 DLL LSB of Divisor Latch DLL LSB of Divisor Latch LCR bit7 1 H BA000002 H 00 IER Interrupt Enable Register IER Interrupt Enable Register LCR bit7 0 H BA000002 DLM MSB of Divisor Latch DLM MSB of Divisor Latch LCR bit7 1 H BA000004 H 01 ISR Interrupt Status Register FCR FIFO Control Register H BA000006 H 00 LCR Line Control Register LCR Line Control Register H BA000008 H 00 MCR Modem Control R...

Page 40: ...IER Interrupt Enable Register IER Interrupt Enable Register LCR bit7 0 H BA800002 DLM MSB of Divisor Latch DLM MSB of Divisor Latch LCR bit7 1 H BA800004 H 01 ISR Interrupt Status Register FCR FIFO Control Register H BA800006 H 00 LCR Line Control Register LCR Line Control Register H BA800008 H 00 MCR Modem Control Register MCR Modem Control Register H BA80000A H 60 LSR Line Status Register N A H ...

Page 41: ...corner is handled as data on the origin 0 0 and data at the lower right corner is handled as data on the coordinates 239 319 The front light on the LCD panel can be turned on or off by the power supply controller For details on front light control refer to 6 Power Supply Controller In addition refer to the pertinent SH7760 Hardware Manual for details on the LCD controller Figure 5 6 LCD Control Bl...

Page 42: ...UT LCDC 26 CL1 OUT LCDC 7 LCD1 OUT LCDC 27 CL2 OUT LCDC 8 LCD2 OUT LCDC 28 DON OUT LCDC 9 LCD3 OUT LCDC 29 M_DISP OUT LCDC 10 LCD4 OUT LCDC 30 FLM OUT LCDC 11 LCD5 OUT LCDC 31 VEPWC OUT LCDC 12 LCD6 OUT LCDC 32 VCPWC OUT LCDC 13 LCD7 OUT LCDC 33 NC Unused 14 GND Power supply 34 GND Power supply 15 GND Power supply 35 GND Power supply 16 LCD8 OUT LCDC 36 IR_IN IN Remote control 17 LCD9 OUT LCDC 37 ...

Page 43: ...N OUT PAD_I F 4 KEY_IN1 IN KEY_I F 16 PAD_DOUT IN PAD_I F 5 KEY_IN2 IN KEY_I F 17 PAD_DCLK OUT PAD_I F 6 KEY_IN3 IN KEY_I F 18 RESET OUT Reset 7 KEY_IN4 IN KEY_I F 19 LCD_FLON OUT LCD Power supply 8 KEY_OUT0 OUT KEY_I F 20 LCD_PWRDY IN LCD Power supply 9 KEY_OUT1 OUT KEY_I F 21 GND Power supply 10 KEY_OUT2 OUT KEY_I F 22 GND Power supply 11 GND Power supply 23 3 3VSB Power supply 12 GND Power supp...

Page 44: ...C10 H 0280 Fetch data line address offset register for display data H FE300C12 H 0000 Palette control register H FE300800 H FE300BFC Palette data register H FE300C14 H 4F52 Horizontal character count register H FE300C16 H 0050 Horizontal synchronization signal register H FE300C18 H 01DF Vertical display line count register H FE300C1A H 01DF Vertical total line count register H FE300C1C H 01DF Vert...

Page 45: ... be controlled via the generator The electronic volume is controlled by the power supply controller For details refer to 6 Power Supply Controller In addition Solution Engine2 has the following characteristics for microphone input and headphone output Microphone input Impedance 2 2KO Sensitivity 51dB Pa Headphone output Impedance 32O For more details refer to the pertinent SH7760 Hardware Manual a...

Page 46: ... Figure 5 9 Sound Generator I O Mini jack CN9 CN10 Table 5 9 Sound Generator I O Mini jack CN9 Signals Pin No Signal name 1 GND 2 R IN 3 R OUT 4 MIC IN 5 HP_SENSE Table 5 10 Sound Generator I O Mini jack CN10 Signals Pin No Signal name 1 GND 2 L OUT 3 R OUT 4 HP_SENSE 5 NC 1 5 3 4 2 CN9 CN10 Sound generator I O mini jack 2 5 Model name HSJ1602 010011 Maker Hoshiden Corporation ...

Page 47: ...er abbreviation Address R W Initial value Access size SSICR0 H FE680000 R W H 0000 0000 32 SSISR0 H FE680004 R W H 0200 0003 32 SSITDR0 H FE680008 R H 0000 0000 32 SSIRDR0 H FE68000C R H 0000 0000 32 SSICR1 H FE690000 R W H 0000 0000 32 SSISR1 H FE690004 R W H 0200 0003 32 SSITDR1 H FE690008 R H 0000 0000 32 SSIRDR1 H FE69000C R H 0000 0000 32 ...

Page 48: ...ow output from SIM_RST The SIM card reset pin is set to Low Reset High output from SIM_RST The SIM card reset pin is set to High Normal Power supply to the SIM card is controlled through the power supply controller H8 3048f ONE The SIM card is being powered while Solution Engine2 s power is turned on Before inserting or removing the SIM card be sure to turn off the Solution Engine2 unit For more d...

Page 49: ...d Interface Connector CN4 Pins Table 5 12 SIM Card Interface Connector CN4 Signals Pin No Signal name 1 C1 VCC 2 C2 RST 3 C3 CLK 4 C4 1 5 C5 GND 6 C6 VPP 7 C7 I O 8 C8 1 1 Don t use the pins 4 and 8 because they must be connected to the board test connector CN13 1 3 4 2 CN4 SIM card interface connector Model name 04 5036 008 110 862 Maker Kyocera Elco 5 6 7 8 ...

Page 50: ...mode register H FE480002 H 07 Bit rate register H FE480004 H 00 Serial control register H FE480006 H FF Transmit data register H FE480008 H 84 Serial status register H FE48000A H 00 Received data register H FE48000C H 01 Smart card mode register H FE48000E H 00 Serial control 2 register H FE480010 H 0000 Wait time register H FE480012 H 00 Guard extension register H FE480014 H 0173 Sample register ...

Page 51: ...760 and the power supply controller refer to 6 2 Serial Communications between SH7760 and the Power Supply Controller H8 3048F ONE SH7727 ST16C2550CQ48 UART CTSA RTSA RXA TXA EXTAL P82 IRQ2 P27 TXD0 RXD0 CK RV5C348A RTC ADS7843E Touch panel IRQ1 P50 INT CE S I SO CLK LCD DIN DOUT DCLK PENIRQ CS LCD board IRQ0 P80 P51 Cursor switch i SW1 j Push button switch SW2 3 P22 P21 P20 P14 P13 P12 P11 P10 P ...

Page 52: ...ommunications take place between SH7760 and the power supply controller 6 2 1 Serial Format This subsection describes a format for serial communications between SH7760 and the power supply controller 1 Mode Start stop 2 Baud rate 38400 bits second 3 Stop bit 1 bit 4 Start bit 1 bit 5 Parity bit None 6 LSB first ...

Page 53: ...de 1 byte 2 Function code 1 byte or 2 byte 3 Register address 2byte Figure 6 2 Read Command 1 Start code The code is fixed at 0x20 2 Function code A 1 byte function code specifies the size of data to be read in the lower 4 bits when the upper 4 bits of a function code are 1000 Figure 6 3 shows a function command where the upper 4 bits are 1000 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 Size of data Figure 6 ...

Page 54: ...of a register subject to a read operation returns 4 Data Read data returns The size of this data is equal to the value specified in the function code 6 2 5 Error Response during a read Operation Figure 6 6 shows the error response format for the read command The power supply controller returns a NAK code and an error code in this order as a response at error occurrence 1 NAK code 1 byte 2 rror cod...

Page 55: ...ter address 2byte 4 Data N byte Figure 6 7 Read Command 1 Start code This code is fixed at 0x20 2 Function code A 1 byte function code specifies the size of data to be written in the lower 4 bits when the upper 4 bits of a function code are 1100 Figure 6 3 shows a function command where the upper 4 bits are 1100 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 0 Size of data Figure 6 8 Function Command 1 Byte A 2 by...

Page 56: ...yte 3 Register address 2 byte 4 Data N byte Figure 6 10 Normal Response during a Write Operation 1 ACK code This code is fixed at ACK 0x06 2 Function code The same code as for the write command returns 3 Register address The address of a register subject to a write operation returns 4 Data Write data returns The size of this data is equal to the value specified in the function code However note th...

Page 57: ...ror code in this order as an error response 1 NAK code 1 byte 2 Error No 1 byte Figure 6 11 Error Response during a Write Operation 1 NAK code This code is fixed at NAK 0x15 2 Error code Table 6 2 summarizes the error codes Table 6 2 Error Codes Error No Error type 0x01 Communication error 0x02 Invalid function code 0x03 Invalid register number 0x04 Register size error 0x05 Data size error ...

Page 58: ...ss R W Size Remarks RTC control register RTCCR 0x0000 R W 1 byte RTC status register RTCSR 0x0001 R W 1 byte Second counter SECCNT 0x0002 R W 1 byte Minute counter MINCNT 0x0003 R W 1 byte Hour counter HRCNT 0x0004 R W 1 byte Day of the week counter WKCNT 0x0005 R W 1 byte Day counter DAYCNT 0x0006 R W 1 byte Month counter MONCNT 0x0007 R W 1 byte Year counter YRCNT 0x0008 R W 1 byte Second alarm ...

Page 59: ... Initial value 1 An interrupt is generated at intervals of 1 second 3 1secI 1secI bit Setting 0 No interrupt is generated at intervals of 1 second Initial value 1 An interrupt is generated at intervals of 1 second 4 0 5secI 0 5secI bit Setting 0 No interrupt is generated at intervals of 0 5 second Initial value 1 An interrupt is generated at intervals of 0 5 second 5 SECCAF SECCAF bit Setting 0 No...

Page 60: ...f each counter is updated Zero clear condition The counter is cleared with zeros when counter update is complete This clear operation is automatically performed Note Don t write to any counter while the START bit is set to 0 Set the CNTS bit to 1 after updating the value of each counter with the START bit set to 1 ...

Page 61: ...hat of each counter register At this time an interrupt occurs if the ARI bit is set to 1 Clear condition This counter is cleared when 0 is written with the ARF bit set to 1 2 1secF 1secF bit Setting 0 A second has not elapsed yet Initial value 1 A second has elapsed Clear condition This counter is cleared when 0 is written with the 1secF bit set to 1 3 0 5secF 0 5secF bit Setting 0 A half second h...

Page 62: ...7 D6 D5 D4 D3 D2 D1 D0 0 10 minutes 1 minute R R W R W R W R W R W R W R W The counter value is a BCD Binary Coded Decimal value Counting takes place within a range from 00 to 59 When the value changes from 59 to 00 a carry is generated in the hour counter 6 3 5 Hour Counter HRCNT Address 0x0004 Initial value 0xXX Not defined D7 D6 D5 D4 D3 D2 D1 D0 0 0 10 hours 1 hour R R R W R W R W R W R W R W ...

Page 63: ...ounter DAYCNT Address 0x0006 Initial value 0xXX Not defined D7 D6 D5 D4 D3 D2 D1 D0 0 0 10 days 1 day R R R W R W R W R W R W R W The counter value is a BCD Binary Coded Decimal value Counting takes place within a range from 1 to 31 January March July August October and December 1 to 30 April June September and November 1 to 28 February in normal year or 1 to 29 February in leap year 6 3 8 Month C...

Page 64: ...itial value 0xXX Not defined D7 D6 D5 D4 D3 D2 D1 D0 10 yars 1 year R W R W R W R W R W R W R W R W The counter value is a BCD Binary Coded Decimal value Counting takes place within a range from 0 to 99 In this range 00 04 92 and 96 are leap years ...

Page 65: ...BCD code minute counter Hour alarm register BCD code Hour counter Day of the week alarm register 0x00 to 0x07 Day of the week counter Day alarm register BCD code Day counter Month alarm register BCD code Month counter 6 3 11 Second Alarm Register SECAR Address 0x0009 Initial value 0x00 D7 D6 D5 D4 D3 D2 D1 D0 AR 10 seconds 1 second R W R W R W R W R W R W R W R W The alarm value must be a BCD Bina...

Page 66: ... from 0x00 to 0x06 Day of theweek and septinary counter value D2 D1 D0 0 0 0 Sunday D2 D1 D0 0 0 1 Monday D2 D1 D0 0 1 0 Tuesday D2 D1 D0 0 1 1 Wednesdady D2 D1 D0 1 0 0 Thursday D2 D1 D0 1 0 1 Friday D2 D1 D0 1 1 0 Saturday 6 3 15 Day Alarm Register DAYAR Address 0x000D Initial value 0x00 D7 D6 D5 D4 D3 D2 D1 D0 AR 0 10 days 1 day R W R R W R W R W R W R W R W The alarm value must be a BCD Binary...

Page 67: ...ster indicates the RTC touch panel or key input status The following is a brief description of RTC related status bits Address 0x0090 Initial value 0x00 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 IRRIF POWERIF KEYIF TPIF RTCIF R R R R W R W R W R W R W 1 RTCIF RTCIF bit Setting 0 The ARF 1secF and 0 5secF bits of the RTC register are all set to 0 Initial value 1 One of the ARF 1secF ad 0 5secF bits of the RTC ...

Page 68: ...ition obtained three times from sampling are approximate to each other a pen touch ON interrupt is generated for SH7760 In addition when the touch panel is turned off a pen touch OFF interrupt is generated 3 To keep the pen touch ON sampling is performed at intervals of 20msec to 100msec and a pen touch ON interrupt is generated if the results obtained from sampling are approximate to each other 4...

Page 69: ...APAR 0x0038 R W 2 byte YA position A D register YAPAR 0x003A R W 2 byte XB position A D register XBPAR 0x003C R W 2 byte YB position A D register YBPAR 0x003E R W 2 byte XC position A D register XCPAR 0x0040 R W 2 byte YC position A D register YCPAR 0x0042 R W 2 byte DX dot register DXDR 0x0044 R W 2 byte DY dot register DYDR 0x0046 R W 2 byte X position dot calculation A D value XPARDOT 0x0048 R ...

Page 70: ...nel is enabled 2 PEN_ONI PEN_ONI bit Setting 0 A pen touch ON interrupt is not generated Initial value 1 A pen touch ON interrupt is generated 3 PEN_OFFI PEN_OFFI bit Setting 0 A pen touch OFF interrupt is not generated Initial value 1 A pen touch OFF interrupt is generated 4 PEN_ONRE PEN_ ONRE bit Setting 0 A pen touch ON interrupt is not generated when pen touch continues Initial value 1 A pen t...

Page 71: ...tion A D register Y position A D register X position dot register and Y position dot register At this time a pen touch ON interrupt is generated if the PEN_ONI bit is set to 1 Clear condition This register is cleared when 0 is written with the PEN_ONIF bit set to 1 2 PEN_OFFIF PEN_OFFIF bit Setting 0 The touch panel has not been pen touched pen touch OFF Initial value 1 At this time a pen touch OF...

Page 72: ...sec 20msec R W R W R W R W R W R W R W R W A sampling interval for the touch panel can be set within a range from 20msec to 160msec unit 20msec When a bit is set to 1 the corresponding sampling interval from 20msec to 160msec is set Note that only the following values can be specified Correspondence between the setting values and sampling intervals 0x01 20msec 0x02 40msec 0x04 60msec 0x08 80msec 0...

Page 73: ...ition A D register indicates the A D conversion result of a pen touched X position on the touch panel 6 4 5 Y Position A D Register YPAR Address 0x0026 Initial value 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 YA_D11 YA_D10 YA_D9 YA_D8 R R R R R R R R D7 D6 D5 D4 D3 D2 D1 D0 YA_D7 YA_D6 YA_D5 YA_D4 YA_D3 YA_D2 YA_D1 YA_D0 R R R R R R R R The Y position A D register indicates the A D conversion re...

Page 74: ...he output value of this register after calibration The output value is not settled without calibration 6 4 7 Y Position Dot Register YPDR Address 0x002A Initial value 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 YD_D15 YD_D14 YD_D13 YD_D12 YD_D11 YD_D10 YD_D9 YD_D8 R R R R R R R R D7 D6 D5 D4 D3 D2 D1 D0 YD_D7 YD_D6 YD_D5 YD_D4 YD_D3 YD_D2 YD_D1 YD_D0 R R R R R R R R The Y position dot register indicates ...

Page 75: ... R W The XA position dot register indicates the X dot position of point A when calibration takes place 6 4 9 YA Position Dot Register YAPDR Address 0x002E Initial value 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 YAD_D15 YAD_D14 YAD_D13 YAD_D12 YAD_D11 YAD_D10 YAD_D9 YAD_D8 R W R W R W R W R W R W R W R W D7 D6 D5 D4 D3 D2 D1 D0 YAD_D7 YAD_D6 YAD_D5 YAD_D4 YAD_D3 YAD_D2 YAD_D1 YAD_D0 R W R W R W R W R W ...

Page 76: ... R W The XB position dot register indicates the X dot position of point B when calibration takes place 6 4 11 YB Position Dot Register YBPDR Address 0x0032 Initial value 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 YBD_D15 YBD_D14 YBD_D13 YBD_D12 YBD_D11 YBD_D10 YBD_D9 YBD_D8 R W R W R W R W R W R W R W R W D7 D6 D5 D4 D3 D2 D1 D0 YBD_D7 YBD_D6 YBD_D5 YBD_D4 YBD_D3 YBD_D2 YBD_D1 YBD_D0 R W R W R W R W R W...

Page 77: ...ibration takes place This register will be functionally enhanced in future Don t access this register 6 4 13 YC Position Dot Register YCPDR Address 0x0036 Initial value 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 YCD_D15 YCD_D14 YCD_D13 YCD_D12 YCD_D11 YCD_D10 YCD_D9 YCD_D8 R W R W R W R W R W R W R W R W D7 D6 D5 D4 D3 D2 D1 D0 YCD_D7 YCD_D6 YCD_D5 YCD_D4 YCD_D3 YCD_D2 YCD_D1 YCD_D0 R W R W R W R W R W ...

Page 78: ...position A D register indicates the X position A D conversion result of point A subject to calibration 6 4 15 YA Position A D Register YAPAR Address 0x003A Initial value 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 YAA_D11 YAA_D10 YAA_D9 YAA_D8 R R R R R W R W R W R W D7 D6 D5 D4 D3 D2 D1 D0 YAA_D7 YAA_D6 YAA_D5 YAA_D4 YAA_D3 YAA_D2 YAA_D1 YAA_D0 R W R W R W R W R W R W R W R W The YA position A D...

Page 79: ...position A D register indicates the X position A D conversion result of point B subject to calibration 6 4 17 YB Position A D Register YBPAR Address 0x003E Initial value 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 YBA_D11 YBA_D10 YBA_D9 YBA_D8 R R R R R W R W R W R W D7 D6 D5 D4 D3 D2 D1 D0 YBA_D7 YBA_D6 YBA_D5 YBA_D4 YBA_D3 YBA_D2 YBA_D1 YBA_D0 R W R W R W R W R W R W R W R W The YB position A D...

Page 80: ...ubject to calibration This register will be functionally enhanced in future Don t access this register 6 4 19 YC Position A D Register YCPAR Address 0x0042 Initial value 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 YCA_D11 YCA_D10 YCA_D9 YCA_D8 R R R R R W R W R W R W D7 D6 D5 D4 D3 D2 D1 D0 YCA_D7 YCA_D6 YCA_D5 YCA_D4 YCA_D3 YCA_D2 YCA_D1 YCA_D0 R W R W R W R W R W R W R W R W The YC position A D...

Page 81: ... register XAPAR When the DX dot register DXDR has been set to 0 the dot position is not calculated 6 4 21 DY Dot Register DYDR Address 0x0046 Initial value 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 DY1_D15 DY1_D14 DY1_D13 DY1_D12 DY1_D11 DY1_D10 DY1_D9 DY1_D8 R W R W R W R W R W R W R W R W D7 D6 D5 D4 D3 D2 D1 D0 DY1_D7 DY1_D6 DY1_D5 DY1_D4 DY1_D3 DY1_D2 DY1_D1 DY1_D0 R W R W R W R W R W R W R W R W T...

Page 82: ... Calculation A D Value 1 XPARDOT1 Address 0x004A Initial value 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 XD1_D9 XD1_D8 R W R W R W R W R W R W R W R W D7 D6 D5 D4 D3 D2 D1 D0 XD1_D7 XD1_D6 XD1_D5 XD1_D4 XD1_D3 0 0 0 R W R W R W R W R W R W R W R W The X position dot calculation A D value 1 register XPARDOT1 holds an XPARDOT value before sampling 6 4 24 X Position Dot Calculation A D Value 2...

Page 83: ... R W R W R W R W R W R W R W D7 D6 D5 D4 D3 D2 D1 D0 XD4_D7 XD4_D6 XD4_D5 XD4_D4 XD4_D3 0 0 0 R W R W R W R W R W R W R W R W The X position dot calculation A D value 4 register XPARDOT4 holds an XPARDOT value before sampling 6 4 27 Y Position Dot Calculation A D Value YPARDOT Address 0x0052 Initial value 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 YD_D9 YD_D8 R W R W R W R W R W R W R W R W ...

Page 84: ...0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 YD2_D9 YD2_D8 R W R W R W R W R W R W R W R W D7 D6 D5 D4 D3 D2 D1 D0 YD2_D7 YD2_D6 YD2_D5 YD2_D4 YD2_D3 0 0 0 R W R W R W R W R W R W R W R W The Y position dot calculation A D value 2 register YPARDOT2 holds a YPARDOT value before sampling 6 4 30 Y Position Dot Calculation A D Value 3 YPARDOT3 Address 0x0058 Initial value 0x0000 D15 D14 D13 D12 D1...

Page 85: ...wer Supply Status Register RTKISR This status register indicates the RTC touch panel or key input status Below is a brief description of the status bits related to the touch panel Address 0x0090 Initial value 0x00 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 IRRIF POWERIF KEYIF TPIF RTCIF R R R R W R W R W R W R W 1 TPIF TPIF bit Setting 0 The PEN_ONIF PEN_OFFIF CAIF and CAEF bits of the touch panel status regis...

Page 86: ... and A D conversion coordinates that are necessary for calibration Figure 6 11 Points of the Drawing Coordinates and A D Conversion Coordinates T Engine Board LCD Point A Point B Origin of A D convertion coordinates A D conver sion coordinates x axis Origin of drawing coordinates Drawing coordinates x axis Drawing coor dinates y axis SW1 SW2 SW3 A D conversion coordinates x axis ...

Page 87: ...AR TXB Y position A D conversion result of point B YBPAR 5 The above calculation results are multiplied by 1 000 their decimal places are rounded and the resulting integers are written to the registers DXDR and DYDR DX dot register DXDR DX x 1 000 rounding the decimal places DY dot register DYDR DY x 1 000 rounding the decimal places 6 The power supply controller uses data stored in the registers ...

Page 88: ...ly controller The power supply controller controls the switches SW1 to SW3 on the CPU board and the switches SW1to SW3 on the LCD board Figure 6 12 Solution Engine 2 Switch Power on switch SW1 Reset switch SW2 SW1 SW2 Solution Engine 2 LCD NMI switch SW3 SW2 CPU board switch SW1 SW2 SW3 Application switch ...

Page 89: ...itch is pressed 3 NMI switch SW3 An NMI interrupt occurs for the SH7760 when the NMI switch is pressed 6 5 2 LCD Board Switch Control Application Switch 1 Cursor switch SW1 and push button switches SW2 and SW3 on the LCD board The cursor switch and push button switches are subject to sampling at intervals of 10msec When consecutive three samplings indicate that the same key is being pressed key bi...

Page 90: ...Switch Registers Register Abbreviation Address R W Size Remarks Key control register KEYCR 0x0060 R W 1 byte Key auto repeat time register KATIMER 0x0061 R W 1 byte Key input status register KEYSR 0x0062 R W 1 byte Key bit pattern register KBITPR 0x0064 R W 2 byte RTC Touch panel Key input Power supply status register RTKISR 0x0090 R W 1 byte ...

Page 91: ...pt is enabled 3 KEY_OFFI KEY_OFFI bit Setting 0 An application switch OFF interrupt is disabled Initial value 1 An application switch key OFF interrupt is enabled 4 ARKEY ARKEY bit Setting 0 An application switch auto repeat interrupt is disabled Initial value 1 An application switch auto repeat interrupt is enabled 5 PONSWI PONSWI bit Setting 0 A power on switch interrupt is disabled Initial valu...

Page 92: ...sec unit 50msec When one of the bits 100msec to 450msec is set the corresponding auto repeat interrupt generation time is set 6 5 6 Key Bit Pattern Register KBIPR Address 0x0064 Initial value 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 SW2 0 SW3 R R R R R R R R D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 SW1 5 Decided SW1 4 SW1 3 SW1 2 SW1 1 R R R R R R R R This register stores the bit pattern of the applica...

Page 93: ...Setting 0 An application switch key is ON or OFF Initial value 1 An application switch key has changed from ON to OFF Initial value At this time if the KEY_OFFI bit is set to 1 a key OFF interrupt occurs Clear condition This bit is cleared when 0 is written with the KEY_OFFI bit set to 1 3 ARKEYF ARKEYF bit Setting 0 The same application switch key is not ON for the time specified in the key auto ...

Page 94: ...all set to 1 and a KEY_ONF interrupt occurs so long as it is enabled 2 If data in the key bit pattern register changes when multiple keys are pressed at the same time a KEY_ONF interrupt occurs so long as it is enabled Example This KEY_ONF interrupt occurs when the state with switches SW1 and SW2 pressed simultaneously changes to one with switches SW1 and SW3 pressed simultaneously 3 When multiple...

Page 95: ...Initial value 0x00 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 IRRIF POWERIF KEYIF TPIF RTCIF R R R R W R W R W R W R W 1 KEYIF KEYIF bit Setting 0 The PONSWF ARKEYF KEY_OFFF and KEY_ONF bits of the key input status register are all set to 0 Initial value 1 One of the PONSWF ARKEYF KEY_OFFF or KEY_ONF bits of the key input status register is set to 1 Clear condition This bit is cleared when 0 is written with th...

Page 96: ...on Engine2 is OFF it is turned ON if the power on switch is pressed for 2sec or more 3 Solution Engine2 can be turned OFF from the SH7760 4 If the DIP switch SW7 is se to ON Solution Engine2 is also turned ON at the same time the power supply controller is turned ON Table 6 6 Power Control Registers Register Abbreviation Address R W Size Remarks System power control register 1 SPOWCR1 0x0070 R W 1...

Page 97: ... SFPOWER Setting 0 Solution Engine2 is turned OFF by SH7760 control 1 Solution Engine2 is turned OFF by pressing the power on switch Initial value 6 6 3 RTC Touch Panel Key Input Power Supply Status Register RTKISR This status register indicates the RTC touch panel or key input status Below is a brief description of the status bits for power control Address 0x0090 Initial value 0x00 D7 D6 D5 D4 D3...

Page 98: ...EDs LED1 to LED8 on the CPU board Table 6 7 LED Controller Registers Register Abbreviation Address R W Size Remarks LED register LEDR 0x00A0 R W 1byte 6 7 1 LED Register LEDR Address 0x00A0 Initial value 0xXX D7 D6 D5 D4 D3 D2 D1 D0 LED8 LED7 LED6 LED5 LED4 LED3 LED2 LED1 R W R W R W R W R W R W R W R W 1 LEDn LEDn bit Setting 0 LEDn is turned OFF 1 LEDn is turned ON LEDn is turned ON for the H8 3...

Page 99: ...LCD front light Table 6 8 LCD Front Light Registers Register Abbreviation Address R W Size Remarks LCD front light registers LCDR 0x00A1 R W 1byte 6 8 1 LCD Front Light Register LCDR Address 0x00A1 Initial value 0x01 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 FRONTL R R R R R R R R W 1 FRONTL FRONTL bit Setting 0 The LCD front light is turned ON 1 The LCD front light is turned OFF Initial value ...

Page 100: ...RESTCR Address 0x00A2 Initial value 0x02 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 SWRES SORES R R R R R R R W R W 1 SORES SORES bit Setting 0 Solution Engine2 is not restarted by reset Initial value 1 Solution Engine2 is restarted by reset If this bit is set to 1 Solution Engine2 is restarted 2 SWRES SWRES bit Setting 0 Devices other than the power supply controller are reset with the reset switch SW2 ...

Page 101: ...ving interrupt may be generated 3 Function for transmitting infrared remote control signals A maximum of 255 bytes of the infrared remote control signal can be transmitted Transmit data can be written to the transmitting FOFOI data register IRRSFDR Infrared remote control signals of the specified format are transmitted Table 6 10 Infrared Remote Control Registers Register Abbreviation Address R W ...

Page 102: ...at is set Initial value 1 The Home Appliance Manufacturer s Association format is set 3 RDIE RDIE bit Setting 0 An interrupt is disabled upon completion of receiving a frame of infrared remote control signal Initial value 1 An interrupt is enabled upon completion of receiving a frame of infrared remote control signal 4 TDIE TDIE bit Setting 0 An interrupt is disabled upon completion of transmittin...

Page 103: ...ial value 1 A buffer full error has occurred during a receive operation 2 RDI RDI bit Setting 0 A frame of data has not been received Initial value 1 A frame of data has been received Clear condition This bit is cleared when 0 is written with the RDI bit set to 1 3 TDI TDI bit Setting 0 A frame of data has not been transmitted Initial value 1 A frame of data has been transmitted Clear condition Th...

Page 104: ...n the value of this register is 0xFF it indicates that the receive FIFO register is full of data 6 10 4 Transmit Data Count Register for Infrared Remote Control Signals Address 0x00B3 Initial value 0x00 D7 D6 D5 D4 D3 D2 D1 D0 IRRSD_D7 IRRSD_D6 IRRSD_D5 IRRSD_D4 IRRSD_D3 IRRSD_D2 IRRSD_D1 IRRSD_D0 R R R R R R R R This register indicates the number of data items not transmitted infrared remote cont...

Page 105: ...IRRSDR_D3 IRRSDR_D2 IRRSDR_D1 IRRSDR_D0 W W W W W W W W This register is an 8 bit FIFO register that stores transmission data Transmission data can be stored until this register is filled with data For details refer to 6 10 8 Infrared Remote Control Data Structure 6 10 7 RTC Touch Panel Key Input Power Supply Status Register RTKISDR This status register indicates the RTC touch panel or key input s...

Page 106: ...RDNR For infrared signal transmission 1 When transmission data is transmitted it is written to the transmitting FIFO data register The data count for one frame of transmission data and the data itself are written to this data register In addition this transmission data count is not counted as transmission data 2 The count for data not transmitted is set in the transmission data count register IRRS...

Page 107: ...PSR 0x00C1 R W 1 byte EEPROM data register EEPDR 0x0100 0x02FF R W 1 byte x 512 6 11 1 EEPROM Control Register EEPCR Address 0x00C0 Initial value 0x00 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 START R R R R R R R R W 1 START START bit Setting 0 The serial EEPROM is disabled Initial value 1 The serial EEPROM is enabled 6 11 2 EEPROM Status Register EEPSR Address 0x00C1 Initial value 0x00 D7 D6 D5 D4 D3...

Page 108: ...2FE 8 bit 0x02FF 8 bit An EEPROM address corresponds to an EEPDR address When a read write operation is performed on the EEPROM the EEPDR address must be specified for the operation 6 11 4 Serial EEPROM Operation Procedure Initial Setting 1 The START bit of the EEPGR register is set to 1 For a read write operation to the serial EEPROM 1 An EEPDR address corresponding to an EEPROM address must be s...

Page 109: ...rs Register Abbreviation Address R W Size Electronic volume data register for the right speaker EVRDR 0x00D0 R W 1 byte Electronic volume data register for the left speaker EVLDR 0x00D1 R W 1 byte 6 12 1 Electronic Volume Data Register for the Right Speaker EVRDR Address 0x00D0 Initial value 0x00 D7 D6 D5 D4 D3 D2 D1 D0 EVRDR_D7 EVRDR_D6 EVRDR_D5 EVRDR_D4 EVRDR_D3 EVRDR_D2 EVRDR_D1 EVRDR_D0 R W R ...

Page 110: ...n A Condition B Condition C Condition D RTC control register RTCCR Initial value Initial value Hold Initial value RTC status register RTCSR Initial value Hold Hold Hold Second counter SECCNT Initial value Operation Operation Operation Minute counter MINCNT Initial value Operation Operation Operation Hour counter HRCNT Initial value Operation Operation Operation Day of the week counter WKCNT Initia...

Page 111: ...old Hold Hold X position dot calculation A D value 1 XPARDOT1 Initial value Hold Hold Hold X position dot calculation A D value 2 XPARDOT2 Initial value Hold Hold Hold X position dot calculation A D value 3 XPARDOT3 Initial value Hold Hold Hold X position dot calculation A D value 4 XPARDOT4 Initial value Hold Hold Hold Y position dot calculation A D value YPARDOT Initial value Hold Hold Hold Y po...

Page 112: ...ol signals IRRRDNR Initial value Initial value Hold Initial value Transmit data count register for infrared remote control signals IRRSDNR Initial value Initial value Hold Initial value Receiving FIFO data register for infrared remote control signals IRRRFDR Initial value Initial value Hold Initial value Transmitting FIFO data register for infrared remote control signals IRRSFDR Initial value Init...

Page 113: ...pt level 10 3 PCMCIA controller SIRQ1 IRL 3 0 IRL 3 0 1000 Interrupt level 7 4 PCMCIA controller SIRQ0 IRL 3 0 IRL 3 0 1010 Interrupt level 5 5 UART controller chA IRL 3 0 IRL 3 0 0110 Interrupt level 9 6 UART controller chB IRL 3 0 IRL 3 0 0011 Interrupt level 12 7 H8 3048F ONE IRL 3 0 IRL 3 0 0010 Interrupt level 13 8 Extension slot IRQ3 IRL 3 0 IRL 3 0 0000 Interrupt level 15 9 Extension slot I...

Page 114: ...el 20 5603 14 0101 861 Kyocera Elco Adaptable connector model 10 5603 14 0101 861 Kyocera Elco Figure 8 1 Extension Slot Position 75 00mm 3 00mm 3 00m m Center of 3mm x 3mm 2 3 Clearance 6 120 00mm 5 50mm 37 50mm 0 58 Giude pin CN 1 Serial interface connector 0 98 Giude pin 1 2 139 140 Entension slot magnified Extension slot ...

Page 115: ...O 20 D15 I O 55 A10 OUT 90 IRQ1 IN 125 AUDSYNC OUT 21 GND 56 A11 OUT 91 IRQ2 IN 126 AUDCK IN 22 GND 57 A12 OUT 92 IRQ3 IN 127 3 3V 4 23 D16 I O 58 A13 OUT 93 NMI_IN IN 128 3 3V 24 D17 I O 59 A14 OUT 94 RST_IN IN 129 3 3V 25 D18 I O 60 A15 OUT 95 RST_OUT OUT 130 3 3V 26 D19 I O 61 GND 96 DREQ IN 131 3 3V 27 D20 I O 62 GND 97 DRAK OUT 132 3 3V 28 D21 I O 63 A16 OUT 98 DACK OUT 133 VBAT_IN 5 29 D22 I...

Page 116: ...rent that can be supplied from Solution Engine2 to a daughter board When a daughter board requires more current a power supply must be mounted on the daughter board Table 9 1 Voltage and Current to the Daughter Board Extension slot signal name Output voltage Permissible current Remarks 3 3V 3 3VSB 3 3V 250mA 3 3V Supplied when the H7760 is turned ON 3 3VSB Always supplied when the AC adais connect...

Page 117: ...a WAIT is output from the daughter board open collector output must take place to prevent a collision of WAIT output when multiple daughter boards are stacked Figure 9 3 Extension Slot IORDY Pin Structure Solution Engine2 Extension slot 20 5603 14 0101 861 Extension slot 10 5603 14 0101 861 Extension slot 20 5603 14 0101 861 Extension slot 10 5603 14 0101 861 Extension slot 20 5603 14 0101 861 Dau...

Page 118: ...esigning the daughter board consider this delay Figure 9 5 shows the basic bus timing of the SH7760 For details on SH7760 bus timing refer to the pertinent SH7760 Hardware Manual Figure 9 4 Extension Slot Bus Buffer Structure Note 1 The bus timing delay time must be used only for reference This is not a guaranteed value SH7760 Bus signal Address bus control signal Data bus Inside Solution Engine B...

Page 119: ... t RWD tRSD tAD tAD tRDH tRDS DACKn SA IO Memory tDACD tDACD Note IO DACK DEVICE SA Single address DMA Transfer DA Dual address DMA Transfer DACK in High Active F i g u r e 9 5 M e m o r y B y t e c o n t r o l S R A M B u s c y c l e B a s i c R e a d c y c l e No wait Address set up Insert hold time AnS 1 AnH 1 116 ...

Page 120: ...terminal Make communication settings as shown in Table 12 1 In addition this monitor program outputs CR LF as a carriage return code Table 10 1 Communication Specifications Data length 8 bit Parity bit None Stop bit 1 bit Baud rate 115200bps Flow control Xon Xoff 2 Monitor program specifications Figure 10 1 shows a monitor program address map Don t write to the area used by the monitor program h 0...

Page 121: ...t h 0FFF0000 h 0FFFFFFF Area used by the monitor program h 10000000 h 13FFFFFF Extension area CS4 CS4 area bus width arbitrary h 14000000 h 17FFFFFF Extension area CS5 CS5 area bus width arbitrary h 18000000 h 1BFFFFFF PCMCIA area CS6 area bus width 16bit Figure 10 1 Memory Map Real Memory Space 3 Monitor program start Connect Solution Engine2 and the host system with an RS 232C cross cable When t...

Page 122: ...ject file has been provided with address information and the object program is located according to this information When the object file has no address information i e it is a relocatable file specify an offset address with the ml command This offset address must be within a user area shown in Figure 10 1 Upon completion of file loading into memory the following message is displayed on the screen...

Page 123: ...0000000 00000000 00000000 00000000 AFC00000 Bank Registers R0 7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Control Registers SR 60000090 SSR 60000090 SPC 00000000 GBR 00000000 VBR 00000000 SGR 00000000 DBR 00000000 MD 1 RB 1 BL 0 FD 0 M 0 Q 0 IMASK 0x9 S 0 T 0 System Registers PC 0C000000 PR 00000000 MACH 00000000 MACL 00000000 FPSCR 00040001 FPUL 00000000 FR 0 SZ 0 PR...

Page 124: ...060 A3 BC 77 EB 2E 63 0E FD AC000070 03 7A F7 F9 8A AB 09 FB AC000080 49 B9 80 FE FF FF 45 FF AC000090 EC E9 6A FB FF FF FD E9 AC0000A0 B8 E1 35 5F DF FF FF FF AC0000B0 CD F4 7D 67 F1 6B BC E7 AC0000C0 4A FF B3 37 FF FF 27 BF AC0000D0 6A 05 31 FE FF DF 31 73 AC0000E0 4A 42 BB F8 F7 FF 6B FB AC0000F0 4A 4A 80 7F FF FF 76 FE 5E F5 43 FA BB FF 2F 7F FF EF E7 F6 FF FF D4 A4 FF FF FC D6 FF FF DD F7 B9 ...

Page 125: ... 00000000 00000000 AFFF0000 Bank Registers R0 7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 SR 600000E1 SSR 60000090 SPC AC00001C GBR 00000000 VBR 00000000 SGR AFFF0000 DBR 00000000 MD 1 RB 1 BL 0 FD 0 M 0 Q 0 IMASK 0xE S 0 T 1 System Registers PC AC00001C PR 00000000 MACH 00000000 MACL 00000000 FPSCR 00040001 FPUL 00000000 FR 0 SZ 0 PR 0 DN 1 Cause 0x00 Enable 0x00 Fla...

Page 126: ... memory like EPROM To disable the set breakpoint use the bi command To enable the set breakpoint disabled by the bi command use the be command 10 Change and display of memory data Use the me command to change the contents of memory Enter the me command as shown below If characters other than hexadecimals are entered the monitor program exits from the me command and displays the command prompt comm...

Page 127: ... an offset address in the fl command This offset address must be within a user area shown in Figure 12 1 Upon completion of program loading into the memory the following message is displayed on the host system screen In this example the program has been loaded into the address h A0000000 within area 3 When flash ROM erasure begins the monitor program displays the following message Upon completion ...

Page 128: ... Start message displayed on the host system screen Turn OFF the power switch SW1 Disconnect the AC adapterfrom CN12 Check for cables and settings Connect the AC adapter from CN14 Write to the flash ROM with the monitor command FL Program written to the flash ROM to be run Disconnect the AC adapter from CN14 Turn OFF the power with the power switch SW1 Open the jumper pin J1 on the debug board Conn...

Page 129: ...to a specific SH register Register display RC Register Clear Clears all the SH registers ME Memory Edit Edits memory MD Memory Dump Dumps memory MF Memory Fill Fills memory Memory DA Disassemble Disassemble G Go Executes a program S Step Executes a program in units of steps BS Breakpoint Set Sets a breakpoint BD Breakpoint Delete Deletes a breakpoint BC Breakpoint Clear Deletes all the breakpoints...

Page 130: ...Though a program can be loaded by specifying an offset address it is effective only when the program to be loaded does not depend on the absolute address When a jump program using an absolute address is loaded with an offset address specified its operation is not guaranteed For this reason don t specify an offset address and load the program into an address at linkage ...

Page 131: ...dress MOTOROLA S format address SDRAM top address H 0c000000 Upper 4 bits of MOTOROLA S format address are ignored 3 Delete FlashROM data Delete all Flash ROM data after the transfer 4 Writing Write first 8M byte data of the SDRAM address to Flash ROM 5 Changing place between Flash ROM and EPROM Change the place between EPROM and Flash ROM by DIP switch setting after writing Programs written to Fl...

Page 132: ...rs Format RR Example Ready RR None Command Option Function RW Register Write Writes data to the corresponding register Format RW regname data Example Ready RW R0 12AB Command Function RC Register Clear Clears all registers with zeros RC Example Ready RC Option None Format ...

Page 133: ...tion Format A Function MD Memory Dump Dumps Memory MD start address end address Example Ready MD Ready MD 0 Ready MD 0 200 A Display in ASCII codes Command Option Format Command MF Memory Fill Fills memory data MF start address end address option Example Ready MF Ready MF AC000000 AC000200 Ready MF AC000000 AC000200 55 Fill with specified data Function Format Option ...

Page 134: ...0 Command Function Option Format G Go Executes a program from a specified address None G start address Example Ready G AC000000 Command Function Option Format S Step Executes a program in units of steps from a specified address None S start address Example Ready S AC000000 Command Function Option Format ...

Page 135: ...dress Command Function Option None Format Example Ready BD 45C BS Breakpoint Set Sets a breakpoint BS address Example Ready BS AC000000 Command Function Option None Format BC Break Clear Deletes all the breakpoints BC Example Ready BC Command Function Option None Format ...

Page 136: ...133 BI Break Ignore Ignores a breakpoint BI Example Ready BI Command Function Option None Format BE Break Enable Causes a break at a breakpoint BE Example Ready BE Command Function None Option Format ...

Page 137: ...F FL 5 Disassemble DA 6 Start User Program G S 7 Cache CA CR CE CD CF CW CB H elp number or class for more information Ready H 4 Debugger Help 4 Memory Memory Load M em L oad Memory Edit M em E dit startAdrs size W L Memory Dump M em D ump startAdrs endAdrs ASCIIcode A Memory Fill M em F ill startAdrs endAdrs Data Data endAdrs Data Data Flash Load F lash L oad offsetAdrs Ready Displays a help menu...

Page 138: ...on Date 1st Edition Mar 2004 Published by Ubiquitous Platform Design Dept Hitachi ULSI Systems Co Ltd Edit by Ubiquitous Platform Design Dept Hitachi ULSI Systems Co Ltd Copy right Hitachi ULSI Systems Co Ltd 2004 All rights are reserved Printed in Japan ...

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