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5
9.5 Extension Slot AC Timing
As shown in Figure 9.4, the SH7760 bus signal is output to the extension slot via the bus buffer. For this reason,
the bus signal delays approx. 8nsec for the AC timing of the SH7660 bus. When designing the daughter board,
consider this delay. Figure 9.5 shows the basic bus timing of the SH7760.
For details on SH7760 bus timing, refer to the pertinent SH7760 Hardware Manual.
Figure 9.4 Extension Slot Bus Buffer Structure
[Note]
(1) The bus timing delay time must be used only for reference. This is not a guaranteed value.
SH7760
Bus signal
Address bus
control signal
Data bus
Inside Solution Engine
Bus buffer
Extension slot
Summary of Contents for SH7760 Solution Engine2
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