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Hitachi HTS721010G9AT00, Specifications

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Travelstar 7K100 Hard Disk Drive Specification

64 

10.13  Status Register

Table 44: Status Register

This register contains the device status. The contents of this register are updated whenever an error occurs and at 
the completion of each command.

If the host reads this register when an interrupt is pending, it is considered to be the interrupt acknowledge. Any 
pending interrupt is cleared whenever this register is read.

If BSY=1, no other bits in the register are valid.

Bit

Definitions

7

6

5

4

3

2

1

0

BSY

DRDY

DF

DSC

DRQ

CORR

IDX

ERR

BSY

Busy. BSY=1 whenever the device is accessing the registers. The host should not read or write 
any registers when BSY=1. If the host reads any register when BSY=1, the contents of the Status 
Register will be returned.

DRDY 
(RDY)

Device Ready. RDY=1 indicates that the device is capable of responding to a command. RDY 
will be set to 0 during power on until the device is ready to accept a command.

DF

Device Fault. DF=1indicates that the device has detected a write fault condition. DF is set to 0 
after the Status Register is read by the host.

DSC

Device Seek Complete. DSC=1indicates that a Seek has completed and the device head is settled 
over a track.  DSC is set to 0 by the device just before a Seek begins. When an error occurs, this 
bit is not changed until the Status Register is read by the host and at that time the bit again indi-
cates the current Seek complete status. When the device enters into or is in Standby mode or 
Sleep mode, this bit is set by device in spite of the drive not spinning up.

DRQ

Data Request.  DRQ=1 indicates that the device is ready to transfer a word or byte of data 
between the host and the device. The host should not write the Command register when DRQ=1.

CORR

Corrected Data. Always 0

IDX

Index.  IDX=1 once per revolution. Since IDX=1 only for a very short time during each revolu-
tion, the host may not see it set to 1 even if the host is reading the Status Register continuously. 
Therefore the host should not attempt to use IDX bit for timing purposes.

ERR

Error. ERR=1 indicates that an error occurred during execution of the previous command. The 
Error Register should be read to determine the error type. The device sets bit ERR=0 when the 
next command is received from the host.

Summary of Contents for HTS721010G9AT00

Page 1: ...Hard Disk Drive Specification Hitachi Travelstar 7K100 2 5 inch ATA IDE hard disk drive Model HTS721010G9AT00 HTS721080G9AT00 HTS721060G9AT00 Revision 1 3 13 July 2006 ...

Page 2: ......

Page 3: ...Hard Disk Drive Specification Travelstar 7K100 2 5 inch ATA IDE hard disk drive Model HTS721010G9AT00 HTS721080G9AT00 HTS721060G9AT00 Revision 1 3 13 July 2006 ...

Page 4: ...cation Hitachi may make improvements or changes in any products or programs described in this publication at any time It is possible that this publication may contain reference to or information about Hitachi products machines and programs programming or services that are not announced in your country Such references or information must not be construed to mean that Hitachi intends to announce suc...

Page 5: ... Operating modes 16 5 0 Data integrity 17 5 1 Data loss at power off 17 5 2 Write Cache 17 5 3 Equipment status 17 5 4 WRITE safety 18 5 5 Data buffer test 18 5 6 Error recovery 18 5 7 Automatic reallocation 18 5 7 1 Nonrecovered write errors 18 5 7 2 Nonrecoverable read error 18 5 7 3 Recovered read errors 18 5 8 ECC 19 6 0 Specification 21 6 1 Environment 21 6 1 1 Temperature and humidity 21 6 1...

Page 6: ... 6 8 Electromagnetic compatibility 33 6 8 1 CE mark 33 6 8 2 C TICK mark 33 6 8 3 BSMI mark 33 6 8 4 MIC mark 33 6 9 Safety 34 6 9 1 UL and CSA approval 34 6 9 2 IEC compliance 34 6 9 3 German safety mark 34 6 9 4 Flammability 34 6 9 5 Secondary circuit protection 34 6 10 Packaging 34 7 0 Electrical interface specification 35 7 1 Cabling 35 7 2 Interface connector 35 7 3 Signal definitions 36 7 4 ...

Page 7: ...us Register 64 11 0 General 65 11 1 Reset response 65 11 2 Register initialization 66 11 3 Diagnostic and Reset considerations 67 11 4 Power off considerations 68 11 4 1 Load Unload 68 11 4 2 Emergency unload 68 11 4 3 Required power off sequence 68 11 5 Sector Addressing Mode 69 11 5 1 Logical CHS addressing mode 69 11 5 2 LBA addressing mode 69 11 6 Power management features 70 11 6 1 Power mode...

Page 8: ...Seek Overlap 83 11 13 Write Cache function 83 11 14 Reassign Function 84 11 14 1 Auto Reassign Function 84 11 15 48 bit Address Feature Set 85 12 0 Command protocol 87 12 1 Data In commands 87 12 2 Data Out Commands 88 12 3 Non data commands 89 12 4 DMA Data Transfer commands 91 13 0 Command descriptions 93 13 1 Check Power Mode E5h 98h 97 13 2 Device Configuration Overlay B1h 98 13 2 1 DEVICE CON...

Page 9: ...46 13 29 Security Freeze Lock F5h 148 13 30 Security Set Password F1h 149 13 31 Security Unlock F2h 151 13 32 Seek 7xh 152 13 33 Sense Condition F0h vendor specific 153 13 34 Set Features EFh 154 13 35 Set Max ADDRESS F9h 156 13 36 Set Max ADDRESS EXT 37h 158 13 37 Set Multiple C6h 160 13 38 Sleep E6h 99h 161 13 39 S M A R T Function Set B0h 162 13 39 1 S M A R T Function Subcommands 163 13 39 2 D...

Page 10: ...rite Sectors 30h 31h 193 13 50 Write Sectors s EXT 34h 195 13 51 Write Verify 3Ch vendor specific 196 14 0 Time out values 197 15 0 Appendix 199 15 1 Commands Support Coverage 199 15 2 SET FEATURES Commands Support Coverage 201 15 3 Changes from the Travelstar 5K100 202 ...

Page 11: ...ration PSD Profile Breakpoints nonoperating 31 Table 21 Operating shock 31 Table 22 Nonoperating shock 31 Table 23 Weighted sound power 32 Table 24 Signal definitions 36 Table 25 Special signal definitions for Ultra DMA 37 Table 26 System reset timings 40 Table 27 PIO cycle timings 41 Table 28 Multiword DMA cycle timings 42 Table 29 Ultra DMA cycle timings Initiating Read 43 Table 30 Ultra DMA cyc...

Page 12: ...Cache command E7h 103 Table 64 Format Track command 50h 104 Table 65 Format Unit command F7h 105 Table 66 Identify Device command ECh 106 Table 67 Identify device information Part 1 of 7 107 Table 68 Identify device information Part 2 of 7 108 Table 69 Identify device information Part 3 of 7 109 Table 70 Identify device information Part 4 of 7 110 Table 71 Identify device information Part 5 of 7 1...

Page 13: ...h 152 Table 108 Sense Condition F0h vendor specific 153 Table 109 Set Features EFh 154 Table 110 Set Max ADDRESS F9h 156 Table 111 Set Max ADDRESS EXT Command 37h 158 Table 112 Set Multiple command C6h 160 Table 113 Sleep E6h 99h 161 Table 114 S M A R T Function Set B0h 162 Table 115 Device Attribute Data Structure 168 Table 116 Status Flag definitions 170 Table 117 Device Attribute Thresholds Dat...

Page 14: ...Table 134 Write Multiple EXT 39h 191 Table 135 Write Sectors Command 30h 31h 193 Table 136 Write Sector s EXT Command 34h 195 Table 137 Time out values 197 ...

Page 15: ...stem C Celsius CSA Canadian Standards Association C UL Canadian Underwriters Laboratory Cyl cylinder DC Direct Current DFT Drive Fitness Test DMA Direct Memory Access ECC error correction code EEC European Economic Community EMC electromagnetic compatibility ERP Error Recovery Procedure ESD Electrostatic Discharge FCC Federal Communications Commission FRU field replacement unit G gravity a unit of...

Page 16: ... A weighted sound power m meter max maximum MB 1 000 000 bytes Mbps 1 000 000 bits per second MHz megahertz MLC Machine Level Control mm millimeter ms millisecond us ms microsecond No number O Output OD Open Drain Programmed Input Output PIO Programmed Input Output POH power on hours Pop population P N part number p p peak to peak PSD power spectral density RES radiated electromagnetic susceptibil...

Page 17: ... tristate logic 1 4 Caution Do not apply force to the top cover See figure below Do not cover the breathing hole on the top cover See figure below Do not touch the interface connector pins or the surface of the printed circuit board This drive can be damaged by electrostatic discharge ESD Any damages incurred to the drive after its removal from the shipping package and the ESD protective bag are t...

Page 18: ...Travelstar 7K100 Hard Disk Drive Specification 4 ...

Page 19: ...ad Solomon Code Non interleave 2 symbol system ECC Segmented Buffer with write cache 8192 KB Upper 417 KB is used for firmware Fast data transfer rate up to 100 MB s Media data transfer rate max 629 Mb s Average seek time 10 ms for read Closed loop actuator servo Embedded Sector Servo Rotary voice coil motor actuator Load Unload mechanism Mechanical latch Adaptive power save control 0 85 Watts at ...

Page 20: ...Travelstar 7K100 Hard Disk Drive Specification 6 ...

Page 21: ...Travelstar 7K100 Hard Disk Drive Specification 7 Part 1 Functional specification ...

Page 22: ...Travelstar 7K100 Hard Disk Drive Specification 8 ...

Page 23: ...nctions AT Interface Protocol Embedded Sector Servo No ID TM formatting Multizone recording Code 100 106 ECC On The Fly Enhanced Adaptive Battery Life Extender 3 2 Head disk assembly data The following technologies are used in the drive Femto slider Textured laminated AFC glass disk GMR head Integrated lead suspension ILS Load unload mechanism Mechanical latch ...

Page 24: ...Travelstar 7K100 Hard Disk Drive Specification 10 ...

Page 25: ...ogical Lay out Number of heads 16 16 16 Number of Sectors track 63 63 63 Number of Cylinders 16 383 16 383 16 383 Number of sectors 195 371 568 156 301 488 117 210 240 Total logical data bytes 100 030 242 816 80 026 361 856 60 011 642 880 Table 2 Data sheet Rotational Speed RPM 7200 Data transfer rates buffer to from media Mbps 267 629 Data transfer rates ULTRA DMA 100 Mbyte sec 100 Recording dens...

Page 26: ...10 286 13 319 846 Data Zone 5 13 320 17 093 828 Data Zone 6 17 094 20 127 810 Data Zone 7 20 128 23 161 792 Data Zone 8 23 162 26121 774 Data Zone 9 26 122 29 451 756 Data Zone 10 29 452 32 411 738 Data Zone 11 32 412 36 111 720 Data Zone 12 36 112 38 553 702 Data Zone 13 38 554 41 513 684 Data Zone 14 41 514 43 733 666 Data Zone 15 43 734 47 433 648 Data Zone 16 47 434 50 8037 612 Data Zone 17 50...

Page 27: ...e drive It does not include system throughput which is dependent on the system and the application The following table gives a typical value for each parameter The detailed descriptions are found in Section 5 0 Data integrity beginning on page 17 4 4 1 Command overhead Command overhead time is defined as the interval from the time that a drive receives a command to the time that the actuator start...

Page 28: ...ctuator s motion to the start of a reliable read or write operation A reliable read or write implies that error correction or recovery is not used to correct arrival problems The average seek time is measured as the weighted average of all possible seek combinations max Σ m 1 n Tn Tn n 1 Weighted Average max 1 max where max maximum seek length n seek length 1 to max Tnin inward measured seek time ...

Page 29: ...dy time Table 7 Single track seek time Command type Typical ms Max ms Read 1 0 4 0 Write 1 2 4 5 Table 8 Average latency Rotational speed RPM Time for one revolution ms Average latency ms 7200 8 3 4 2 Table 9 Drive ready time Condition Drive ready time sec Typical Max Power on to Ready 4 0 9 5 Ready The condition in which the drive is able to perform a media access command for exam ple read write ...

Page 30: ...mode Write Write operation mode Read Read operation mode Performance Idle The device is capable of responding immediately to idle media access requests All elec tronic components remain powered and the full frequency servo remains operational Active idle The device is capable of responding immediately to media access requests Some cir cuitry including servo system and R W electronics is in power s...

Page 31: ...not yet written onto the disk In order to prevent this data loss confirm the completion of the actual write operation prior to the power off by issuing a Soft reset Hard reset Flush Cache command Standby command Standby Immediate command Sleep command Confirm the command s completion 5 3 Equipment status The equipment status is available to the host system whenever the drive is not ready to read w...

Page 32: ...hen specific conditions are met The drive does not report any auto reallocation to the host system The conditions for auto reallocation are described below 5 7 1 Nonrecovered write errors When a write operation cannot be completed after the Error Recovery Procedure ERP is fully carried out the sectors are reallocated to the spare location An error is reported to the host system only when the write...

Page 33: ...pa bility The first 6 symbol of ECC are 4 check symbols for user data and the 2 symbol system ECC The other 34 symbols are Read Solomon ECC Hardware logic corrects up to 16 symbols 20 bytes errors on the fly 2 symbol System ECC is generated when HDC receives user data from HOST and can correct up to 1 symbol 10bit errors on the fly when one transfers to HOST ...

Page 34: ...Travelstar 7K100 Hard Disk Drive Specification 20 ...

Page 35: ...mbly The maximum storage period in the shipping package is one year Table 12 Environmental condition Operating conditions Temperature 5 to 55ºC See note below Relative humidity 8 to 90 non condensing Maximum wet bulb temperature 29 4ºC non condensing Maximum temperature gradient 20ºC hour Altitude 300 to 3 048 m 10 000 ft Non operating conditions Temperature 40 to 65ºC Relative humidity 5 to 95 no...

Page 36: ... after being exposed to a temperature humidity stress of 50 C 90 RH relative humidity for one week followed by a temperature and humidity drop to 25 C 40 RH in 2 hours Specification Environment 0 10 20 30 40 50 60 70 80 90 100 45 35 25 15 5 5 15 25 35 45 55 65 Temperature degC Relative Humidity Operating Non Operating WetBulb 40 C WetBulb29 4 C 41 C 95 31 C 90 65 C 23 55 C 15 ...

Page 37: ...requency range from DC to 20 Mhz injected through any two of the mounting screw holes of the drive when an AC current of up to 45 mA p p is applied through a 50 ohm resistor connected to any two mounting screw holes 6 1 4 Magnetic fields The disk drive will withstand radiation and conductive noise The test method is defined in the Noise Susceptibility Test Method specification P N 95F3944 Table 14...

Page 38: ...erage current is specified based on three operations per 100 ms 6 The worst case operating current includes motor surge 6 2 1 Power consumption efficiency Note Power consumption efficiency is calculated as Power Consumption of Low Power Idle in Watts Capacity GB Table 15 DC power requirements Item Requirements Nominal supply 5Volt DC Supply voltage 0 3 Volt to 6 0 Volt Power supply ripple 0 20 MHz...

Page 39: ... and usage condition The drive is designed to be used under the following conditions The drive should be operated within specifications of shock vibration temperature humidity altitude and magnetic field The drive should be protected from ESD The breathing hole in the top cover of the drive should not be covered Force should not be applied to the cover of the drive The specified power requirements...

Page 40: ...e mechanically stressful than a normal unload The drive supports a minimum of 20 000 emergency unloads 6 3 6 2 Required Power Off Sequence The required BIOS sequence for removing power from the drive is as follows Step 1 Issue one of the following commands Standby Standby immediate Sleep Note Do not use the Flush Cache command for the power off sequence because this command does not invoke Unload ...

Page 41: ...nload function Start Stop testing should be done by commands through the interface not by power cycling the drive Simple power cycling of the drive invokes the emergency unload mechanism and subjects the HDD to nontypical mechan ical stress Power cycling testing may be required to test the boot up function of the system In this case Hitachi recommends that the power off portion of the cycle contai...

Page 42: ...ons The mounting hole locations and size of the drive are shown below 6 4 3 Connector and jumper description A jumper is used to designate the drive address as either master or slave The jumper setting method is described in Section 7 10 Drive address setting on page 51 Table 17 Physical dimensions and weight Height mm 9 5 0 2 Width mm 69 85 0 25 Length mm 100 2 0 25 Weight grams maximum 115 Max ...

Page 43: ...on will be able to run verti cally and vice versa The recommended mounting screw torque is 3 0 0 5 kgf cm The recommended mounting screw depth is 3 0 0 3 mm for bottom and 3 5 0 5 mm for horizontal mounting The user is responsible for using the appropriate screws or equivalent mounting hardware to mount the drive securely enough to prevent excessive motion or vibration of the drive at seek operati...

Page 44: ...ing subjected to the following vibration levels 6 5 1 1 Random vibration The test consists of 30 minutes of random vibration using the power spectral density PSD levels below The vibration test level is 6 57 m sec2 RMS Root Mean Square 0 67 G RMS 6 5 1 2 Swept sine vibration Table 18 Random vibration PSD profile breakpoints operating Random vibration PSD profile breakpoint Hz m x 10n m2 sec4 Hz 5 ...

Page 45: ... criteria in the table below while operating under these conditions The shock test consists of 10 shock inputs in each axis and direction for a total of 60 There must be a minimum delay of 3 seconds between shock pulses The disk drive will operate without a hard error while subjected to the following half sine shock pulse The input level shall be applied to the normal disk drive subsystem mounting...

Page 46: ...be used The acoustical characteristics of the disk drive are measured under the following conditions Mode definitions Idle mode Power on disks spinning track following unit ready to receive and respond to control line com mands Operating mode Continuous random cylinder selection and seek operation of the actuator with a dwell time at each cylinder The seek rate for the drive is calculated with the...

Page 47: ...d Regulations Class B Part 15 RFI Suppression German National Requirements RFI Japan VCCI Requirements of Hitachi products EU EMC Directive Technical Requirements and Conformity Assessment Procedures 6 8 1 CE mark The drive is certified for compliance with EC directive 89 336 EEC The EC marking for the certification appears on the drive 6 8 2 C TICK mark The drive complies with the Australian EMC ...

Page 48: ...n obtained 6 9 4 Flammability The printed circuit boards used in this drive are made of material with a UL recognized flammability rating of V 1 or better The flammability rating is marked or etched on the board Except for small mechanical parts all other parts not considered electrical components are made of material with a UL recognized flammability rating of V 1 or better 6 9 5 Secondary circui...

Page 49: ...gth in the host system shall not exceed 18 inches 7 2 Interface connector The signal connector for AT attachment is designed to mate with Dupont part number 69764 044 or equivalent The figure below and show the connector and pin location Pin position 20 is left blank for correct connector insertion Pin positions A B C and D are used for the drive address setting 43 44 22 Pin Pin 19 1 2 A C B D ...

Page 50: ...TTL 02 GND 03 DD07 I O 3 state 04 DD08 I O 3 state 05 DD06 I O 3 state 06 DD09 I O 3 state 07 DD05 I O 3 state 08 DD10 I O 3 state 09 DD04 I O 3 state 10 DD11 I O 3 state 11 DD03 I O 3 state 12 DD12 I O 3 state 13 DD02 I O 3 state 14 DD13 I O 3 state 15 DD01 I O 3 state 16 DD14 I O 3 state 17 DD00 I O 3 state 18 DD15 I O 3 state 19 GND 20 Key 21 DMARQ O 3 state 22 GND 23 DIOW I TTL 24 GND 25 DIOR ...

Page 51: ...lected RESET This line is used to reset the drive It shall be kept at a Low logic state during power up and kept High thereafter DIOW The rising edge of this signal holds data from the data bus to a register or data register of the drive DIOR When this signal is low it enables data from a register or data register of the drive onto the data bus The data on the bus shall be latched on the rising ed...

Page 52: ...wing the receipt of a valid Execute Drive Diagnostics command device 1 shall negate PDIAG within 1 ms to indicate to device 0 that it is busy and has not yet passed its drive diagnostics If device 1 is present then device 0 shall wait up to 6 seconds from the receipt of a valid Execute Drive Diagnostics command for drive 1 to assert PDIAG Device 1 should clear BSY before asserting PDIAG as PDIAG i...

Page 53: ...BE Ultra DMA This signal is used only for Ultra DMA data transfers between host and drive The signal HSTROBE is the data out strobe signal from the host for an Ultra DMA data out transfer Both the rising and falling edge of HSTROBE latch the data from DD 15 0 into the device The host may stop toggling HSTROBE to pause an Ultra DMA data out transfer STOP Ultra DMA This signal is used only for Ultra...

Page 54: ...ble 26 System reset timings Inputs Input High Voltage ViH Input Low Voltage ViL 2 0 V min 5 5 V max 0 5 V min 0 8 V max Outputs Output High Voltage VoH Output Low Voltage VoL 2 4 V min 0 5 V max Current Driver Sink Current IoL Driver Source Current Ioh 16mA min 400 µA min PARAMETER DESCRIPTION Min µs Max µs t1 RESET high to Not BUSY 9 5 t10 RESET low width 25 t10 t1 RESET BUSY ...

Page 55: ...5 t2 DIOR DIOW pulse width 70 t2i DIOR DIOW recovery time 25 t3 DIOW data setup 20 t4 DIOW data hold 10 t5 DIOR data setup 20 t6 DIOR data hold 5 t6z DIOR data tristate 30 t9 DIOR DIOW to address valid hold 10 tRD Read data valid to IORDY active 0 tA IORDY setup width 35 tB IORDY pulse width 1 250 IOCS16 t9 t0 t2 t2i t3 t4 t5 t8 t7 t1 tB Read data DD 15 0 DIOR DIOW CS 1 0 DA 2 0 W rite data DD 15 ...

Page 56: ...e 120 tD DIOR DIOW asserted pulse width 70 tE DIOR data access 50 tF DIOR data hold 5 tG DIOR DIOW data setup 20 tH DIOW data hold 10 tI DMACK to DIOR DIOW setup 0 tJ DIOR DIOW to DMACK hold 5 tKR tKW DIOR negated pulse width DIOW negated pulse width 25 tLR tLW DIOR to DMARQ delay DIOW to DMARQ delay 35 tZ DMACK to read data released 25 WRITEDD 15 0 READDD 15 0 DMACK DMARQ DIOR DIOW t0 tLR tLW tJ ...

Page 57: ...0 20 tENV Envelope time 20 70 20 70 20 70 20 55 20 55 20 50 tZIORDY Minimum time before driv ing IORDY 0 0 0 0 0 0 tFS First DSTROBE time 0 230 0 200 0 170 0 130 0 120 0 90 tCYC Cycle time 112 73 54 39 25 16 8 t2CYC Two cycle time 230 154 115 86 57 38 tAZ Maximum time allowed for output drivers to release 10 10 10 10 10 10 tZAD Drivers to assert 0 0 0 0 0 0 tDS Data setup time at host 15 10 7 7 5 ...

Page 58: ...SR timing the host should be ready to receive two more data words after HDMARDY is negated PARAMETER DESCRIPTION MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MIN ns MAX ns MIN ns MAX ns MIN ns MAX ns MIN ns MAX ns MIN ns MAX ns MIN ns MAX ns tSR DSTROBE to HDMARDY time 50 30 20 tRFS HDMARDY to final DSTROBE time 75 70 60 60 60 50 DSTROBE HDMARDY DMACK DMARQ tSR STOP tRFS ...

Page 59: ...e 0 150 0 150 0 150 0 100 0 100 0 75 tAZ Maximum time allowed for output drivers to release 10 10 10 10 10 10 tZAH Minimum delay time required for output 20 20 20 20 20 20 tMLI Interlock time with mini mum 20 20 20 20 20 20 tDS CRC word setup time at device 15 10 7 7 5 4 tDH CRC word hold time at device 5 5 5 5 5 4 6 tACK Hold time for DMACK negation 20 20 20 20 20 20 tIORDYZ Maximum time before r...

Page 60: ...0 150 0 150 0 100 0 100 0 75 tAZ Maximum time allowed for output drivers to release 10 10 10 10 10 10 tZAH Maximum delay time required for output 20 20 20 20 20 20 tMLI Interlock time with mini mum 20 20 20 20 20 20 tDS CRC word setup time at device 15 10 7 7 5 4 tDH CRC word hold time at device 5 5 5 5 5 4 6 tACK Hold time for DMACK negation 20 20 20 20 20 tIORDYZ Maximum time before releasing IO...

Page 61: ...ACK 20 20 20 20 20 20 tENV Envelope time 20 70 20 70 20 70 20 55 20 55 20 55 tZIORDY Minimum time before driv ing IORDY 0 0 0 0 0 0 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 tCYC Cycle time 112 73 54 39 25 16 8 t2CYC Two cycle time 230 154 115 86 57 38 tDS Data setup time at device 15 10 7 7 5 4 tDH Data Hold time at device 5 5 5 5 5 4 6 HSTROBE DDMARDY DMACK DMARQ STOP tUI tAC...

Page 62: ... the tSR timing the device is ready to receive two more data words after DDMARDY is negated PARAMETER DESCRIPTION MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MIN ns MAX ns MIN ns MAX ns MIN ns MAX ns MIN ns MAX ns MIN ns MAX ns MIN ns MAX ns tSR HSTROBE to DDMARDY time 50 30 20 tRFS DDMARDY to final HSTROBE time 75 70 60 60 60 50 HSTROBE DDMARDY DMACK DMARQ tSR STOP tRFS ...

Page 63: ...0 60 50 tRP Ready to pause time 160 125 100 100 100 85 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 tMLI Interlocking time with mini mum 20 20 20 20 20 20 tDS CRC word setup time at device 15 10 7 7 5 4 tDH CRC word hold time at device 5 5 5 5 5 4 6 tACK Hold time for DMACK negation 20 20 20 20 20 20 tIORDYZ Maximum time before releasing IORDY 20 20 20 20 20 20 HSTROBE DDMARDY DMA...

Page 64: ...dge to assertion of STOP 50 50 50 50 50 50 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 tMLI Interlock time with mini mum 20 20 20 20 20 20 tCS CRC word setup time at device 15 10 7 7 5 4 tCH CRC word hold time at device 5 5 5 5 5 4 6 tACK Hold time for DMACK 20 20 20 20 20 20 tIORDYZ Maximum time before releasing IORDY 20 20 20 20 20 20 HSTROBE DDMARDY DMACK DMARQ STOP tMLI DD 15...

Page 65: ...er no jumper is used Setting 2 Device 1 Slave Setting 3 Cable Select Setting 4 Do not attach a jumper here Setting 5 Do not attach a jumper here The default setting at shipment is Setting 1 no jumper When pin C is grounded the drive does not spin up at POR When the drive address is Cable Select the address depends on the condition of pin 28 of the AT interface cable If pin 28 is ground or low the ...

Page 66: ...to address the Command Block registers while the CS1 is used to address Con trol Block registers The following table shows the I O address map Table 37 I O address map CS0 CS1 DA02 DA01 DA00 DIOR 0 Read DIOW 0 Write Command Block Registers 0 1 0 0 0 Data Reg Data Reg 0 1 0 0 1 Error Reg Features Reg 0 1 0 1 0 Sector count Reg Sector count Reg 0 1 0 1 1 LBA low Reg LBA low Reg 0 1 1 0 0 LBA mid Reg...

Page 67: ...Travelstar 7K100 Hard Disk Drive Specification 53 Part 2 Interface specification ...

Page 68: ...Travelstar 7K100 Hard Disk Drive Specification 54 ...

Page 69: ...mitations described in Section 9 0 Deviations from standard on page 57 The drive supports the following functions as Vendor Specific Functions Address Offset Feature Format Unit Function SENSE CONDITION command 8 2 Terminology Device The Travelstar 7K100 drive Host Host indicates the system to which the device is attached First Command The first command which is executed immediately after the powe...

Page 70: ...Travelstar 7K100 Hard Disk Drive Specification 56 ...

Page 71: ...on 3b dated 26 February 2002 with the following deviation Write Verify WRITE VERIFY command does not include read verification after write operation The function is the same as WRITE SECTORS command S M A R T Return Status S M A R T RETURN STATUS subcommand does not check advisory attributes This means that the device will not report a threshold exceeded condition unless the prefailure attributes ...

Page 72: ...Travelstar 7K100 Hard Disk Drive Specification 58 ...

Page 73: ...ate status Addresses Functions CS0 CS1 DA2 DA1 DA0 READ DIOR WRITE DIOW N N x x x Data bus high impedence Not used Control block registers N A 0 x x Data bus high impedance Not used N A 1 0 x Data bus high impedance Not used N A 1 1 0 Alternate Status Device Control N A 1 1 1 Device Address Not used Command block registers A N 0 0 0 Data Data A N 0 0 1 Error Register Features A N 0 1 0 Sector Coun...

Page 74: ...immediately after this register is written The command set is shown in Table 53 Command Set 1 of 2 on page 93 and Table 54 Command Set 2 of 2 on page 94 All other registers required for the command must be set up before writ ing to the Command Register 10 3 Data Register This register is used to transfer data blocks between the device data buffer and the host It is also the register through which ...

Page 75: ...t least 5 ms before setting RST 0 IEN Interrupt Enable When IEN 0 and the device is selected the device interrupts to the host will be enabled When IEN 1 or the device is not selected the device interrupts to the host will be disabled 7 6 5 4 3 2 1 0 HIZ WTG H3 H2 H1 H0 DS1 DS0 Bit Definitions HIZ High Impedance This bit is not a device and will always be in a high impedance state WTG Write Gate T...

Page 76: ...y LBA mode DRV Device When DRV 0 device 0 Master is selected When DRV 1 device 1 Slave is selected HS3 HS2 HS1 HS0 These contain bits 24 27 of the LBA At command completion these bits are updated to reflect the current LBA bits 24 27 7 6 5 4 3 2 1 0 CRC UNC 0 IDNF 0 ABRT TK0N AMN ICRCE CRC Interface CRC Error CRC 1 indicates that a CRC error has occurred on the data bus during a Ultra DMA transfer...

Page 77: ...ten content contains LBA Bits 0 7 and the previous content contains Bits 24 31 10 11 LBA Mid Register This register contains Bits 8 15 At the end of the command this register is updated to reflect the current LBA Bits 8 15 When 48 bit addressing commands are used the most recently written content contains LBA Bits 8 15 and the previous content contains Bits 32 39 10 12 Sector Count Register This r...

Page 78: ... to 0 after the Status Register is read by the host DSC Device Seek Complete DSC 1indicates that a Seek has completed and the device head is settled over a track DSC is set to 0 by the device just before a Seek begins When an error occurs this bit is not changed until the Status Register is read by the host and at that time the bit again indi cates the current Seek complete status When the device ...

Page 79: ...oft reset Aborting Host interface o o Aborting Device operation 1 1 Initialization of hardware o x x Internal diagnostic o x x Starting spindle motor 6 x x Initialization of registers 2 o o o DASP handshake o o x PDIAG handshake o o o Reverting programmed parameters to default Number of CHS set by Initialize Device Parameters Multiple mode Write Cache Read look ahead ECC bytes Volatile max address...

Page 80: ...power on hard reset or the Execute Device Diagnostic command are shown in the table below Table 46 Default Register Values Register Default Value Error Diagnostic Code Sector Count 01h LBA Low 01h LBA Mid 00h LBA High 00h Device A0h Status 50h Alternate Status 50h Table 47 Diagnostic codes Code Description 01h No error detected 02h Formatter device error 03h Sector buffer error 04h ECC circuitry e...

Page 81: ...ice 0 clears the BSY bit whenever it is ready to accept commands Device 0 may assert DASP to indicate device activity If Device 1 is not present Device 0 does not Assert DASP at POR Soft Reset If Device 1 is present Device 0 shall read PDIAG to determine when it is valid to clear the BSY bit and whether Device 1 has reset without any errors otherwise Device 0 shall simply reset and clear the BSY b...

Page 82: ...mergency unload is intended to be invoked in rare situations Because this operation is inherently uncontrolled it is more mechanically stressful than a normal unload A single emergency unload operation is more stressful than 100 normal unloads Use of emergency unload reduces the start stop life of the drive at a rate at least 100 times faster than that of normal unload and may damage the drive 11 ...

Page 83: ... numbered from 1 to the maximum value allowed by the current CHS translation mode but cannot exceed 255 0FFh Heads are numbered from 0 to the maximum value allowed by the current CHS translation mode but cannot exceed 15 0Fh Cylinders are numbered from 0 to the maximum value allowed by the current CHS translation mode but cannot exceed 65535 0FFFFh When the host selects a CHS translation mode usin...

Page 84: ...ed to move a device out of sleep mode When a device exits sleep mode it will enter standby mode The Standby and Standby Immediate commands move a device to standby mode immediately from the active or idle modes The standby command also sets the standby timer count 11 6 3 Standby Sleep command completion time 1 Confirm the completion of writing cached data in the buffer to media 2 Unload the heads ...

Page 85: ... and the validity of INTRQ is guaranteed for two seconds after the Sleep command is completed After this period the contents of interface registers may be lost Since the contents of interface registers may be invalid the host should NOT check the Status register nor the Alternate Status register prior to issuing a soft reset to wake up a device 11 6 7 Initial Power Mode at Power On After power on ...

Page 86: ...sumption is 45 55 less than that of Performance Idle mode Additional electronics are powered off and the head is parked near the mid diameter of the disk without servoing Recovery time to Active mode is about 20 ms 11 7 3 Low Power Idle Mode Power consumption is 60 65 less than that of Performance Idle mode The heads are unloaded on the ramp but the spindle is still rotated at the full speed Recov...

Page 87: ... that particular device The specific set of attributes being used and the identity of these attributes is vendor specific and proprietary 11 8 2 Attribute values Attribute values are used to represent the relative reliability of individual performance or calibration attributes Higher attribute values indicate that the analysis algorithms being used by the device are predicting a lower proba bility...

Page 88: ...g security modes are provided 11 9 2 Security level The following security levels are provided Security Set Password F1 h Security Unlock F2 h Security Erase Prepare F3 h Security Erase Unit F4 h Security Freeze Lock F5 h Security Disable Password F6 h Device Locked Mode The device disables media access commands after power on Media access commands are enabled by either a Security Unlock command o...

Page 89: ...11 9 4 1 Master Password setting The system manufacturer or dealer can set an initial Master Password using the Security Set Password command without enabling the Device Lock Function 11 9 4 2 User Password setting When a User Password is set the device will automatically enter lock mode the next time the device is powered on Figure 2 Initial setting Master Password When the Master Password is set...

Page 90: ...rs to the commands in Table 51 Command table for device lock operation on page 78 POR Device Locked mode Unlock CMD Command 1 Command 1 Password Erase Unit Password Match Reject Complete Complete Erase Unit Lock function Disable Normal operation All commands are available Freeze Lock command Enter Device Frozen mode Normal Operation expect Set Password Disable Password Erase Unit Unlock commands E...

Page 91: ...NLOCK command has an attempt limit the purpose of which is to prevent someone from attempting to unlock the drive with various passwords numerous times The device counts the password mismatch If the password does not match the device counts it without distinguishing the Master password and the User password If the count reaches 5 EXPIRE bit bit 4 of Word 128 in Identify Device information is set a...

Page 92: ...o o o S M A R T Enable Disable automatic off line o o o Initialize Device Parameters o o o S M A R T Enable Disable Attribute Autosave o o o Read Buffer o o o S M A R T Enable Operations o o o Read DMA x o o S M A R T Exectue Off line Immdeiate o o o Read DMA EXT x o o S M A R T Read Attribute Values o o o Read Long x o o S M A R T Read Attribute Thresholds o o o Read Multiple x o o S M A R T Read...

Page 93: ...n tested to have a capacity of 536 MB flagging the media defects not visible by the system 2 Preparing drives at the system manufacturer Special utility software is required to define the size of the protected area and to store the data in it The sequence is as follows i Issue Read Native Max ADDRESS command to get the real device max of LBA CYL Returned value shows that native device Max LBA is 0...

Page 94: ... This command requests a transfer of a single sector of data from the host The following figure defines the content of this sector of information The password is retained by the device until the next power cycle When the device accepts this command the device is in Set Max Unlocked mode The Set Max LOCK command allows the host to disable the Set Max commands except Set Max UNLOCK and Set Max FREEZ...

Page 95: ...any commands which access sectors across the original native maximum LBA are rejected with error even if this protection is removed by a Set Max Address command 11 11 1 Enable Disable Address Offset Mode Subcommand code 09h Enable Address Offset Mode offsets address Cylinder 0 Head 0 Sector 1 LBA 0 to the start of the nonvolatile protected area established using the Set Max Address command The off...

Page 96: ...ntify Device data word 86 bit 7 indicates the device is in Address Offset mode 11 11 3 Exceptions in Address Offset Mode Any commands which access sectors across the original native maximum LBA are rejected with error even if the access protection is removed by a Set Max Address command Read Look Ahead operation and Write Cache Function are not carried out in Address Offset mode even if they are e...

Page 97: ...he number of seeks is large this overhead can be ignored Figure 7 Seek overlap 11 13 Write Cache function Write cache is a performance enhancement whereby the device reports completion of the write command Write Sector s and Write Multiple to the host as soon as the device has received all of the data in its buffer The device assumes responsibility to write the data subsequently onto the disk Writ...

Page 98: ...itions for auto reallocation are described below 11 14 1 1 Nonrecovered write errors When a write operation can not be completed after the Error Recovery Procedure ERP is fully carried out the sector s are reallocated to the spare location An error is reported to the host system only when the write cache is disabled and the auto reallocation fails If the number of available spare sectors reaches 1...

Page 99: ...content location The host may read the previous content of the Features the Sector Count the LBA Low Mid High registers by first setting the High Order Bit HOB bit 7 of the Device control register to one and then reading the desired register If HOB in the Device Control register is cleared to zero the host reads the most recently written content when the register is read A write to any Command Blo...

Page 100: ...Travelstar 7K100 Hard Disk Drive Specification 86 ...

Page 101: ...upts are cleared when the host reads the Status Register issues a reset or writes to the Command Register See Section 14 0 Time out values on page 197 for the device time out values 12 1 Data In commands The following are Data In commands Device Configuration Identify Identify Device Read Buffer Read Long Read Multiple Read Multiple EXT Read Sector s Read Sector s EXT S M A R T Read Attribute Valu...

Page 102: ... BSY 0 ERR 1 ABT 1 and inter rupting the host If an error occurs the device sets BSY 0 ERR 1 and DRQ 1 The device then stores the error status in the Error Register and interrupt the host The registers will contain the location of the sector in error The error location will be reported using CHS mode or LBA mode The mode is decided by the mode select bit bit 6 of the Device Head register upon issu...

Page 103: ...luding ECC bytes via the Data Register c The device sets BSY 1 after it has received the sector d After processing the sector of data the device sets BSY 0 and interrupts the host e In response to the interrupt the host reads the Status Register f The device clears the interrupt in response to the Status Register being read The Write Multiple command transfers one block of data for each interrupt ...

Page 104: ... S M A R T Enable Disable Automatic Off line S M A R T Enable Operations S M A R T Execute Off line Immediate S M A R T Return Status S M A R T Save Attribute Values Standby Standby Immediate Execution of these commands involves no data transfer a The host writes any required parameters to the Features Sector Count LBA High LBA Mid LBA Low and Device Registers b The host writes the command code to...

Page 105: ...r commands The host resets the DMA channel prior to reading status from the device The DMA protocol allows high performance multitasking operating systems to eliminate processor overhead asso ciated with PIO transfers 1 The host initializes the Slave DMA channel 2 The host writes any required parameters to the Features Sector Count LBA High LBA Mid LBA Low and Device registers 3 The host writes co...

Page 106: ...Travelstar 7K100 Hard Disk Drive Specification 92 ...

Page 107: ... 97 1 0 0 1 0 1 1 1 3 Idle Immediate E1 1 1 1 0 0 0 0 1 3 Idle Immediate 95 1 0 0 1 0 1 0 1 3 Initialize Device Parameters 91 1 0 0 1 0 0 0 1 1 Read Buffer E4 1 1 1 0 0 1 0 0 4 Read DMA C8 1 1 0 0 1 0 0 0 4 Read DMA C9 1 1 0 0 1 0 0 1 5 Read FPDMA Queued 60 0 1 1 0 0 0 0 0 4 Read DMA EXT 25 0 0 1 0 0 1 0 1 1 Read Long 22 0 0 1 0 0 0 1 0 1 Read Long 23 0 0 1 0 0 0 1 1 1 Read Multiple C4 1 1 0 0 0 1...

Page 108: ...ons B0 1 0 1 1 0 0 0 0 3 S M A R T Execute Off line Immediate B0 1 0 1 1 0 0 0 0 1 S M A R T Read Attribute Values B0 1 0 1 1 0 0 0 0 1 S M A R T Read Attribute Thresholds B0 1 0 1 1 0 0 0 0 1 S M A R T Read Log Sector B0 1 0 1 1 0 0 0 0 3 S M A R T Return Status B0 1 0 1 1 0 0 0 0 3 S M A R T Save Attribute Values B0 1 0 1 1 0 0 0 0 2 S M A R T Write Log Sector B0 1 0 1 1 0 0 0 0 3 Standby E2 1 1...

Page 109: ...Travelstar 7K100 Hard Disk Drive Specification 95 Protocol 1 PIO data IN command 3 Non data command Vendor specific command 2 PIO data OUT command 4 DMA command ...

Page 110: ...tomatic Off line B0 DB Set Features Enable Write Cache EF 02 Set Transfer mode EF 03 Enable Advanced Power Management feature EF 05 Enable Power Up in Standby feature EF 05 Power Up in Standby feature device Spin up EF 07 Enable Address Offset mode EF 09 52 bytes of ECC apply on Read Write Long EF 44 Disable read look ahead feature EF 55 Disable reverting to power on defaults EF 66 Disable write c...

Page 111: ... an input parameter Output registers 0 This indicates that the bit must be set to 0 1 This indicates that the bit must be set to 1 D The device number bit This indicates that the device number bit of the Device Register should be specified Zero selects the master device and one selects the slave device H Head number This indicates that the head number part of the Device Head Register is an output ...

Page 112: ...r if the spindle motor is at speed and the device is not in Standby or Sleep mode Other wise the Sector Count Register is set to 0 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count V V V V V V V V LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device 1 1 D Device Command 1 1 ...

Page 113: ...ce Con figuration Overlay settings After successful execution of a DEVICE CONFIGURATION FREEZE LOCK com mand all DEVICE CONFIGURATION SET DEVICE CONFIGURATION FREEZE LOCK DEVICE CONFIGURATION IDENTIFY and DEVICE CONFIGURATION RESTORE commands are aborted by the device The DEVICE CONFIGURATION FREEZE LOCK condition shall be cleared by a power down The DEVICE CONFIGURATION FREEZE LOCK condition shal...

Page 114: ...et If a bit is set in the overlay transmitted by the device that is not set in the overlay received from a DEVICE CONFIGURATION IDENTIFY command no action is taken for that bit The format of the overlay transmitted by the device is described in the table in Table 59 Device Configuration Overlay Data structure on page 101 The restrictions on changing these bits is described in the text following th...

Page 115: ...ow are supported 3 1 Ultra DMA mode 3 and below are supported 2 1 Ultra DMA mode 2 and below are supported 1 1 Ultra DMA mode 1 and below are supported 0 1 Ultra DMA mode 0 is supported 3 6 Maximum LBA address 7 Command set feature set supported 15 9 Reserved 8 1 48 bit Addressing feature set supported 7 1 Host Protected Area feature set supported 6 1 Automatic acoustic management supported 5 Rese...

Page 116: ...o this command Instead the register contains a diagnostic code See Table 47 Diagnostic codes on page 66 for the definition Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device 1 1 Device Command 1 0 0 1 0 0 0 0 Status see bel...

Page 117: ...s written to the disk media Return a successful completion Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device 1 1 D Device Command 1 1 1 0 0 1 1 1 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 ...

Page 118: ...ster 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current Sector Count HOB 0 Previous HOB 1 LBA Low Current LBA Low HOB 0 Previous HOB 1 LBA Mid Current LBA Mid HOB 0 Previous HOB 1 LBA High Current LBA High HOB 0 Previous HOB 1 Device Head D Device Head Command 1 1 1 0 1 0 1 0 Status See below Error Register S...

Page 119: ...BA mode this reg ister specifies that LBA address bits 24 27 are to be formatted L 1 Input parameters from the device LBA Low In LBA mode this register specifies the current LBA address bits as 0 7 L 1 LBA High Mid In LBA mode this register specifies the current LBA address bits as 8 15 Mid and bits 16 23 High H In LBA mode this register specifies the current LBA address bits as 24 27 L 1 In LBA m...

Page 120: ...be completed immediately prior to the Format Unit command If the device receives a Format Unit command without a prior Security Erase Prepare command the device aborts the Format Unit command If the Feature register is NOT 11h the device returns an Abort error to the host This command does not request a data transfer Output parameters to the device Feature The Destination code for this command 11H...

Page 121: ... in Table 67 Identify device information Part 1 of 7 on page 108 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device 1 1 D Device Command 1 1 1 0 1 1 0 0 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 ...

Page 122: ...e 1 1 1 hard sectored 0 0 Reserved 01 Note 1 Number of cylinders in default translate mode 02 xxxxH Specific configuration C837h SET FEATURES subcommand is not required to spin up and IDENTIFY DEVICE response is complete 37C8h SET FEATURES subcommand is required to spin up and IDENTIFY DEVICE response is complete 03 Note 1 Number of heads in default translate mode 04 05 0 Reserved 06 003FH Number ...

Page 123: ...ng mode Refer Word 62 and 63 53 0007H Validity flag of the word 15 3 0 Reserved 2 1 1 Word 88 is Valid 1 1 1 Word 64 70 are Valid 0 1 1 Word 54 58 are Valid 54 XXXXH Number of current cylinders 55 XXXXH Number of current heads 56 XXXXH Number of current sectors per track 57 58 XXXXH Current capacity in sectors Word 57 specifies the low word of the capacity 59 0XXXH Current Multiple setting Bit ass...

Page 124: ...e time in nanoseconds 240 ns 8 3 MB s 68 0078H Minimum PIO Transfer Cycle Time With IORDY Flow Control 15 0 78h Cycle time in nanoseconds 120 ns 16 6 MB s 69 79 0000H Reserved 80 007CH Major version number ATA 1 2 3 and ATA ATAPI 4 5 6 81 0019 Minor version number ATA ATAPI 6 T13 1410D Revision 3a 82 746BH Command set supported 15 0 Reserved 14 1 1 NOP command supported 13 1 1 READ BUFFER command ...

Page 125: ... Feature Set supported 3 1 1 Advanced Power Management Feature Set supported 2 0 1 CFA Feature Set supported 1 0 1 READ WRITE DMA QUEUED supported 0 0 1 DOWNLOAD MICROCODE command supported 84 4023H Command set feature supported extension 15 0 Always 14 1 Always 13 6 0 Reserved 5 1 1 General Purpose Logging feature set supported 4 2 0 Reserved 1 1 1 SMART self test supported 0 1 1 SMART error logg...

Page 126: ... Power management Feature Set enabled 2 0 1 CFA Feature Set supported 1 0 1 READ WRITE DMA QUEUED command supported 0 0 1 DOWNLOAD MICROCODE command supported 87 4023H Command set feature enabled 15 0 Always 14 1 Always 13 6 0 Reserved 5 1 1 General Purpose Logging feature set supported 4 2 0 Reserved 1 1 1 SMART self test supported 0 1 1 SMART error logging supported 88 XX3FH Ultra DMA Transfer m...

Page 127: ...How Device 1 determined the device number 00 Reserved 01 a jumper was used 10 the CSEL signal was used 11 some other method used or method unknown 8 1 Always 7 0 Device 0 hardware reset result Device 1 clears these bits to 0 7 0 Reserved 6 X 1 Semi duplex mode is enabled 5 X 1 Device 0 detected Device 1 4 X 1 Device 1 passed diagnostic 3 X 1 Device 0 passed diagnostic 2 1 X how Device 0 determined...

Page 128: ...e supported 4 0 1 Security count expired 3 0 1 Security Frozen 2 0 1 Security Locked 1 0 1 Security Enabled 0 0 1 Security Support 129 000XH Current Set Feature Option Bit assignments 15 4 0 Reserved 3 X 1 Auto reassign enabled 2 X 1 Reverting enabled 1 X 1 Read Look ahead enabled 0 X 1 Write Cache enabled 130 XXXXH Reserved 131 000XH Initial Power Mode Selection Bit assignments 15 2 0 Reserved 1 ...

Page 129: ...10G9AT00 Number of cylinders 3FFFh Number of heads 10h Buffer size 3AE6h Total number of user addressable sectors BA52230h Microcode revision MCxOAxxx HTS721080G9AT00 Number of cylinders 3FFFh Number of heads 10h Buffer size 3AE6h Total number of user addressable sectors 950F8B0h Microcode revision MCxOAxxx HTS721060G9AT00 Number of cylinders 3FFFh Number of heads 10h Buffer size 3AE6h Total numbe...

Page 130: ...nput parameters to the device Sector Count This indicates the Time out Parameter If it is zero the time out interval Standby Timer is disabled If it is other than zero the time out interval is set for Time out Parameter 5 seconds The device will enter Standby mode automatically if the time out interval expires with no device access from the host The time out interval will be reinitialized if there...

Page 131: ... to respond to the host commands immediately The Idle Immediate command will not affect the auto power down time out parameter Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device 1 1 D Device Command 1 1 1 0 0 0 0 1 Status s...

Page 132: ...on of CCh is set Output parameters to the device Sector Count This indicates the number of sectors per track Zero 0 indicates 0 sectors per track instead of 256 sectors per track It means that there are no sectors per track H This indicates the number of heads minus 1 per cylinder The minimum is 0 and the maxi mum is 15 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 ...

Page 133: ...ffer command The contents of the sector may be different if any reads or writes have occurred since the Write Buffer command was issued Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device 1 1 D Device Command 1 1 1 0 0 1 0 0...

Page 134: ...t sector to be transferred L 0 In LBA mode this register specifies that LBA address bits 0 7 are to be transferred L 1 LBA High Mid This indicates the cylinder number of the first sector to be transferred L 0 In LBA mode this register specifies LBA address bits 8 15 Mid and 16 23 High to be transferred L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode this ...

Page 135: ...ndicates the sector number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 0 7 L 1 LBA High Low This indicates the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Mid and bits16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode this register contains...

Page 136: ...ts 15 8 If 0000h in the Sector Count register is specified 65 536 sectors will be transferred LBA Low Current LBA 7 0 LBA Low Previous LBA 31 24 LBA Mid Current LBA 15 8 LBA Mid Previous LBA 39 32 LBA High Current LBA 23 16 LBA High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High...

Page 137: ...A Low HOB 1 LBA 31 24 of the address of the first unrecoverable error LBA Mid HOB 0 LBA 15 8 of the address of the first unrecoverable error LBA Mid HOB 1 LBA 39 32 of the address of the first unrecoverable error LBA High HOB 0 LBA 23 16 of the address of the first unrecoverable error LBA High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 138: ...linder Low Current The first sector of the log to be read low order bits 7 0 Cylinder Low Previous The first sector of the log to be read high order bits 15 8 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector Count H...

Page 139: ...rror log SMART error logging Ready Only 06h SMART self test log SMART self test See Note 07h Extended SMART self test log SMART self test Read Only 20h Streaming Performance log Streaming Read Only 21h Write Stream Error log Streaming Read Only 22h Read Stream Error log Streaming Read Only 80h 9Fh Host vendor specific SMART Read Write Description Bytes Offset General purpose logging version 2 00h ...

Page 140: ...cleared to 0 Valid values for the error log index are 0 to 4 13 15 2 3 Extended Error log data structure An error log data structure shall be presented for each of the last four errors reported by the device These error log data structure entries are viewed as a circular buffer The fifth error shall create an error log structure that replaces the first error log data structure The next error after...

Page 141: ...ror log data structure 18 48h Error data structure 34 5Ah 124 Description Bytes Offset Device Control register 1 00h Features register 7 0 see Note 1 01h Features register 15 8 1 02h Sector count register 7 0 1 03h Sector count register 15 8 1 04h Sector number register 7 0 1 05h Sector number register 15 8 1 06h Cylinder Low register 7 0 1 07h Cylinder Low register 15 8 1 08h Cylinder High regist...

Page 142: ...not implemented by the device or requests with invalid parameters or invalid addresses If the maximum value for this field is reached the count shall remain at the maximum value when additional errors are encountered and logged 13 15 3 Extended Self test log sector The figure below defines the format of each of the sectors that comprise the Extended SMART self test log Description Bytes Offset Res...

Page 143: ... 2 Self test descriptor index This indicates the most recent self test descriptor If there have been no self tests this is set to zero Valid values for the Self test descriptor index are 0 to 18 13 15 3 3 Extended Self test log descriptor entry The content of the self test descriptor entry is shown below Description Bytes Offset Self test log data structure revision number 1 00h Reserved 1 01h Sel...

Page 144: ...LBA Low This indicates the sector number of the sector to be transferred L 0 In LBA mode this register contains LBA bits 0 7 L 1 LBA High Mid This indicates the cylinder number of the sector to be transferred L 0 In LBA mode this register contains LBA bits 8 15 Low 16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode this register contains LBA bits 24 27 ...

Page 145: ...de this register contains current LBA bits 8 15 Low 16 23 High L 1 H This indicates the head number of the transferred sector L 0 In LBA mode this register contains current LBA bits 24 27 L 1 The device internally uses 40 bytes of ECC data on all data written or read from the disk The 4 byte mode of oper ation is provided by means of an emulation Use of the 40 byte ECC mode is recommended for test...

Page 146: ... L 0 In LBA mode this register contains LBA bits 8 15 Mid 16 23 High L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode this register contains LBA bits 24 27 L 1 Input parameters from the device Sector Count This indicates the number of requested sectors not transferred This number is zero unless an unrecoverable error occurs LBA Low This indicates the secto...

Page 147: ...indicates the cylinder number of the last transferred sector L 0 In LBA mode this register contains current LBA bits 8 15 Mid 16 23 High L 1 H This indicates the head number of the last transferred sector L 0 In LBA mode this register contains current LBA bits 24 27 L 1 ...

Page 148: ...s of the first unrecoverable error LBA High HOB 0 LBA 23 16 of the address of the first unrecoverable error LBA High HOB 1 LBA 47 40 of the address of the first unrecoverable error Table 90 Read Multiple EXT 29h Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previou...

Page 149: ...gister contains the native max LBA bits 0 7 L 1 In CHS mode this register contains the native max LBA Low L 0 LBA High Mid In LBA mode this register contains the native max LBA bits 8 15 Mid and bits 16 23 High L 1 In CHS mode this register contains the native max cylinder number L 0 H In LBA mode this register contains the native max LBA bits 24 27 L 1 In CHS mode this register contains the nativ...

Page 150: ...e max areas LBA High HOB 1 LBA 47 40 of the address of the Native max areas Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current Sector Count HOB 0 Previous HOB 1 LBA Low Current LBA Low HOB 0 V V V V V V V V Previous HOB 1 V V V V V V V V LB...

Page 151: ... the retry bit this bit is ignored Input parameters from the device Sector Count This is the number of requested sectors not transferred This will be zero unless an unre coverable error occurs LBA Low This is the sector number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 0 7 L 1 LBA High Low This is the cylinder number of the last transferred sector L ...

Page 152: ...Low Previous LBA 31 24 LBA Mid Current LBA 15 8 LBA Mid Previous LBA 39 32 LBA High Current LBA 23 16 LBA High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector Count HOB 0 Previous V V V V V V V V...

Page 153: ...A Low HOB 1 LBA 31 24 of the address of the first unrecoverable error LBA Mid HOB 0 LBA 15 8 of the address of the first unrecoverable error LBA Mid HOB 1 LBA 39 32 of the address of the first unrecoverable error LBA High HOB 0 LBA 23 16 of the address of the first unrecoverable error LBA High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 154: ...LBA mode this register contains the LBA bits 8 15 Mid and bits 16 23 High L 1 H This is the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This is the retry bit this bit is ignored Input parameters from the device Sector Count This is the number of requested sectors not transferred This number will be zero unless an unrecoverable e...

Page 155: ...s the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Mid and bits 16 23 High L 1 H This is the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 156: ... transferred LBA Low Current LBA 7 0 LBA Low Previous LBA 31 24 LBA Mid Current LBA 15 8 LBA Mid Previous LBA 39 32 LBA High Current LBA 23 16 LBA High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Se...

Page 157: ...A Low HOB 1 LBA 31 24 of the address of the first unrecoverable error LBA Mid HOB 0 LBA 15 8 of the address of the first unrecoverable error LBA Mid HOB 1 LBA 39 32 of the address of the first unrecoverable error LBA High HOB 0 LBA 23 16 of the address of the first unrecoverable error LBA High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 158: ...l be set in the Error Register Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device 1 1 D Device Command 0 0 0 1 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY ...

Page 159: ...nformation for Security Disable Password command The device will compare the password sent from this host with that specified in the control word Identifier Zero indicates that the device should check the supplied password against the user pass word stored internally One indicates that the device should check the given password against the master password stored internally Command Block Output Reg...

Page 160: ...mmand This com mand is to prevent accidental erasure of the device This command does not request the transfer of data Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device 1 1 D Device Command 1 1 1 1 0 0 1 1 Status see below ...

Page 161: ...disables the security mode feature device lock func tion After completing of this command all the user data will be initialized to zero with a write operation At this time the data write is not verified with a read operation to determine if the data sector is initialized correctly At this time the defective sector information and the reassigned sector information for the device are not updated The...

Page 162: ...nd may be reactivated later when a new user password is set If you execute this command on disabling the security mode feature device lock function the password sent by the host is NOT compared with the Master Password and the User Password The device only erases all user data The execution time of this command is shown below HTS721010G9AT00 70 min HTS721080G9AT00 52 min HTS721060G9AT00 40 min ...

Page 163: ...ice is in frozen mode Refer to Table 51 Command table for device lock operation on page 78 Security Set Password Security Unlock Security Disable Password Security Erase Unit Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Devi...

Page 164: ...nction of this command Table 105 Security Set Password information Identifier Zero indicates that the device should check the supplied password against the user password stored internally One indicates that the device should check the given password against the master password stored internally Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3...

Page 165: ... The setting of the Identifier and Security level bits interact as follows Identifier User Security level High The password supplied with the command will be saved as the new user password The security mode feature lock function will be enabled from the next power on The drive may then be unlocked by either the user password or the previously set master password Identifier Master Security level Hi...

Page 166: ...d is decremented for each password mismatch When this counter reaches zero all password protected commands are rejected until there is a hard reset or a power off Identifier A zero indicates that the device regards Password as the User Password A one indicates that the device regards Password as the Master Password The user can detect if the attempt to unlock the device has failed due to a mismatc...

Page 167: ...or seek L 1 Input parameters from the device LBA Low In LBA mode this register contains the current LBA bits 0 7 L 1 LBA High Mid In LBA mode this register contains the current LBA bits 8 15 Mid and bits 16 23 High L 1 H In LBA mode this register contains the current LBA bits 24 27 L 1 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Da...

Page 168: ...nput parameters from the device Sector Count The Sector Count register contains result value Value Description 00h Temperature is equal to or lower than 20 C 01h FEh Temperature is Value 2 20 C FFh Temperature is higher than 107 C N Not recommendable condition for start up If over stressed condition is detected this bit will be set to one Command Block Output Registers Command Block Input Register...

Page 169: ...A High LBA High Device 1 1 D Device Command 1 1 1 0 1 1 1 1 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 0 V Write cache Enable ECC bytes 4 bytes Read look ahead Enable Reverting to power on defaults Disable Address Offset mode Disable Feature Destination code for this command 02H En...

Page 170: ...Identify Device command Hard reset or power off must not be done during the first 5 seconds after write command completion when write cache is enabled Note 3 When the Feature register is 85h Disable Advanced Power Management the deepest Power Saving mode becomes Active Idle 86H Disable Power Up in Standby feature set 89H Disable Address Offset mode AAH Enable read look ahead feature BBH 4 bytes of...

Page 171: ...E and LBA Low are ignored The default value see default CHS in Identify device information is used for that In LBA mode the Head number of Device LBA High LBA Mid and LBA Low specify the max LBA This com mand sets this LBA as the max LBA of the device After a successful command completion Identify Device response words 61 60 shall reflect the maximum address set with this command If the 48 bit Add...

Page 172: ...is register is ignored L 0 LBA High Mid In LBA mode this register contains LBA bits 8 15 Mid 16 23 High which is to be set L 1 In CHS mode this register contains max cylinder number which is to be set L 0 H In LBA mode this register contains LBA bits 24 27 which are to be input L 1 In CHS mode this register is ignored L 0 L This indicates the LBA addressing mode L 0 specifies the CHS mode and L 1 ...

Page 173: ... Address Ext command or the device is in the Set Max Locked or Set Max Frozen state the device shall return command aborted If the device in Address Offset mode receives this command with the nonvolatile option the device returns aborted error to the host The device returns the command aborted for a second non volatile Set Max Address Ext command until next power on or hardware reset Command Block...

Page 174: ...mmand will be lost by POR B 1 is not valid when the device is in Address Offset mode LBA Low Current Set Max LBA 7 0 LBA Low Previous Set Max LBA 31 24 LBA Mid Current Set Max LBA 15 8 LBA Mid Previous Set Max LBA 39 32 LBA High Current Set Max LBA 23 16 LBA High Previous Set Max LBA 47 40 Input parameters from the device LBA Low HOB 0 Set Max LBA 7 0 LBA Low HOB 1 Set Max LBA 31 24 LBA Mid HOB 0 ...

Page 175: ...l tiple commands will be disabled Output parameters to the device Sector Count This indicates the block size to be used for the Read Multiple and the Write Multiple com mands Valid block sizes can be selected from 0 2 4 8 or 16 If 0 is specified the Read Multiple and the Write Multiple commands are disabled Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Regis...

Page 176: ...set The use of hardware reset to recover from Sleep Mode may be incompatible with continued operation of the host system If the device is already spun down the spin down sequence is not executed Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LB...

Page 177: ...re listed below Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature V V V V V V V V Error see below Sector Count V V V V V V V V Sector Count LBA Low LBA Low LBA Mid 0 1 0 0 1 1 1 1 LBA Mid LBA High 1 1 0 0 0 0 1 0 LBA High Device 1 1 D Device Command 1 0 1 1 0 0 0 0 Status see below Error Register Status Register 7 6 5 4...

Page 178: ...re to be disabled The state of the Attribute Autosave feature either enabled or disabled will be preserved by the device across the power cycle A value of 00h written by the host into the device s Sector Count Register before issuing the S M A R T Enable Disable Attribute Autosave subcommand will cause this feature to be disabled Disabling this feature does not preclude the device from saving Attr...

Page 179: ...e plus a selectable read scan The host shall not write the Selective self test log while the execution of a Selective self test command is in progress The user may choose to do read scan only on specific areas of the media To do this user shall set the test spans desired in the Selective self test log and set the flags in the Feature flags field of the Selective self test log to indi cate do not p...

Page 180: ...the scan shall be delayed the time indicated in the Selective self test pending time field in the Selective self test log During this delay time the pending flag shall be set to one and the active flag shall be set to zero in the Selective self test log Once the time expires the active flag shall be set to one and the off line scan shall resume When the entire media has been scanned the off line s...

Page 181: ...sables all S M A R T capabilities within the device including the device s attribute auto save feature After receipt of this subcommand the device disables all S M A R T operations Non self preserved Attribute Values will no longer be monitored The state of S M A R T either enabled or disabled is preserved by the device across power cycles Note that this subcommand does not preclude the device s p...

Page 182: ...y the feature to be enabled or disabled A value of zero written by the host into the device s Sector Count register before issuing this subcommand shall cause the automatic off line data collection feature to be disabled Disabling this feature does not preclude the device from saving attribute values to nonvolatile memory during some other normal operation such as during a power on during a power ...

Page 183: ...ich version of this data structure is implemented by the device This revision number will be set to 0005h This revision number identifies both the Attribute Value and Attribute Threshold Data structures Description Byte Offset Format Value Data Structure Revision Number 2 00h binary 0010h 1st Device Attribute 12 02h 1 2 30th Device Attribute 12 15Eh 1 2 Off line data collection status 1 16Ah 1 2 S...

Page 184: ...Value valid values from 01h to FEh 1 03h binary 00h invalid for attribute value not to be used 01h minimum value 64h initial value for all attributes prior to any data collection FDh maximum value FEh value is not valid FFh invalid for attribute value not to be used Reserved may not be 0 1 04h binary Reserved may not be 0 6 05h binary Reserved 00h 1 0Bh binary Total Bytes 12 ID Attribute Name 0 In...

Page 185: ...c Off line Data Collection Status Bit 7 Automatic Off line Data Collection Status 0 Automatic Off line Data Collection is disabled 1 Automatic Off line Data Collection is enabled Bits 0 6 represent a hexadecimal status value reported by the device Value Definition 0 Off line data collection never started 2 All segments completed without errors In this case the current segment pointer is equal to t...

Page 186: ...s implemented 2 Abort restart off line by host bit 0 The device will suspend off line data collection activity after an interrupting command and resume it after a vendor specific event 1 The device will abort off line data collection activity upon receipt of a new command Bit Definition 0 3 Percent Self test remaining An approximation of the percent of the self test routine remaining until complet...

Page 187: ...the S M A R T ENABLE DISABLE ATTRIBUTE AUTOSAVE command Bit Definition 0 Pre power mode attribute saving capability If bit 1 the device will save its Attribute Values prior to going into a power saving mode Standby or Sleep mode 1 Attribute auto save capability If bit 1 the device supports the S M A R T ENABLE DISABLE ATTRIBUTE AUTOSAVE command 2 15 Reserved 0 13 39 2 9 Error logging capability Bi...

Page 188: ... Structure 13 39 3 2 Individual Thresholds Data Structure The following defines the 12 bytes that make up the information for each Threshold entry in the Device Attribute Thresholds Data Structure Attribute entries in the Individual Threshold Data Structure are in the same order and correspond to the entries in the Individual Attribute Data Structure Description Byte Offset Format Value Data Struc...

Page 189: ...bute Threshold These values are preset at the factory and are not meant to be changeable However the host might use the S M A R T Write Attribute Threshold subcommand to override these preset values in the Threshold sectors 13 39 3 5 Data Structure Checksum The Data Structure Checksum is the 2 s compliment of the result of a simple 8 bit addition of the first 511 bytes in the data structure ...

Page 190: ... M A R T error log version This value is set to 01h 13 39 5 2 Error log pointer This points to the most recent error log data structure Only values 1 through 5 are valid 13 39 5 3 Device error count This field contains the total number of errors The value will not roll over Description Bytes Offset S M A R T Logging Version 2 00h Number of sectors in the log at log address 1 1 02h Reserved 1 03h N...

Page 191: ...cture Description Byte Offset 1st command data structure 12 00h 2nd command data structure 12 0Ch 3rd command data structure 12 18h 4th command data structure 12 24h 5th command data structure 12 30h Error data structure 30 3Ch 90 Description Byte Offset Device Control register 1 00h Features register 1 01h Sector count register 1 02h LBA Low register 1 03h LBA Mid register 1 04h LBA High register...

Page 192: ...cription Byte Offset Reserved 1 00h Error register 1 01h Sector count register 1 02h LBA Low register 1 03h LBA Mid register 1 04h LBA High register 1 05h Device register 1 06h Status register 1 07h Extended error data vendor spe cific 19 08h State 1 1Bh Life time stamp hours 2 1Ch 30 Value State x0h Unknown x1h Sleep x2h Standby x3h Active Idle x4h S M A R T Off line or Self test x5h xAh Reserved...

Page 193: ... and read by the host This log allows the host to select the parameters for the self test and to monitor the progress of the self test The following table defines the contents of the Selective self test log which is 512 bytes long All multi byte fields shown in these data structures follow the specifications for byte ordering Description Byte Offset Data structure revision 2 00h Self test number 1...

Page 194: ...a structure checksum 1 1FFh R W 512 Error condition Status Register Error Register A S M A R T FUNCTION SET command was received by the device without the required key being loaded into the LBA High and LBA Mid registers 51h 04h A S M A R T FUNCTION SET command was received by the device with a subcommand value in the Features Regis ter that is either invalid or not supported by this device 51h 04...

Page 195: ...ameters to the device Sector Count The Time out Parameter It is is zero the time out interval Standby Timer is disabled If it is other than zero the time out interval is set for Time out Parameter 5 seconds When the automatic power down sequence is enabled the device will enter the Standby mode automatically if the time out interval expires with no device access from the host The time out interval...

Page 196: ...xecuted During the Standby mode the device will respond to commands however there will be a delay while waiting for the spindle to reach operating speed The Standby Immediate command will not affect the auto power down time out parameter Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sect...

Page 197: ...nized such that sequential Write Buffer and Read Buffer commands access the same 512 byte within the buffer Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device 1 1 D Device Command 1 1 1 0 1 0 0 0 Status see below Error Regi...

Page 198: ...s register contains the LBA bits 0 7 L 1 LBA High Mid This indicates number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 8 15 Mid and bits 16 23 High L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This indicates the retry bit but this bit is ignored Input paramet...

Page 199: ...gister contains the current LBA bits 0 7 L 1 LBA High Mid This indicates the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Mid and bits 16 23 High L 1 H This indicates the head number of the last transferred sector L 0 LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 200: ...o be transferred high order bits 15 8 If zero is speci fied in the Sector Count register then 65 536 sectors will be transferred LBA Low Current LBA 7 0 LBA Low Previous LBA 31 24 LBA Mid Current LBA 15 8 LBA Mid Previous LBA 39 32 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Err...

Page 201: ...irst unrecoverable error LBA Low HOB 1 LBA 31 24 of the address of the first unrecoverable error LBA Mid HOB 0 LBA 15 8 of the address of the first unrecoverable error LBA Mid HOB 1 LBA 39 32 of the address of the first unrecoverable error LBA High HOB 0 LBA 23 16 of the address of the first unrecoverable error LBA High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 202: ...ector of the log to be written low order bits 7 0 Cylinder Low Previous The first sector of the log to be written high order bits 15 8 If the feature set associated with the log specified in the Sector Number register is not supported or enabled or if the values in the Sector Count Sector Number or Cylinder Low registers are invalid the device shall return com mand aborted If the host attempts to ...

Page 203: ... 1 LBA High Mid This indicates the cylinder number of the sector to be transferred L 0 In LBA mode this register contains the LBA bits 8 15 Mid and bits 16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R The retry bit but this bit is ignored Input parameters from the device Sector Count This indicates the ...

Page 204: ...e sector to be transferred L 0 In LBA mode this register contains current the LBA bits 24 27 L 1 The drive internally uses 40 bytes of ECC on all data read or writes The 4 byte mode of operation is provided via an emulation technique As a consequence of this emulation it is recommended that 40 byte ECC mode is used for all tests to confirm the operation of the ECC hardware of the drive Unexpected ...

Page 205: ...n LBA mode this register contains the LBA bits 24 27 L 1 Input parameters from the device Sector Count This indicates the number of requested sectors not transferred The Sector Count will be zero unless an unrecoverable error occurs LBA Low This indicates the sector number of the last transferred sector L 0 In LBA mode this register contains current the LBA bits 0 7 L 1 LBA High Mid This indicates...

Page 206: ...ll be transferred LBA Low Current LBA 7 0 LBA Low Previous LBA 31 24 LBA Mid Current LBA 15 8 LBA Mid Previous LBA 39 32 LBA High Current LBA 23 16 LBA High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V...

Page 207: ...A Low HOB 1 LBA 31 24 of the address of the first unrecoverable error LBA Mid HOB 0 LBA 15 8 of the address of the first unrecoverable error LBA Mid HOB 1 LBA 39 32 of the address of the first unrecoverable error LBA High HOB 0 LBA 23 16 of the address of the first unrecoverable error LBA High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 208: ... 15 Mid and bits 16 23 High L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This indicates the retry bit this bit is ignored Input parameters from the device Sector Count This indicates the number of requested sectors not transferred The Sector Count will be zero unless an unrecoverable error occurs LBA Low ...

Page 209: ...s the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Mid and bits 16 23 High L 1 H This indicates the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 210: ... Low Previous LBA 31 24 LBA Mid Current LBA 15 8 LBA Mid Previous LBA 39 32 LBA High Current LBA 23 16 LBA High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector Count HOB 0 Previous V V V V V V V ...

Page 211: ...ble error LBA Mid HOB 1 LBA 39 32 of the address of the first unrecoverable error LBA High HOB 0 LBA 23 16 of the address of the first unrecoverable error LBA High HOB 1 LBA 47 40 of the address of the first unrecoverable error 13 51 Write Verify 3Ch vendor specific In the implementation of the drive the Write Verify command is exactly the same as the Write Sectors command 30h Read verification is...

Page 212: ...Travelstar 7K100 Hard Disk Drive Specification 198 ...

Page 213: ...us RESET Signal Asserted Status Register BSY 1 400 ns Device Ready After Hard Reset Bus RESET Signal Asserted Status Register BSY 0 and RDY 1 31 sec Data In Com mand Device Busy After Com mand Code Out OUT To Command Register Status Register BSY 1 400 ns Interrupt DRQ For Data Transfer In Status Register BSY 1 Status Register BSY 0 and DRQ 1 Interrupt 30 sec Device Busy After Data Transfer In 256t...

Page 214: ... FORMAT UNIT command the execution time is referred to 13 7 Format Unit F7h vendor specific on page 105 Note 3 When the initial power mode at power on is Standby mode and when the following commands are issued by the host as First Command the command s time out value of the field is 10 seconds Security Disable Password Security Erase Unit Security Set Password Security Unlock ...

Page 215: ...ECTOR S Yes Mandatory 31h WRITE SECTOR S Yes Obsoleted 32h WRITE LONG Yes Obsoleted 33h WRITE LONG Yes Obsoleted 38h CFA TRANSLATE SECTORS W O ERASE No Optional Note 7 3Ch WRITE VERIFY 2 Vendor specific Obsoleted 40h READ VERIFY SECTOR S Yes Mandatory 41h READ VERIFY SECTOR S Yes Obsoleted 50h FORMAT TRACK Yes Obsoleted 7xh SEEK Yes Mandatory 87h CFA TRANSLATE SECTORS No Optional 90h EXECUTE DEVIC...

Page 216: ...E0h STANDBY IMMEDIATE Yes Mandatory E1h IDLE IMMEDIATE Yes Mandatory E2h STANDBY Yes Mandatory E3h IDLE Yes Mandatory E4h READ BUFFER Yes Optional E5h CHECK POWER MODE Yes Mandatory E6h SLEEP Yes Mandatory E7h FLUSH CACHE Yes Mandatory E8h WRITE BUFFER Yes Optional ECh IDENTIFY DEVICE Yes Mandatory EDh MEDIA EJECT No Optional Note 7 EEh IDENTIFY DEVICE DMA No Obsoleted EFh SET FEATURES Yes Mandato...

Page 217: ... Advanced Power Management Yes 06h Enable Power Up in Standby feature set 07h Power Up in Standby feature set device spin up 09h Enable Address Offset mode Yes 42h Enable Automatic Acoustic Management feature set 44h Set vendor specific bytes ECC Yes 55h Disable read look ahead feature Yes 5Dh Enable release interrupt No 5Eh Enable SERVICE interrupt No 66h Disable reverting to power on defaults Ye...

Page 218: ...Travelstar 7K100 Hard Disk Drive Specification 202 15 3 Changes from the Travelstar 5K100 The changes between the Travelstar 7K100 and the Travelstar 5K100 are listed below Product ID Time to format ...

Page 219: ...ions 93 Command overhead 13 Command protocol 87 Command table 78 Commands Support Coverage 199 Conductive noise 23 Control electronics 9 Corrosion test 22 CSA approval 34 C TICK mark 33 Cylinder allocation 12 Cylinders heads sectors by model 114 D Data 11 Data In commands 87 Data Out Commands 88 Data Reliability 25 Data sheet 11 DC power requirements 24 Deviations from standard 57 Device Configura...

Page 220: ...6 Environment 21 Execute Device Diagnostic 101 F Failure prediction S M A R T 25 Features Register 63 Fixed disk subsystem 9 Fixed disk subsystem description 9 Flammability 34 Flush Cache 102 Format Track 104 Format Unit 105 H Head disk assembly data 9 Humidity 21 I Identify Device 106 Idle 115 Idle Immediate 116 IEC compliance 34 Interface connector 35 L Labels Identification 33 Latency average 1...

Page 221: ...ing 34 Performance characteristics 13 Physical cylinders 12 PIO timings 41 Power consumption effiency 24 Power management commands 70 Power management features 70 Power off considerations 68 Power Off Sequence 26 Preventive maintenance 25 Protected Area Function 79 R Radiation noise 23 Read Buffer 118 Read DMA 119 Read DMA EXT 121 Read Long 129 Read Native Max ADDRESS 134 Read Sectors 136 Read Ver...

Page 222: ...assword 144 Security Erase Unit 146 Security Set Password 149 Security Unlock 151 Seek 152 Seek Overlap 83 Seek time average 14 full stroke 14 single track 15 Sense Condition 153 Service life 25 Set Features 154 Set Max ADDRESS 156 Set Max ADDRESS EXT 158 Set Multiple 160 shock 30 Signal definitions 36 Signal descriptions 37 Sleep 161 Sound power levels 32 Specification 21 Standby 180 Standby time...

Page 223: ...Transition time 72 U UL approval 34 V Vibration 30 W Write Buffer 182 Write Cache function 83 Z Zone 12 ...

Page 224: ......

Page 225: ...gistered trade marks of their respective companies References in this publication to Hitachi Global Storage Technologies products programs or services do not imply that Hitachi Global Storage Technologies intends to make these available in all countries in which Hitachi Global Storage Technologies operates Product information is provided for information pur poses only and does not constitute a war...

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