GOWIN DK-START-GW2A55-PG484 User Manual Download Page 25

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3 Development Board Circuit

3.7 LVDS Interfaces

DBUG375-1.0E

16(40)

3.6.2

Pinout

Table 3-5 Ethernet Pinout

Name

FPGA Pin No. BANK

I/O Level

Description

PHY_MDC

H19

3.3V

Manage channel clock

PHY_MDIO

J18

3.3V

Manage channel data

PHY1_GTCLK

H21

3.3V

PHY1 Transmit Clock

PHY1_TXD0

H22

3.3V

PHY1 transmitting data channel 0

PHY1_TXD1

G21

3.3V

PHY1 transmitting data channel 1

PHY1_TXD2

G22

3.3V

PHY1 transmitting data channel 2

PHY1_TXD3

F21

3.3V

PHY1 transmitting data channel 3

PHY1_TX_EN

F22

3.3V

PHY1 transmitting data enable

PHY1_RXC

E22

3.3V

PHY1 receiving clock

PHY1_RXD0

D22

3.3V

PHY1 receiving data channel 0

PHY1_RXD1

D20

3.3V

PHY1 receiving data channel 1

PHY1_RXD2

C22

3.3V

PHY1 receiving data channel 2

PHY1_RXD3

B21

3.3V

PHY1 receiving data channel 3

PHY1_RX_DV

B20

3.3V

PHY1 receiving data enable

PHY2_GTCLK

N19

3.3V

PHY2 transmitting clock

PHY2_TXD0

M21

3.3V

PHY2 transmitting data channel 0

PHY2_TXD1

L21

3.3V

PHY2 transmitting data channel 1

PHY2_TXD2

L22

3.3V

PHY2 transmitting data channel 2

PHY2_TXD3

K22

3.3V

PHY2 transmitting data channel 3

PHY2_TX_EN

J22

3.3V

PHY2 transmitting data enable

PHY2_RXC

L20

3.3V

PHY2 receiving clock

PHY2_RXD0

K20

3.3V

PHY2 receiving data channel 0

PHY2_RXD1

L19

3.3V

PHY2 receiving data channel 1

PHY2_RXD2

J20

3.3V

PHY2 receiving data channel 2

PHY2_RXD3

K19

3.3V

PHY2 receiving data channel 3

PHY2_RX_DV

K18

3.3V

PHY2 receiving data enable

3.7

LVDS Interfaces

3.7.1

Introduction

The LVDS interfaces are the four 20 pins with the pitch of 2.00mm, two

of which are transmitting interfaces, and the other are receiving interfaces.
Each interface includes five pairs of differential signals. J13 needs to be set

Summary of Contents for DK-START-GW2A55-PG484

Page 1: ...DK START GW2A55 PG484 V1 3 Development BoardDK START GW2A55 PG484 V1 3 Development Board User Guide DBUG375 1 0E 04 22 2020 ...

Page 2: ... identified as trademarks or service marks are the property of their respective holders as described at www gowinsemi com GOWINSEMI assumes no liability and provides no warranty either expressed or implied and is not responsible for any damage incurred to your hardware software data or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms...

Page 3: ...Revision History Date Version Description 04 22 2020 1 0E Initial version published ...

Page 4: ...logy and Abbreviations 2 1 5 Support and Feedback 2 2 Introduction 3 2 1 Overview 3 2 2 Development Kit 4 2 3 PCB Components 5 2 4 System Block Diagram 6 2 5 Features 6 3 Development Board Circuit 9 3 1 FPGA Module 9 3 2 Download Module 9 3 2 1 Introduction 9 3 2 2 Pinout 10 3 3 Power Supply 11 3 3 1 Introduction 11 3 4 Clock and Reset 12 3 4 1 Introduction 12 3 4 2 Pinout 13 ...

Page 5: ...DSI 20 3 8 1 Introduction 20 3 8 2 Pinout 21 3 9 MIPI CSI 22 3 9 1 Introduction 22 3 9 2 Pinout 23 3 10 SD Card 24 3 10 1 Introduction 24 3 10 2 Pinout 25 3 11 RTC 25 3 11 1 Introduction 25 3 11 2 Pinout 25 3 12 AD DA 26 3 12 1 Introduction 26 3 12 2 Pinout 26 3 13 CAN 27 3 13 1 Introduction 27 3 13 2 Pinout 27 3 14 WIFI 27 3 14 1 Introduction 27 3 14 2 Pinout 28 3 15 GPIO 28 3 15 1 Introduction 2...

Page 6: ...33 3 17 LED Module 34 3 17 1 Introduction 34 3 17 2 Pinout 34 3 18 Keys Module 35 3 18 1 Introduction 35 3 18 2 Pinout 35 3 19 Switches Module 35 3 19 1 Introduction 35 3 19 2 Pinout 36 4 Quick Start 37 4 1 Install Software 37 4 2 Development Board Power on Test 37 4 3 Build Demo Program 37 4 4 Download and Run 38 ...

Page 7: ...am of FPGA and Ethernet 15 Figure 3 6 LVDS TX Interface 17 Figure 3 7 LVDS RX Interface 17 Figure 3 8 Connection Diagram of MIPI DSI 20 Figure 3 9 Connection Diagram of MIPI CSI 23 Figure 3 10 Connection Diagram of SD Card 24 Figure 3 11 Connection Diagram of RTC 25 Figure 3 12 Connection Diagram of AD DA 26 Figure 3 13 Connection Diagram of CAN 27 Figure 3 14 Connection Diagram of WIFI 28 Figure ...

Page 8: ...List of Figures DBUG375 1 0E v Figure 4 2 Process Window 38 Figure 4 3 Build Completed 38 Figure 4 4 Programmer Window 39 Figure 4 5 Device Configure Window 39 Figure 4 6 Click Program Configure 40 ...

Page 9: ...3 8 LVDS TX2 Pinout 18 Table 3 9 LVDS TX2 Pinout 19 Table 3 10 MIPI DSI Pinout 21 Table 3 11 MIPI DSI Pinout 23 Table 3 12 SD Card Pinout 25 Table 3 13 RTC Pinout 25 Table 3 14 AD DA Pinout 26 Table 3 15 CAN Pinout 27 Table 3 16 WIFI Pinout 28 Table 3 17 40pin Interface Pinout 30 Table 3 18 20pin Interface Pinout 31 Table 3 19 50pin FPC Interface Pinout 33 Table 3 20 LCD Screen Brightness Control ...

Page 10: ...o the development board system architecture and hardware resources 3 An introduction to the hardware circuits functions and pinout 1 2 Supported Products The information presented in this guide applies to GW2A LV55PG484 device 1 3 Related Documents The latest user guides are available on the GOWINSEMI Website You can find the related documents at www gowinsemi com 1 DS102 GW2A series FPGA Products...

Page 11: ... Random Access Memory DSP Digital Signal Processing FLASH Flash Memory FPGA Field Programmable Gate Array GPIO General Purpose Input Output LDO Low Dropout Regulator LUT4 Four input Look up Tables LVDS Low Voltage Differential Signaling S SRAM Shadow Static Random Access Memory 1 5 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support If you have any ques...

Page 12: ...K START GW2A55 PG484 V1 3 applies to high speed data storage based on DDR3 high speed communication test based on MIPI LVDS and GbE 55k series of FPGA products functions evaluation the verification of hardware reliability software learning and debugging etc The development board uses the GW2A LV55PG484 FPGA device ...

Page 13: ...elopment board includes a DDR3 chip with 2Gbit 16 bit bus width Its two Gigabit Ethernet interfaces support 10M 100M 1000M Ethernet communication It has abundant peripheral interfaces including LVDS interfaces a SD card socket CAN bus interface MIPI CSI MIPI DSI AD DA interface and GPIO interfaces RTC module is designed to provide real time clock for MCU IP Besides that it also offers an external ...

Page 14: ... 5V Power Ethernet1 1 0V Power DDR3 1 5V Power 3 3V Power Power Socket Power Switch 40PIN GPIO LED 4 USB MINI B Switch 4 USB to JTAG chip LVDS RX LVDS TX FPGA Key 4 Reset Configure FLASH Bank4 Level Selection SD 20PIN GPIO LCD Interface CAN Interface CSI DSI AD DA WIFI 1 2V Power 1 8V Power Dip switch Ethernet2 ...

Page 15: ...atures The key features are as follows 1 The FPGA device Gowin GW2A LV55PG484 FPGA Max user I O 319 2 Download and Boot Integrates the download module and can be downloaded with USB Mini B cable External Flash boot The blue DONE light is on after loading 3 Power External DC 5V 2A The blue POWER light is on after power on ...

Page 16: ... supporting 3 3v 2 5v and 1 8v Note J13 needs to be set to 2 5V when LVDS is used 8 MIPI DSI Interface The interface includes 5 pairs of differential signals among which one for clock and four for data The stacked board connector with 30 contacts 0 4mm pitch is used Five lane DSI signals are simultaneously channeled to 20pin double row of pins with 2 00mm pitch 9 MIPI CSI Interface MIPI interface ...

Page 17: ...d The communication with FPGA is via UART The maximum rate is 1Mbps 14 WIFI The ESP WROOM 02 WIFI module of Lexin is used The communication with FPGA is via SPI SPI rate is 20Mbps 15 GPIO Interface There are 40PIN double rows pins including 34 GPIOs I O Bank voltage is adjusted to 3 3V and there are also 3 3V voltage and 5V voltage and two ground pins There are 20PIN double rows pins including 16 ...

Page 18: ...FT2232 USB conversion chip You can set the MODE value to download the programs to the on chip SRAM or external Flash When downloaded to SRAM the data stream file will be lost if the device is power down When downloaded to Flash the data stream file will not be lost if power down The MODE value configuration is as follows 1 In any modes you can download the data stream file to the on chip SRAM and ...

Page 19: ... chip the B channel of FT2232 can be configured as an asynchronous FIFO interface The connection diagram is follows Figure 3 2 Asynchronous FIFO Connection Diagram EEDATA EECLK EECS FTDI_RD FTDI_TXE FTDI_RXF FIFO_D 7 0 USB to FIFO USB_D USB_D Configure EEPROM FTDI_SIWU FTDI_WR 3 2 2 Pinout Table 3 1 FPGA Download and Pinout Name FPGA Pin No BANK I O Level Description JTAG_TCK N20 2 3 3V JTAG Signa...

Page 20: ...ite Enable Signal FTDI_RXF C10 0 1 2V Read Enable Signal FIFO_D0 E19 2 3 3V Data bits 0 FIFO_D1 E20 2 3 3V Data bit 1 FIFO_D2 F18 2 3 3V Data bit 2 FIFO_D3 F19 2 3 3V Data bit 3 FIFO_D4 G20 2 3 3V Data bit 4 FIFO_D5 G19 2 3 3V Data bit 5 FIFO_D6 H20 2 3 3V Data bit 6 FIFO_D7 H18 2 3 3V Data bit 7 3 3 Power Supply 3 3 1 Introduction The development board is powered through a power adapter The input...

Page 21: ...try screen One AAT1541A power chip is used to generate 5V and 5v power for MIPI DSI interface One TPS61161A power chip is used to generate 17 4v power for MIPI DSI interface backlighting 3 4 Clock and Reset 3 4 1 Introduction The development board offers a 50MHz oscillator connecting to the global clock pins The reset circuit uses keys and dedicated reset chips After power on the reset chip automa...

Page 22: ... input RST_N A14 1 2 5V Reset Signal active Low 3 5 DDR3 3 5 1 Introduction The development board includes a DDR3 chip with 2Gbit 16 bit bus width and the highest data rate is 1600MT s Figure 3 4 Connection Diagram of FPGA and DDR3 3 5 2 Pinout Table 3 4 DDR3 Pinout Name FPGA Pin No BANK I O Level Description DDR3_A0 G1 7 1 5V Address DDR3_A1 U5 6 1 5V Address DDR3_A2 G5 7 1 5V Address ...

Page 23: ...ank address DDR3_BA1 U4 6 1 5V Bank address DDR3_BA2 F3 7 1 5V Bank address DDR3_CASn C3 7 1 5V Column address strobe DDR3_CK_EN E3 7 1 5V Clock Enable DDR3_CKn R22 3 1 5V Differential clock DDR3_CKp P22 3 1 5V Differential clock DDR3_DQ0 M5 6 1 5V Data DDR3_DQ1 T3 6 1 5V Data DDR3_DQ2 M3 6 1 5V Data DDR3_DQ3 T2 6 1 5V Data DDR3_DQ4 Y1 6 1 5V Data DDR3_DQ5 U1 6 1 5V Data DDR3_DQ6 N3 6 1 5V Data DD...

Page 24: ...a strobe DDR3_WEn C1 7 1 5V Write enable 3 6 Ethernet 3 6 1 Introduction The development board has two Ethernet circuits and supports gigabit mode which can provide hardware testing environment in the LED display applications The interface connected to other devices is RJ45 and the transformer is integrated The connection diagram is as follows Figure 3 5 Connection Diagram of FPGA and Ethernet PHY...

Page 25: ...3V PHY1 receiving data channel 3 PHY1_RX_DV B20 2 3 3V PHY1 receiving data enable PHY2_GTCLK N19 2 3 3V PHY2 transmitting clock PHY2_TXD0 M21 2 3 3V PHY2 transmitting data channel 0 PHY2_TXD1 L21 2 3 3V PHY2 transmitting data channel 1 PHY2_TXD2 L22 2 3 3V PHY2 transmitting data channel 2 PHY2_TXD3 K22 2 3 3V PHY2 transmitting data channel 3 PHY2_TX_EN J22 2 3 3V PHY2 transmitting data enable PHY2...

Page 26: ...VDS_B10_N J19 Figure 3 7 LVDS RX Interface 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 LVDS_A1_P LVDS_A2_P LVDS_A3_P LVDS_A4_P LVDS_A5_P LVDS_A1_N LVDS_A2_N LVDS_A3_N LVDS_A4_N LVDS_A5_N J18 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 LVDS_A6_P LVDS_A7_P LVDS_A8_P LVDS_A9_P LVDS_A10_P LVDS_A6_N LVDS_A7_N LVDS_A8_N LVDS_A9_N LVDS_A10_N J17 3 7 2 Pinout Table 3 6 LVDS TX Pinout Pins Nu...

Page 27: ...mber Name FPGA Pin No BANK I O Level Description 1 LVDS_B6_P AB15 4 2 5V Differential Channel 6 2 LVDS_B6_N AA15 4 2 5V Differential Channel 6 5 LVDS_B7_P Y16 4 2 5V Differential Channel 7 6 LVDS_B7_N W16 4 2 5V Differential Channel 7 9 LVDS_B8_P V14 4 2 5V Differential Channel 8 10 LVDS_B8_N V15 4 2 5V Differential Channel 8 13 LVDS_B9_P AB12 4 2 5V Differential Channel 9 14 LVDS_B9_N AA12 4 2 5V...

Page 28: ... 17 LVDS_A5_P AB17 4 2 5V Differential Channel 5 18 LVDS_A5_N AB18 4 2 5V Differential Channel 5 Table 3 9 LVDS TX2 Pinout Pins Number Name FPGA Pin No BANK I O Level Description 1 LVDS_A6_P Y14 4 2 5V Differential Channel 6 2 LVDS_A6_N Y15 4 2 5V Differential Channel 6 5 LVDS_A7_P W14 4 2 5V Differential Channel 7 6 LVDS_A7_N W15 4 2 5V Differential Channel 7 9 LVDS_A8_P AB13 4 2 5V Differential ...

Page 29: ...m pitch Figure 3 8 Connection Diagram of MIPI DSI 1 10 2 3 4 5 6 7 8 9 11 12 13 14 15 DSI_D0n 30 21 29 28 27 26 25 24 23 22 20 19 18 17 16 DSI_D0p DSI_D1n DSI_D1p DSI_CLKn DSI_CLKp DSI_D2n DSI_D2p DSI_D3n DSI_D3p DSI_LED DSI_LED DSI_ 5V DSI_ 5V VCC1P8 DSI_RSTn DSI_CABC DSI_TE DSI_D0n DSI_D0p DSI_LP_D0n DSI_LP_D0p DSI_D1n DSI_D1p DSI_LP_D1n DSI_LP_D1p DSI_D2n DSI_D2p DSI_LP_D2n DSI_LP_D2p DSI_D3n D...

Page 30: ...DSI_D2p A17 1 2 5V HS differential data 2 DSI_D3n B15 1 2 5V HS differential data 3 DSI_D3p A15 1 2 5V HS differential data 3 DSI_LP_D0n C7 0 1 2V LP single ended data 0 DSI_LP_D0p A7 0 1 2V LP single ended data 0 DSI_LP_D1n A6 0 1 2V LP single ended data 1 DSI_LP_D1p B7 0 1 2V LP single ended data 1 DSI_LP_CLKn B6 0 1 2V LP single ended clock DSI_LP_CLKp D7 0 1 2V LP single ended clock DSI_LP_D2n...

Page 31: ... 2 5V Tearing effect output signal 3 9 MIPI CSI 3 9 1 Introduction MIPI CSI uses 15pin connector with 1mm pitch The interface includes 3 pairs of differential signals among which one for clock and two for data Differential signals of three lanes are simultaneously channeled to the double rows pin of 20pin with 2 00mm pitch ...

Page 32: ...CSI_D0n CSI_D0p CSI_LP_D0n CSI_LP_D0p CSI_D1n CSI_D1p CSI_LP_D1n CSI_LP_D1p CSI_CLKn CSI_CLKp CSI_LP_CLKn CSI_LP_CLKp 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 CSI_D0p CSI_D1p CSI_CLKp CSI_D0n CSI_D1n CSI_CLKn J10 3 9 2 Pinout Table 3 11 MIPI DSI Pinout Name FPGA Pin No BANK I O Level Description CSI_D0n C15 1 2 5V HS differential data 0 CSI_D0p C14 1 2 5V HS differential data 0 CSI_D1n E...

Page 33: ... data 1 CSI_LP_D1p B1 0 1 2V LP single ended data 1 CSI_LP_CLKn C4 0 1 2V LP single ended clock CSI_LP_CLKp C5 0 1 2V LP single ended clock CSI_RESET C21 2 3 3V Reset signal CSI_CLK C20 2 3 3V Clock CSI_SCL D19 2 3 3V I2C signal CSI_SDA G17 2 3 3V I2C signal 3 10 SD Card 3 10 1 Introduction The SD card slot on the board is the push push type with eight contacts It offers the detection of the card ...

Page 34: ...2 3 1 5V Insertion Detection 3 11 RTC 3 11 1 Introduction The real time clock module uses NXP PCF8563 and is externally connected with 32 768kHz quartz crystal It can be powered by the board power supply and the button battery The communication interface with the FPGA is I2C The connection diagram is follows Figure 3 11 Connection Diagram of RTC RTC Module RTC_INT IIC_SDA RTC_CLK IIC_SCL 3 11 2 Pi...

Page 35: ...of ADC DAC GPIO and shares the I2C bus with the RTC module The input and output interface uses 8pin and the connection diagram is follows Figure 3 12 Connection Diagram of AD DA IIC_SDA RTC_CLK AD DA_A0 AD DA_D0 AD DA_D1 AD DA_D2 AD DA_D3 AD DA_D4 AD DA_D5 AD DA_D6 AD DA_D7 AD DA Module 1 3 5 7 2 4 6 8 AD DA_D0 AD DA_D1 AD DA_D2 AD DA_D3 AD DA_D4 AD DA_D5 AD DA_D6 AD DA_D7 3 12 2 Pinout Table 3 14...

Page 36: ...n rate is 1Mbps The connection diagram is as follows Figure 3 13 Connection Diagram of CAN CAN_RXD CAN_TXD CANL CANH CAN Module 3 13 2 Pinout Table 3 15 CAN Pinout Name FPGA Pin No BANK I O Level Description CAN_TXD C11 1 2 5V Transmitting data CAN_RXD C12 1 2 5V Receiving data 3 14 WIFI 3 14 1 Introduction The ESP WROOM 02 WIFI module of Lexin is used to support SPI and UART SPI transmission rate...

Page 37: ...WIFI_SPI_CLK D9 0 1 2V SPI clock WIFI_SPI_MISO A10 0 1 2V SPI data WIFI_SPI_MOSI B8 0 1 2V SPI data WIFI_SPI_CS C8 0 1 2V SPI chip selection WIFI_TX D8 0 1 2V UART transmitting WIFI_RX A9 0 1 2V UART receiving 3 15 GPIO 3 15 1 Introduction 34 GPIOs channeled by two double column pins with 2 54mm pitch are reserved on the development board for testing The 40pin interfaces are connected to Bank5 The...

Page 38: ...37 39 32 34 36 38 40 3 3V H_GPIO_03 H_GPIO_05 H_GPIO_07 H_GPIO_09 H_GPIO_11 H_GPIO_13 H_GPIO_15 H_GPIO_17 H_GPIO_19 H_GPIO_21 H_GPIO_23 H_GPIO_01 H_GPIO_25 H_GPIO_27 H_GPIO_29 H_GPIO_31 H_GPIO_33 H_GPIO_04 H_GPIO_06 H_GPIO_08 H_GPIO_10 H_GPIO_12 H_GPIO_14 H_GPIO_16 H_GPIO_18 H_GPIO_20 H_GPIO_22 H_GPIO_24 H_GPIO_02 H_GPIO_26 H_GPIO_28 H_GPIO_30 H_GPIO_32 H_GPIO_34 5 0V J22 ...

Page 39: ...K I O Level Description 3 H_GPIO_01 AA11 5 3 3V General I O 4 H_GPIO_02 V11 5 3 3V General I O 5 H_GPIO_03 AB11 5 3 3V General I O 6 H_GPIO_04 V9 5 3 3V General I O 7 H_GPIO_05 Y11 5 3 3V General I O 8 H_GPIO_06 Y3 5 3 3V General I O 9 H_GPIO_07 V10 5 3 3V General I O 10 H_GPIO_08 W11 5 3 3V General I O 11 H_GPIO_09 W10 5 3 3V General I O 12 H_GPIO_10 Y10 5 3 3V General I O 13 H_GPIO_11 W9 5 3 3V ...

Page 40: ...al I O 33 H_GPIO_31 AB3 5 3 3V General I O 34 H_GPIO_32 AA3 5 3 3V General I O 35 H_GPIO_33 AB2 5 3 3V General I O 36 H_GPIO_34 AB1 5 3 3V General I O Table 3 18 20pin Interface Pinout Pins Number Name FPGA Pin No BANK I O Level Description 3 H_GPIO_01 AA11 5 3 3V General I O 4 H_GPIO_11 W9 5 3 3V General I O 5 H_GPIO_02 V11 5 3 3V General I O 6 H_GPIO_03 AB11 5 3 3V General I O 7 H_GPIO_04 V9 5 3...

Page 41: ... multiplex GPIO of FPGA Figure 3 17 50pin FPC Interface Diagram 1 J23 10 2 3 4 5 6 7 8 9 11 20 12 13 14 15 16 17 18 19 21 30 22 23 24 25 26 27 28 29 31 40 32 33 34 35 36 37 38 39 41 50 42 43 44 45 46 47 48 49 LCD_MODE LCD_VS LCD_DE LCD_B7 LCD_HS LCD_B5 LCD_B6 LCD_B3 LCD_B4 LCD_B2 LCD_G7 LCD_G5 LCD_G6 LCD_G3 LCD_G4 LCD_G2 LCD_R7 LCD_R5 LCD_R6 LCD_R3 LCD_R4 LCD_DCLK LCD_U D LCD_R L LCD_RST LCD_VCOM ...

Page 42: ...e data bit7 15 LCD_B4 AA8 5 3 3V Blue data bit7 16 LCD_B3 Y7 5 3 3V Blue data bit7 17 LCD_B2 W8 5 3 3V Blue data bit7 20 LCD_G7 V8 5 3 3V Green data bit7 21 LCD_G6 AB8 5 3 3V Green data bit7 22 LCD_G5 W7 5 3 3V Green data bit7 23 LCD_G4 AA7 5 3 3V Green data bit7 24 LCD_G3 AB7 5 3 3V Green data bit7 25 LCD_G2 AA6 5 3 3V Green data bit7 28 LCD_R7 AB6 5 3 3V Red data bit7 29 LCD_R6 AB5 5 3 3V Red da...

Page 43: ...the development board which can be used for demo When the output signal of FPGA corresponding pin is low the LED is lit up When the output signal is high the LED is off The connection diagram is shown in Figure 3 18 Figure 3 18 LED Connection Diagram LED1 W20 LED2 W22 LED3 V22 LED4 U20 3 3V 3 17 2 Pinout Table 3 21 LED Pinout Name FPGA Pin No BANK I O Level Description LED1 W20 3 1 5V LED 1 LED2 W...

Page 44: ...is low The diagram is as shown in Figure 3 19 Figure 3 19 Key Circuit Diagram V20 T18 U18 T17 KEY1 KEY2 KEY3 KEY4 3 18 2 Pinout Table 3 22 Pins Distribution of Keys Module Name FPGA Pin No BANK I O Level Description KEY1 V20 3 1 5V KEY1 KEY2 T18 3 1 5V KEY2 KEY3 U18 3 1 5V KEY3 KEY4 T17 3 1 5V KEY4 3 19 Switches Module 3 19 1 Introduction There are four switches on the development board to control...

Page 45: ...36 40 Figure 3 20 Switch Circuit Diagram SW1 R18 SW2 AB21 SW3 R19 SW4 Y21 1 5V 3 19 2 Pinout Table 3 23 Switches Module Pinout Name FPGA Pin No BANK I O Level Description SW1 R18 3 1 5V Switch1 SW2 AB21 3 1 5V Switch2 SW3 R19 3 1 5V Switch3 SW4 Y21 3 1 5V Switch4 ...

Page 46: ... it is powered on Plug the 5V power supply into the power socket of the development board and and switch to ON and MODE is set to 000 The four blue LED lights are flashing indicating that the development board can operate 4 3 Build Demo Program The LED test program is to demonstrate four LEDs streaming flashing Users can download this demo at Gowinsemi website Support Starter Kits and Development ...

Page 47: ...e Process window and select Rerun All Figure 4 2 Process Window 3 After building the following information will be displayed The generated bitstream file is saved in LED_test impl pnr LED_test fs Figure 4 3 Build Completed 4 4 Download and Run 1 Connect the development board with PC using the download cable and ...

Page 48: ...e device list and select Configure Device The Device configuration dialog box will pop up Figure 4 4 Programmer Window 2 Set the download mode as shown below and specify the bitstream file path Figure 4 5 Device Configure Window 3 After configuration click the Program Configure to download the program After finishing the four LEDs of the development board will streaming flash ...

Page 49: ...4 Quick Start 4 4 Download and Run DBUG375 1 0E 40 40 Figure 4 6 Click Program Configure ...

Page 50: ......

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