3 Development Board Circuit
3.5 DDR3
DBUG375-1.0E
13(40)
3.4.2
Pinout
Table 3-3 Clock and Reset Pinout
Name
FPGA Pin No.
BANK
I/O Level
Description
CLK_G
M19
2
3.3V
50MHz crystal oscillator
input
RST_N
A14
1
2.5V
Reset Signal, active Low
3.5
DDR3
3.5.1
Introduction
The development board includes a DDR3 chip with 2Gbit,16-bit bus
width, and the highest data rate is 1600MT/s.
Figure 3-4 Connection Diagram of FPGA and DDR3
3.5.2
Pinout
Table 3-4 DDR3 Pinout
Name
FPGA Pin No.
BANK
I/O Level Description
DDR3_A0
G1
7
1.5V
Address
DDR3_A1
U5
6
1.5V
Address
DDR3_A2
G5
7
1.5V
Address
