3 Development Board Circuit
3.1 FPGA Module
DBUG375-1.0E
9(40)
3
Development Board Circuit
3.1
FPGA Module
Overview
For the resources of GW2A-LV55PG484 FPGA products, see
GW2A Series of FPGA Products.
I/O BANK Introduction
For the I/O BANK, package and pinout information, see
, GW2A
Series of FPGA Products Package and Pinout User Guide.
3.2
Download Module
3.2.1
Introduction
The development board provides USB download interface, which is
realized by the A channel of FT2232 USB conversion chip. You can set the
MODE value to download the programs to the on-chip SRAM or external
Flash. When downloaded to SRAM, the data stream file will be lost if the
device is power down. When downloaded to Flash, the data stream file will
not be lost if power down.
The MODE value configuration is as follows:
1. In any modes, you can download the data stream file to the on-chip
SRAM and run it immediately.
2. Set MODE as "011" to download the data stream file to the external
Flash. Set MODE to "000" and power on again. The device will read the
FPGA configuration data from the Flash automatically.
The connection diagram for downloading and configuration is as
follows:
