BIOS Setup
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Parameter
Description
NBIO RAS Common Options
Press [Enter] for more options.
NBIO RAS Global Control
– Options available: Manual/Auto. Default option is
Auto
.
NBIO RAS Control
– 0 = Disabled, 1 = MCA, 2 = Legacy.
– Options available: Disabled/MCA/Legacy. Default option is
MCA
.
Egress Poison Severity High
– Enter a value. Each bit set to 1 enables high severity on the
associated IOHC egress port. A bit of 0 indicates low severity.
Egress Poison Severity Low
– Enter a value. Each bit set to 1 enables high severity on the
associated IOHC egress port. A bit of 0 indicates low severity.
NBIO SyncFlood Generation
– This value may be used to mask SyncFlood caused by NBIO RAS
options. When set to TRUE SyncFlood from NBIO is masked.
When set to FALSE NBIO is capable of generating SyncFlood.
– Options available: Enabled/Disabled/Auto. Default option is
Auto
.
NBIO SyncFlood Reporting
– This value may be used to enable SyncFlood reporting to APML.
When set to TRUE SyncFlood will be reported to APML. When set
to FALSE that reporting will be disabled.
– Options available: Enabled/Disabled. Default option is
Disabled
.
Egress Poison Mask High
– Enter a value. These set the enable mask for masking of errors
logged in EGRESS_POISON_STATUS. For each bit set to 1,
errors are masked. For each bit set to 0, errors trigger response
actions.
Egress Poison Mask Low
– Enter a value. These set the enable mask for masking of errors
logged in EGRESS_POISON_STATUS. For each bit set to 1,
errors are masked. For each bit set to 0, errors trigger response
actions.
Uncorrected Converted to Poison Enable Mask High
– Enter a value. These set the enable mask for masking of
uncorrectable parity errors on internal arrays. For each bit set to
1, a system fatal error event is triggered for UCP errors on arrays
associated with that egress port. For each bit set to 0, errors are
masked.
Uncorrected Converted to Poison Enable Mask Low
– Enter a value. These set the enable mask for masking of
uncorrectable parity errors on internal arrays. For each bit set to
1, a system fatal error event is triggered for UCP errors on arrays
associated with that egress port. For each bit set to 0, errors are
masked.
Summary of Contents for R282-Z96
Page 1: ...R282 Z96 AMD EPYC 7002 DP Server System 2U 12 Bay GPU NVMe sku User Manual Rev 1 0 ...
Page 10: ... 10 This page intentionally left blank ...
Page 14: ...Hardware Installation 14 ...
Page 16: ...Hardware Installation 16 1 3 System Block Diagram ...
Page 24: ...System Appearance 24 This page intentionally left blank ...
Page 35: ... 35 System Hardware Installation 4 5 6 7 4 5 6 7 5 6 6 7 7 9 4 ...
Page 39: ... 39 System Hardware Installation 5 Push Push 6 ...
Page 43: ... 43 System Hardware Installation Onboard SATA Cable Onboard SATA Cable 3 12 Cable Routing ...
Page 46: ...System Hardware Installation 46 GPU Card Power Cable ...
Page 47: ... 47 System Hardware Installation NVMe Card Cable CNV3134 U2_A U2_8 CNV3134 U2_B U2_9 ...
Page 48: ...System Hardware Installation 48 NVMe Card Cable CNV3134 U2_C U2_10 CNV3134 U2_D U2_11 ...
Page 52: ...Motherboard Components 52 This page intentionally left blank ...
Page 74: ...BIOS Setup 74 5 2 11 SATA Configuration ...
Page 79: ... 79 BIOS Setup 5 2 16 Intel R I350 Gigabit Network Connection ...