Giga-tronics GT 9000, Operation & Maintenance Manual

Page: 89 / 238

Example:
When the divisor is to be 195 (this occurs when the IF is 195 MHz), the translators are
programmed with the binary equivalent of 195 (011000011). This breaks down as 3 for the 3-bit
counter (binary 011), and 24 for the 6-bit counter (binary 011000). For the first three clock
cycles U11 divides the IF by 9, for a total of 3 x 9 = 27 IF cycles. The 3-bit counter then
reaches zero and programs U11 to divide by 8 for the remaining clock cycles (21, since three of
the 6-bit counter 24 cycles have already been counted simultaneously with the other counter).
After 21 x 8 = 168 further IF cycles (bringing the total so far counted to 195), the low-going
pulse of the output waveform occurs. The counters are preset and the division cycles
recommences. To compensate for the cycles added by delay in presetting the counters, the 6-bit
counter actually stopped early by 2 clock cycles (2 x 8 = 16 IF cycles); the high level at U8-14
occurs two clock cycles before the beginning of the next division cycle, because two clock
pulses are needed to initiate that division cycle. Since 195 IF cycles occurred during one
division cycle, the circuit has divided the input frequency by 195.
The OR gate U10 and four passive components are used to shut down the output of the circuit
under conditions that would interfere with normal operation of the phase lock loop. Under
normal conditions, with an IF input in the 95-395 range, the clock frequency applied to U10-4
will be above 10 MHz. The filter components between the three gates produce a low at U10-12,
and the third gate does not interfere with the circuit output frequency. If the IF drops
substantially below the normal range, however, and the clock frequency at U10-4 falls well
below 10 MHz. The filter action will not be sufficient to have the same effect. U10-9 will go to
an ECL high, preventing any waveform from reaching the phase lock loop. The reason for this
precaution is that the Mod-8/9 counter responds erratically to frequencies below its intended
range, and could prevent the PLL circuit from recovering phase lock when the output frequency
is too low. When the output waveform has been shut down, the PLL circuit reacts by kicking the
output frequency to a higher value. This forces the IF to a higher frequency within the range of
the divider circuit. After the IF has been forced higher, the kicker circuit again allows the output
frequency to reach the PLL.
U16 thru U20 provide drive for the REFerence COUPLER and the REFerence SWITCH filters.
The U18B signal switches the downconverter coupler port. U15 is a decoder which decodes chip
selects. U13 and U14 are buffers required for interfacing with the computer bus.
Theory of Operation
Manual No. 120AM00250, Rev C, September 1998
3-31