Giga-tronics GT 9000, Operation & Maintenance Manual

Page: 79 / 238

3.3.6 Pulse Generator — PC Assembly A5A1
The pulse generator consists of the rate generator, the delay generator, and the width generator.
The rate generator employs a programmable phase lock loop circuit, consisting of a 3-10 MHz
VCO (U1), and two synthesizer chips (U3/U4) containing phase comparators and programmable
dividers. The PLL circuit uses the 10 MHz timebase (translated to TTL levels by U20D and
enabled by U2B when the internal pulse mode is selected) as a reference input, and generates a
series of stable frequencies, selected by the programming of the synthesizer chips. There are
actually two ranges of frequencies, depending on whether U2C (Range 1) or U2D (Range 2) is
enabled. The signal propagates through U5A and U5B to U33A. In the case of externally
triggered modulation, U7A is enabled and the TRIGN input propagates through it to U33A. The
output of U33A (STARTN) gates (via U6A) a 100 MHz delay line clock consisting of U8D,
U22, C32, and C33. This signal is converted to a PM_SYNC signal by U33D, U7B, U7C,
U33C, and U20C, for output to the rear panel.
The delay is generated in 10 ns increments by multiple counters which are clocked by the
100 MHz clock described above. U10 is a 4-bit counter which counts delays up to 160 ns; U16
is an 8-bit counter which counts up to approximately 40.9
µ
s in 160 ns increments. U17 counts
up to approximately 10.485 ms in 40.9
µ
s increments and U23 counts up to approximately 2.6 s
in 10.485
µ
s increments. These counters are programmed by the computer, allowing up to 2
seconds of delay, programmable in 10 ns increments. When the delay cycle is completed and the
DEND from U28A and the COUT from U10 have propagated through the gates giving low
inputs at U8-6 and U8-7, U6-10 is toggled and the width cycle starts on the next clock cycle.
The beginning of the width cycle causes U6-15 to go high. This signal, after propagating
through U13A and U33B, is the actual pulse signal which will ultimately drive the RF pulse
modulators.
The width is also generated in 10 ns increments and the counters (U11, U25, U26, and U27) are
set up similar to those which control the delay cycles. The width cycle ends when both inputs to
U8C are low to reset U6 (this is controlled by U11 COUT and U28 DEND). The next trigger
from the rate generator will start another delay and width cycle.
3.3.7 AM/FM Driver — PC Assembly A6
The AM/FM driver PC assembly has two main functions. The first is to select the internal or
external AM or FM signal. The second is to adjust the amplitude of the selected signal
according to the depth or deviation required before outputting the signal to the level board (for
AM) or the output PLL (for FM).
U3 is an analog switch to select the external AM signal or a signal from the internal generator.
The selected signal is buffered by U1 and then converted to a differential signal by U7A and B.
One side of this differential signal is buffered by U25A for output to the rear panel as the
AM_SIG output. The U8 Modulator IC functions as a variable attenuator controlled by a voltage
from the DAC U4. The voltage at U5-7 changes according to the selected AM depth of
modulation. The DAC has a reference voltage which is derived from U9, inverted and attenuated
to give 3.2 volts. The output of the variable attenuator U8 is a differential signal which is
combined by U2A to give a single AM signal output. U23 switches this output (the signal can
be switched to be DC coupled or inverted to give an output 180 degrees out of phase with the
input signal) to the input of U25B, which provides the AM signal to the level board A10.
U10 is an analog switch to select the external FM signal or a signal from the internal generator.
The selected signal is buffered by U11 and converted to a differential signal by U13A and B.
Theory of Operation
Manual No. 120AM00250, Rev C, September 1998
3-21