Giga-tronics GT 9000, Operation & Maintenance Manual

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3.3.4 CPU — PC Assembly A4
Y1, C3, C4, Q1, and U6A provide clocking for U1, the 68000 microprocessor chip.
U2, U3, and U4 buffer the output to the I/O data bus.
U5A and B make up the Power-On Reset logic. The presence of the clock is detected at U5-2.
There is a set delay before the reset line switches to prevent failures during brownout or power
glitch conditions.
U7 decodes interrupts. When the CPU receives an interrupt, one of the FC0 - FC2 lines is
activated causing U8, U9, and U10 to generate several different logic signals. VPAN puts the
CPU into the non-vectored interrupt mode to handle the interrupt. The MR (Memory Ready)
logic is also generated, which slows the CPU for read/write cycles.
U11 and U12 are a buffer between the I/O bus and the CPU.
U1, U3, and U15-U18 decode chip selects for boards or circuits on the I/O bus. U19, U20, and
U21 give a startup vector to the CPU on power up.
3.3.5 Pulse Driver — PC Assembly A5
The pulse driver PC assembly has various logic circuits required for directing the pulse signals
to the proper locations, as well as the actual pulse driver circuitry which drives the pulse
modulators. U12-U15 are latches providing interface between the I/O bus and the individual
circuits on the driver board as well as the pulse generator board (A5A1). U11 decodes the chip
selects for the latches and other circuits.
When EXT Pulse Modulation is selected, the external pulse signal is received at PM_IN, U1-5.
The external signal and its complement are output on U1-2 and U1-4. EPM- logic at U1-7
selects one of the signals to propagate U2A or B, sel or - edge triggering when EXT
TRIG (+ or -) or EXT PULS (+ or - ) is selected. In the case of EXT TRIG, the trigger signal
(TRIGN) is supplied to the pulse generator PC assembly (A5A1) via U4D, U8C and U9C.
The external pulse signal from U2A or B passes thru U2D to the pulse drivers when U2D is
enabled via U3A and the EXTPUL logic signal. The PULSE signal from the pulse generator PC
assembly passes thru U2C and on to the pulse drivers when the INT/TRIG signal is true. This
allows only one signal at a time, either the external pulse signal or the internal pulse signal, to
drive the pulse modulators.
The selected pulse signal is provided to the rear panel as the PM_VIDEO signal after being
translated to a TTL signal. U6A, U4 and associated components allow the rising and falling
edge of this signal to be positioned to align with the actual pulsed RF out of the unit.
The selected pulse signal (referred to as SAMPN on the schematic) is used for the purpose of
sampling the detector voltage on the leveling board when the RF is on. In order to do this it is
necessary to delay and shorten the pulse. This is done by U8A, B, D, and U9A, B, D. The
signal is then translated by U10A, U10B, Q7 and Q8 to signal levels that are capable of
switching the FET samplers on the Leveling PCA. The resulting signal is called SAMPLE.
U1C and D, and U3D handle the logic which selects the proper driver to be enabled at U5A, B
or C. The pulse signal is translated to TTL levels at U6B thru D.
When pulse modulation is not selected, the FET samplers on the leveling PCA must stay on
continuously. The PULSE_OFF logic signal serves this purpose through U3C and U7A.
Model GT 9000 Microwave Synthesizer
3-20
Manual No. 120AM00250, Rev C, September 1998