Giga-tronics GT 9000, Operation & Maintenance Manual

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3.3.17 Output PLL — PC Assembly A18
The Output Phase Locked Loop circuit compares the output of the divide-by-N circuit (A17) to
a timebase-related reference signal, and fine-tunes the output YIG oscillator to stabilize the
divide-by-N output at 1 MHz.
The 10 MHz timebase input (J3) is buffered by U1 and applied to U3, a frequency divider with
a divisor of 10. The 1 MHz output of U3 is the reference input to the phase detector U2-6. The
variable input at U2-9 is the output of the divide-by-N circuit (J2), buffered by U1, which will
be at 1 MHz when the loop is locked, thus giving the correct RF output frequency. If the two
inputs to the phase detector are not in phase, wide pulses are produced at either U2-12 or U2-3,
depending on whether the variable input is leading or lagging the reference. The loop
amplifier/filter circuit U4A and B averages these pulses in order to produce a fine-tuning signal
for the output YIG oscillator. The object is to adjust the oscillator frequency in the direction that
will reduce the phase difference between the inputs to the U2 phase detector.
In the CW mode, the output of the amplifier/filter U4A and B is applied via analog switches
U7A and B to a low pass filter (C54-56 and L1), required to filter out the 1 MHz reference
frequency. The output of the filter is then applied to U18B, an amplifier with variable AC gain
to compensate for loop gain changes due to a changing divide-by-N output. R83 and R84
provide AC attenuation. The PLL voltage is buffered by U18A before being applied to one of
three summing junctions. Analog switches U19A and B select one of 3 circuits, U20, U21, or
U22, which drive the FM tuning coils of the output YIG oscillators for each frequency band.
U6 is a lock detector circuit which detects when the loop voltage goes beyond a given window,
thus indicating that the loop is unlocked. This circuit pulls the output lock signal low, causing
the lock LED DS1 to light. When the loop voltage is within the window the loop is locked, the
OUTPUTLOCK logic line is high and the DS1 board is dark.
When the FM mode is enabled, an alternative loop amplifier/filter is required. In this case U5A
and B filter the output pulses of the phase detector. The outputs of both amplifier/filter circuits,
U5 and U4, are applied to U7, an analog switch. When the FM mode is selected and the switch
U7A enables the U5 amplifier/filter. Additionally, during FM mode the modulating signal is
summed in with the loop voltage at one of the three FM drive circuits U20, U21, or U22. The
modulating signal sensitivity is adjusted with R33, R34, or R35, depending on which frequency
band is active. The appropriate sensitivity is selected with switch U14A and B, and the
modulating signal is then amplified by U16 and U17. U19A switches the PLL voltage from the
fixed LO PLL PC assembly to the 2-8 GHz oscillator when required for downconversion of
frequencies below 2 GHz.
U8 provides an interface between the computer and the PC assembly by decoding the chip
select lines. U9 buffers the output logic from the PC assembly so that it can be read by the
computer. U10 and U11 are latches for logic input from the computer bus.
Model GT 9000 Microwave Synthesizer
3-32
Manual No. 120AM00250, Rev C, September 1998