Giga-tronics GT 9000, Operation & Maintenance Manual

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3.3.14 1 Hz PLL — PC Assembly A15
The 1 Hz Phase Locked Loop circuit synthesizes a reference frequency programmable in fine
increments. This reference is substituted for the standard timebase signal used by the reference
phase lock loop. By setting the reference output from this circuit, the computer is able to
specify RF frequency in 1 Hz increments. The output at J3 has a range of 10-12 MHz and a
resolution of 2 Hz. When divided in half at the reference PLL input, the result is a 5-6 MHz
reference programmable in 1 Hz steps.
A 100-120 MHz voltage controlled oscillator (Q3) is controlled by U5. U5 is a synthesizer chip
containing several programmable frequency dividers and a phase comparator, used in
conjunction with an external prescaler (U7, which is programmed by U5 to divide by 40 or 41).
U5 compares the prescaled feedback input from the VCO (U5-3) to the timebase input (U5-7)
and produces pulsed outputs at U5-17 or U5-16, depending on which input is leading. A
filter/amplifier circuit (U9A) averages these pulses to produce a tuning input to the VCO. By
programming the dividers in U5, the computer sets the VCO frequency in 50 kHz increments.
The VCO frequency is buffered (Q2, U8A and B) and applied to a mixer circuit consisting of
the flip-flops of U16.
The second frequency input to the U16 mixer circuit is produced by a second VCO (Q4) having
the same range (100-120 MHz) but programmed in finer increments (20 Hz). This VCO is
controlled by a PLL circuit consisting of a phase comparator (U12) and a filter/amplifier circuit
(U13A). The inputs to the phase comparator consist of feedback from the mixer circuit
(U16-15) and a reference input from a third VCO circuit (Q1) divided down (by U3 and U4) to
100-150 kHz, giving 20 Hz increments. The PLL circuit phase locks the VCO to this reference.
The circuit consisting of U13B and U17B performs as a window detector. When the PLL circuit
is out of its normal control range, U17-7 goes high, illuminating the LED unlock indicator and
pulling the LOCK line low. The VCO output (from Q4) is divided by 10 (U14) yielding an
output at J1 with a frequency range of 10-12 MHz and a resolution of 2 Hz.
The third VCO (Q1) has a frequency range of 100-150 MHz, programmed in 20 kHz
increments. Dividers U3 and U4 reduce this frequency to 100-150 kHz so that it can be used as
a reference input by phase comparator U12. U1 is the same type of synthesizer chip as U5, and
its prescaler chip U2 also divides by 40 or 41. Filter/amplifier circuit U6A converts the phase
comparator outputs of U1 into a tuning voltage for the VCO. U11 is a decoder chip used for
decoding chip selects. U10 is a tri-state buffer for outputting board outputs to the bus.
Theory of Operation
Manual No. 120AM00250, Rev C, September 1998
3-27