MM516
User's Manual
38
Revision 1.4 7-8-2011
Hardware Description Manual
5.4.9 PCM_CLK and PCM_SYNC Generation
BlueCore 5 chip has two methods of generating PCM_CLK and PCM_SYNC in master mode. The first is
generating these signals by DDS from BlueCore 5 chip internal 4MHz clock (which is used in BlueCore2-
External). Using this mode limits PCM_CLK to 128, 256 or 512kHz and PCM_SYNC to 8kHz. The second is
generating PCM_CLK and PCM_SYNC by DDS from an internal 48MHz clock (which allows a greater range of
frequencies to be generated with low jitter but consumes more power). This second method is selected by setting
bit 48M_PCM_CLK_GEN_EN in PSKEY_PCM_CONFIG32. When in this mode and with long frame sync, the length
of PCM_SYNC can be either 8 or 16 cycles of PCM_CLK, determined by LONG_LENGTH_SYNC_EN in
PSKEY_PCM_CONFIG32.
This equation describes PCM_CLK frequency when being generated using the internal 48MHz clock:
f =
(CNT_RATE/CNT_LIMIT) x 24MHz
The frequency of PCM_SYNC relative to PCM_CLK can be set using :
f = PCM_CLK/SYNC_LIMIT x 8
CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG. As an example, to
generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set PSKEY_PCM_LOW_JITTER_CONFIG to
0x08080177.
5.4.10 PCM Configuration
The PCM configuration is set using two PS Keys, PSKEY_PCM_CONFIG32 detailed in Table 7.16 and
PSKEY_PCM_LOW_JITTER_CONFIG in Table 7.17. The default for PSKEY_PCM_CONFIG32 is
0x00800000
, i.e., first slot following sync is active, 13-bit linear voice format, long frame sync and interface master generating
256kHz PCM_CLK from 4MHz internal clock with no tristate of PCM_OUT.
Table 7 PSKEY_PCM_CONFIG32 Description
