MM516
User's Manual
11
Revision 1.4 7-8-2011
Hardware Description Manual
3
Physical Description
3.1 RF Receiver
The receiver features a near-zero IF architecture that allows the channel filters to be integrated onto the die. Sufficient
out-of-band blocking specification at the LNA input allows the radio to be used in close proximity to GSM and WCDMA
cellular phone transmitters without being desensitized. The use of a digital FSK discriminator means that no
discriminator tank is needed and its excellent performance in the presence of noise allows BlueCore 5 chip to
exceed the Bluetooth requirements for co-channel and adjacent channel rejection.
For EDR, an ADC is used to digitize the IF received signal.
3.1.1 Low Noise Amplifier
The LNA can be configured to operate in single-ended or differential mode. Single-ended mode is used for Class 1
Bluetooth operation; differential mode is used for Class 2 operation.
3.1.2 Analog to Digital Converter
The ADC is used to implement fast AGC. The ADC samples the RSSI voltage on a slot-by-slot basis. The front-end
LNA gain is changed according to the measured RSSI value, keeping the first mixer input signal within a limited
range. This improves the dynamic range of the receiver, improving performance in interference limited environments.
3.2 RF Transmitter
3.2.1 IQ Modulator
The transmitter features a direct IQ modulator to minimize the frequency drift during a transmit timeslot, which results
in a controlled modulation index. Digital baseband transmit circuitry provides the required spectral shaping.
3.2.2 Power Amplifier
The internal PA has a maximum output power of 6dBm. This allows BlueCore 5 chip to be used in Class 2 and
Class 3 radios without an external RF PA.
Support for transmit power control allows a simple implementation for Class 1 with an external RF PA.
3.3 RF Synthesizer
The radio synthesizer is fully integrated onto the die with no requirement for an external VCO screening can, varactor
tuning diodes, LC resonators or loop filter. The synthesizer is guaranteed to lock in sufficient time across the
guaranteed temperature range to meet the Bluetooth v2.1 + EDR specification.
3.4 Clock Input and Generation
The reference clock for the system is generated from a crystal input of 24MHz. All internal
reference clocks are generated using a phase locked loop, which is locked to the external reference frequency.
