Gibson MM516, User Manual

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MM516
User's Manual
12
Revision 1.4 7-8-2011
Hardware Description Manual
3.5 Baseband and Logic
3.5.1 Memory Management Unit
The MMU provides a number of dynamically allocated ring buffers that hold the data that is in transit between the
host and the air. The dynamic allocation of memory ensures efficient use of the available RAM and is performed by
a hardware MMU to minimize the overheads on the processor during data/voice transfers.
3.5.2 Burst Mode Controller
During radio transmission the BMC constructs a packet from header information previously loaded into memory mapped
registers by the software and payload data/voice taken from the appropriate ring buffer in the RAM. During
radio reception, the BMC stores the packet header in memory-mapped registers and the payload data in the
appropriate ring buffer in RAM. This architecture minimizes the intervention required by the processor during
transmission and reception.
3.5.3 Physical Layer Hardware Engine DSP
Dedicated logic is used to perform the following:

Forward error correction

Header error control

Cyclic redundancy check

Encryption

Data whitening

Access code correlation

Audio transcoding
The following voice data translations and operations are performed by firmware:

A-law/μ-law/linear voice data (from host)

A-law/μ-law/CVSD (over the air)

Voice interpolation for lost packets

Rate mismatch correction
The hardware supports all optional and mandatory features of Bluetooth v2.1 + EDR including AFH and eSCO.
3.5.4 System RAM
48KB of on-chip RAM is provided to support the RISC MCU and is shared between the ring buffers used to hold
voice/data for each active connection and the general purpose memory required by the Bluetooth stack.
3.5.5 External Memory Driver
The External Memory Driver interface can be used to connect to the external Flash memory and also to the optional
external RAM for memory intensive applications.
3.5.6
Kalimba DSP RAM
Additional on-chip RAM is provided to support the Kalimba DSP:

16K x 24-bit for data memory 1 (DM1)

12K x 24-bit for data memory 2 (DM2)

6K x 32-bit for program memory (PM)
DSP can also execute directly from external Flash, using a 64-instruction on-chip cache.
3.5.7 USB
This is a full-speed USB interface for communicating with other compatible digital devices. BlueCore 5 chip acts
as a USB peripheral, responding to requests from a master host controller such as a PC.