GE Mini COM Express 10, Hardware Reference Manual

Page: 67 / 82

6.9 I 2 C Controller Run-Time Registers
I
2
C controller run-time registers are listed in the following table. The address indicates the
offset from the port base addresses programmed in the configuration registers.
I 2 C Controller Run-Time Registers
Offset Name
Description
0x0
Prescale (low byte) Clock prescale – least-significant byte
0x1
Prescale (high byte) Clock prescale – most-significant byte
0x2 Control
Control register
0x3
Receive
Receive data (read)
Transmit
Transmit data (write)
0x4
Status
Status register (read)
Command
Command register (write)
0x5
Transmit (read back) Transmit data (read)
0x6
Command (read back) Command register (read)
0x7 Reserved Reserved
6.9.1 Clock Prescale
The I 2 C clock frequency is set by a 16-bit prescale value. The actual frequency is equal to
the FPGA core clock (33.33 MHz) divided by five times the prescale value (plus one).
For example, a prescale value of 0x42 yields an I
2 C clock frequency of 99.5 kHz, and a
prescale value of 0x10 yields an I
2
C clock frequency of 392.2 kHz.
I 2 C Clock Prescale (LSB) Register (Offset 0x0)
Bit Name Access Default
Description
7:0
PRESCALE[7:0]
R/W 0xFF
LSB of baud-rate
generator divisor
I 2 C Clock Prescale (MSB) Register (Offset 0x1)
Bit Name Access Default
Description
7:0
PRESCALE[15:8]
R/W 0xFF
MSB of baud-rate
generator divisor
FPGA Registers GFK-2896 Hardware Reference Manual 67
For public disclosure