GE Mini COM Express 10 Hardware Reference Manual Download Page 13

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G-Series SoC

CPU Core

L1 Cache

CPU Core

L1 Cache

CPU Core

L1 Cache

CPU Core

L1 Cache

L2 Cache

North Bridge

GPU

South Bridge

LVDS/eDP

DDI0

VGA

I210

PCIe

PCIe[0:3]

GbE0

DDR3 L

2 /4/8GB

ECC

2x SATA

8x USB

2x USB_SS

HDA

GPIO /SD

Flash

SMBus

LPC

FPGA

UART

I2C

WDog

UART

Supv

Ser0

Ser1

I2C

WDT

SPD

Debug

SPI

EeeP

SMBus

User

mCOM10-L1500 Functional Block Diagram

Introduction

GFK-2896 Hardware Reference Manual 13

For public disclosure

Summary of Contents for Mini COM Express 10

Page 1: ...GE Intelligent Platforms GFK 2896 Mini COM Express Type 10 Module mCOM10 L1500 Hardware Reference Manual For public disclosure...

Page 2: ...patents or pending patent applications covering subject matter in this document The furnishing of this document does not provide any license whatsoever to any of these patents GE provides the followi...

Page 3: ...able Unit GPIO General Purpose Input Output GPU Graphics Processing Unit HDMI High Definition Multimedia Interface I2C Inter Integrated Circuit IEEE Institute of Electrical and Electronic Engineers JT...

Page 4: ...Single Root I O Virtualization TAP Test Access Port TDP Thermal Design Power TPM Trusted Platform Module UART Universal Asynchronous Receiver Transmitter UDIMM Unbuffered DIMM UEFI Unified EFI UHCI Un...

Page 5: ...esult in personal injury or death Caution Indicates a procedure condition or statement that if not strictly observed could result in damage to or destruction of equipment Attention Indicates a procedu...

Page 6: ...vice RMA returns and other functions World wide headquarters of GE Intelligent Platforms Inc GE Intelligent Platforms Inc 2500 Austin Drive Charlottesville VA 22911 U S A Regional Areas WW world wide...

Page 7: ...rtup 22 3 4 1 UEFI Firmware Setup 22 4 System Architecture 23 4 1 G Series SoC Processor 23 4 1 1 Memory 24 4 1 2 Digital Display Interface 24 4 1 3 PCI Express 24 4 1 4 BIOS UEFI Firmware 25 4 1 5 Se...

Page 8: ...tion Registers 48 6 3 1 UART Control 48 6 3 2 UART Base Address 48 6 3 3 UART Interrupt Request 49 6 3 4 UART Mode 50 6 4 Supervision Configuration Registers 51 6 4 1 Supervision Control 51 6 4 2 Supe...

Page 9: ...rs 65 6 8 1 Reset Cause 65 6 8 2 Last Reset 66 6 9 I2C Controller Run Time Registers 67 6 9 1 Clock Prescale 67 6 9 2 Control 68 6 9 3 Transmit 68 6 9 4 Receive 68 6 9 5 Command 69 6 9 6 Status 70 6 9...

Page 10: ...Notes 10 GFK 2896 Mini COM Express Type 10 Module mCOM10 L1500 For public disclosure...

Page 11: ...ports eight USB 2 0 host interfaces two of which support USB 3 0 low voltage differential signaling LVDS flat panel or embedded DisplayPort plus a Digital Display Interface DDI LPC SPI SMBus I2C secur...

Page 12: ...lanes configurable as either 4 1 or 1 4 Eight MB SPI Flash for UEFI BIOS firmware Two SATA ports Eight USB 2 0 host interfaces two of which also support USB 3 0 SuperSpeed Two simultaneous display out...

Page 13: ...outh Bridge LVDS eDP DDI0 VGA I210 PCIe PCIe 0 3 GbE0 DDR3L 2 4 8GB ECC 2x SATA 8x USB 2x USB_SS HDA GPIO SD Flash SMBus LPC FPGA UART I2C WDog UART Supv Ser0 Ser1 I2C WDT SPD Debug SPI EeeP SMBus Use...

Page 14: ...Notes 14 GFK 2896 Mini COM Express Type 10 Module mCOM10 L1500 For public disclosure...

Page 15: ...g or removing modules without observing this precaution could result in damage to this and or other modules in your system Wear a properly functioning anti static strap and make sure you are fully gro...

Page 16: ...g the board or module or fitting the device into your system read the manual carefully Also adhere to the following guidelines Observe all precautions for electrostatic sensitive modules If the produc...

Page 17: ...ical to ensure proper operation and long term reliability When unpacking and handling the board be sure to hold the board as displayed in the following figure Board Handling Unpacking and Inspection G...

Page 18: ...Notes 18 GFK 2896 Mini COM Express Type 10 Module mCOM10 L1500 For public disclosure...

Page 19: ...e supply meets the voltage and total power requirements of the mCOM10 L1500 Warning Verify that the power supply is turned OFF while plugging or unplugging the board onto or from a carrier card respec...

Page 20: ...wer and external supplies have been turned off Verify that the jumpers on the carrier board are correctly configured for your application Mount the board on the carrier board very carefully Refer to t...

Page 21: ...stall the mCOM10 L1500 onto the carrier board 1 Carefully slide the mCOM10 L1500 board onto the connector on the carrier board 2 Fasten the mCOM10 L1500 to the board using four M2 5 screws Tighten the...

Page 22: ...store power 3 4 Initial Startup A few seconds after powerup the mCOM10 L1500 system UEFI Firmware banner displays on the screen If you do not see any error messages up to this point the board is runni...

Page 23: ...USB 3 0 SuperSpeed Two SATA 2 x 3 x controllers SD card reader 3 0 or SDIO controller LPC Bus interface High definition audio General purpose I O SPI bus controller Two SMBus controllers Clock generat...

Page 24: ...two simultaneous video outputs with multiple modes The G Series SoC integrates the new generation Radeon Sea Islands GPU which supports DirectX 11 1 There is no independent memory dedicated to the GPU...

Page 25: ...e supported A combined SATA activity indicator is also provided 4 1 6 USB The mCOM10 L1500 provides eight G Series SoC USB controllers to host serial links through the COM Express connector All ports...

Page 26: ...tor starting 4 1 10 Real Time Clock and CMOS RAM The RTC oscillator uses a 32 768 kHz crystal The G Series SoC provides the real time clock RTC and CMOS RAM functions This is powered from the VCC_RTC...

Page 27: ...ectly to the COM Express connector Isolation should be implemented on the carrier board Three status LED outputs from the I210 are decoded in the FPGA to produce four Ethernet link and activity indica...

Page 28: ...us or unintentional changes Once locked it remains locked until reset 4 3 2 I2C Bus The on board I2C bus is also connected to the G Series SoC Sideband Temperature Sensor Interface SB TSI which provid...

Page 29: ...ion For battery less systems the carrier board must hold off standby and primary power to meet the five second requirement when the system powers up Once VCC_5V_SBY or VCC_12V is applied the on board...

Page 30: ...litates programming of the FPGA For processor debug APU_Sel alone is asserted and the G Series SoC will be the only device in the chain APU_Sel Board_Sel G Series SoC I210 FPGA JTAG Connector JTAG Cha...

Page 31: ...ress plug on the carrier board mCOM10 L1500 Connector Pin Assignments Pin Signal Pin Signal A1 GND B1 GND A2 GBE0_MDI3 B2 GBE0_ACT A3 GBE0_MDI3 B3 LPC_FRAME A4 GBE0_LINK100 B4 LPC_AD0 A5 GBE0_LINK1000...

Page 32: ...GND B51 GND A52 RSVD B52 RSVD A53 RSVD B53 RSVD A54 GPI0 B54 GPO1 A55 RSVD B55 RSVD A56 RSVD B56 RSVD A57 GND B57 GPO2 A58 PCIE_TX3 B58 PCIE_RX3 A59 PCIE_TX3 B59 PCIE_RX3 A60 GND B60 GND A61 PCIE_TX2...

Page 33: ...92 SPI_MISO B92 DDI0_PAIR5 A93 GPO0 B93 DDI0_PAIR6 A94 SPI_CLK B94 DDI0_PAIR6 A95 SPI_MOSI B95 DDI0_DDC_AUX_SEL A96 TPM_PP B96 USB_HOST_PRSNT A97 TYPE10 B97 SPI_CS A98 SER0_TX B98 DDI0_CTRLCLK_AUX A99...

Page 34: ...3 3 V 3 3 V 1000 Mbps 1 Gbps link indicator GBE0_CTREF REF N A Ethernet magnetics center tap reference Floating SATA Signal Pin Type Voltage Supply Description SATA0_TX O SATA AC coupled on module Cha...

Page 35: ...RX 0 1 I O AC coupled on carrier board Additional receive differential pairs for SuperSpeed USB data USB_HOST_ PRSNT N A N A USB host present on the carrier indicator Not used LVDS eDP Signal Pin Type...

Page 36: ...ta from module to carrier SPI_CLK O CMOS 3 3 V 3 3 V Bus clock SPI_POWER O CMOS 3 3 V suspend 3 3 V Power supply for carrier board SPI Connected to 3 3 V standby supply BIOS_DIS 0 1 I CMOS 3 3 V 3 3 V...

Page 37: ...m module physical presence Not connected Power and System Management Signal Pin Type Voltage Supply Description PWRBTN I CMOS 3 3 V Suspend 3 3 V Power button SYS_RESET I CMOS 3 3 V Suspend 3 3 V Syst...

Page 38: ...al purpose input 2 or SDIO data 2 GPI3 O CMOS 3 3 V 3 3 V General purpose input 3 or SDIO data 3 GPO0 O CMOS 3 3 V 3 3 V General purpose output 0 or SDIO clock GPO1 O CMOS 3 3 V 3 3 V General purpose...

Page 39: ...d are routed to a connector for use with an external cable Carrier board USB overcurrent monitors may pull the USB_ 0 2 4 6 _ 1 3 5 7 _OC l lines to GND with open drain drivers to indicate that the mo...

Page 40: ...DBRDY 9 GND 10 TDI 11 DBG_RESET 12 TMS 13 GND 14 1 8V_STBY 15 GND 16 1 8V_STBY 17 DBG_PWRBTN 18 TDO 19 GND 20 TRST 21 APU_RST 22 TCK 23 GND TCK TMS TDI TDO and TRST are the standard IEEE 1149 1 JTAG s...

Page 41: ...1500 is 0x0C15 The Subsystem Vendor ID is 0x1775 PCIe Port Assignments Lane Device Connector Width Speed GPP0 mCOMe PCIE0 1 Gen1 2 GPP1 mCOMe PCIE1 1 Gen1 2 GPP2 mCOMe PCIE2 1 Gen1 2 GPP3 mCOMe PCIE3...

Page 42: ...ard SMBus Devices Bus Device Function Address 0 CAT34TS02 SPD EEPROM 1010_000x Temperature Sensor 0011_000x 1 I210 Ethernet Controller Unused 5 2 3 I2C Slave Devices The FPGA hosts an I2C bus controll...

Page 43: ...ENT13_L USB_OC_2_3 In GEVENT14_L USB_OC_4_5 In GEVENT15_L USB_OC_6_7 In GEVENT16_L Unused GEVENT17_L SLEEP In GEVENT18_L BLINK Out GEVENT19_L SYS_RESET In GEVENT20_L Unused GEVENT21_L Unused GEVENT22_...

Page 44: ...IO78 SD_DATA1 Bi GPIO79 SD_DATA2 Bi GPIO80 SD_DATA3 Bi GPIO161 SPI_WP Out GPIO162 SPI_CLK Out GPIO163 SPI_MOSI Out GPIO164 SPI_MISO In GPIO165 SPI_CS1 Out GPIO166 SPI_CS2 Out GPIO167 HDA_SDIN0 Bi GPIO...

Page 45: ...t address The lock and unlock codes do not match any internal index addresses Configuration Access Port Address Name Description 0x002E Index Configuration register index pointer 0x002F Data Configura...

Page 46: ...mware version major release number 0x23 Revision Firmware revision minor release number 0x24 Build Info High High byte of the FPGA Build Information 0x25 Build Info Low Low byte of the FPGA Build Info...

Page 47: ...ision minor release number 6 2 5 Build Information The Build Information is constantly incrementing a 16 bit value that changes each time the FPGA firmware is built using the make command FPGA Build I...

Page 48: ...device to be activated or deactivated UART Control Registers Bit Name Access Default Description 7 01 R 0b0000000 Reserved 0 00 ACTIVATE R W 0 Logical device activation 0 Disabled 1 Enabled 6 3 2 UART...

Page 49: ...Access Default Description 7 04 R 0b0000 Reserved 3 0 IRQ R W 0b0000 Interrupt request line assignment 0b0000 None 0b0001 IRQ1 0b0010 IRQ2 0b0011 IRQ3 0b0100 IRQ4 0b0101 IRQ5 0b0110 IRQ6 0b0111 IRQ7 0...

Page 50: ...tion 6 R W 0 Reserved 5 TEST_FE R W 0 Framing error test mode When set to 1 the transmitted stop bit is truncated to bit time This bit must be cleared to 0 for normal operation 4 TEST_PE R W 0 Parity...

Page 51: ...deactivated Supervision Control Register LDN 0x0A Index 0x30 Bit Name Access Default Description 7 01 R 0b0000000 Reserved 0 ACTIVATE R W 0 Logical device activation 0 Disabled 1 Enabled 6 4 2 Supervi...

Page 52: ...ated or deactivated I2C Control Register LDN 0x0C Index 0x30 Bit Name Access Default Description 7 01 R 0b0000000 Reserved 0 ACTIVATE R W 0 Logical device activation 0 Disabled 1 Enabled 6 5 2 I2C Bas...

Page 53: ...scription 7 04 R 0b0000 Reserved 3 IRQ R W 0b0000 Interrupt request line assignment 0b0000 None 0b0001 IRQ1 0b0010 IRQ2 0b0011 IRQ3 0b0100 IRQ4 0b0101 IRQ5 0b0110 IRQ6 0b0111 IRQ7 0b1000 IRQ8 0b1001 I...

Page 54: ...cal device to be activated or deactivated Watchdog Timer Control Register LDN 0x14 Index 0x30 Bit Name Access Default Description 7 01 R 0b0000000 Reserved 0 ACTIVATE R W 0 Logical device activation 0...

Page 55: ...10 IRQ2 0b0011 IRQ3 0b0100 IRQ4 0b0101 IRQ5 0b0110 IRQ6 0b0111 IRQ7 0b1000 IRQ8 0b1001 IRQ9 0b1010 IRQ10 0b1011 IRQ11 0b1100 IRQ12 0b1101 IRQ13 0b1110 IRQ14 0b1111 IRQ15 6 6 4 Watchdog Timer Options T...

Page 56: ...ant byte of baud rate divisor 0x1 1 Divisor Latch MSB Most significant byte of baud rate divisor 6 7 1 Receive Buffer This register holds the incoming received data after it has been transferred from...

Page 57: ...cription 7 TX_XFR R W 0 Transmit DMA transfer enable Automatically cleared when the transfer is complete as indicated by the terminal count 6 RX_XFR R W 0 Receive DMA transfer enable Automatically cle...

Page 58: ...it Data register A modem status interrupt is cleared by reading the Modem Status register Receive and transmit DMA interrupts are cleared by reading the Interrupt Identification Register when they are...

Page 59: ...11 56 bytes 256 byte FIFO 0b00 1 byte 0b01 32 bytes 0b10 64 bytes 0b11 128 bytes 5 04 TX_TRIG W 0b00 Transmit FIFO trigger level 16 byte FIFO 0bXX 1 byte 64 byte FIFO 0b00 1 byte 0b01 16 bytes 0b10 56...

Page 60: ...d 1 Parity is transmitted and checked as a 0 for odd parity and as a 1 for even parity 4 EVEN_PAR R W 0 Even parity select 0 Odd number of 1s in data parity 1 Even number of 1s in data parity 3 PAR_EN...

Page 61: ...to the receive shift register DTR is connected to DSR RTS is connected to CTS OUT1 is connected to RI and OUT2 is connected to DCD 3 0 OUT2 R W 0 Output 2 In Loop back mode connected to Data Carrier...

Page 62: ...t data parity stop bit time In FIFO mode this applies to the character at the top of the FIFO Generates a Receiver Line Status interrupt Cleared when read 3 FE R 0 Framing error Set to 1 when the rece...

Page 63: ...external DSR input Equals DTR in loopback mode 4 CTS R 0 Complement of external CTS input Equals RTS in loopback mode 3 DDCD R 0 Delta data carrier detect Indicates that the DCD line has changed stat...

Page 64: ...he 33 33 MHz reference clock down to the serial data rate The divisor is a 16 bit value contained in two byte wide registers one for the MSB and one for the LSB For asynchronous mode the clock is set...

Page 65: ...ffected Typically this register should be read early in the boot process Note This register cannot detect software controlled hard or soft resets issued by the SoC Reset Cause Register Offset 0x0 Bit...

Page 66: ...tchdog timeout caused the last board reset Cleared by writing a 1 to the bit 5 R 0 Reserved 4 DB_RST R C 0 When set indicates that a debug port reset caused the last board reset Cleared by writing a 1...

Page 67: ...ta read 0x6 Command read back Command register read 0x7 Reserved Reserved 6 9 1 Clock Prescale The I2C clock frequency is set by a 16 bit prescale value The actual frequency is equal to the FPGA core...

Page 68: ...ransmit The I2C Transmit register is used to write the data and address control bytes to be sent on the I2C bus It can be written at address offset 0x3 and read back at offset 0x5 I2C Transmit Registe...

Page 69: ...t bit 6 STO R W 0 Stop Automatically cleared Always read as zero 0 No action 1 Generate a Stop bit 5 RD R W 0 Read Automatically cleared Always read as zero 0 No action 1 Read from slave 4 WR R W 0 Wr...

Page 70: ...ved acknowledge flag from the slave 0 ACK 1 NACK 6 BUSY R 0 SMBus busy 0 Stop detected 1 Start detected 5 AL R 0 Arbitration lost 0 Normal operation 1 Arbitration lost 4 02 R 0b000 Reserved 1 TIP R 0...

Page 71: ...0x8 Control Timer control register 0x9 Reserved 0xA Reload Timer reload register 0xB Reserved 0xC Status Timer status register 0xD Reserved 0xE Interrupt Enable Interrupt Enable Register 0xF Reserved...

Page 72: ...The reset indication is a sticky bit that is not cleared on a system reset although it is cleared on powerup Watchdog Timer Status Register Offset 0xC Bit Name Access Default Description 7 02 R 0b0000...

Page 73: ...on Level A F Conduction Level D Vibration Random 0 1g2 Hz from 15 to 2000 Hz Shock 40g pk saw tooth 11 ms duration Humidity 10 to 90 RH non condensing Altitude Up to 4 572 m 15 000 ft above sea level...

Page 74: ...Notes 74 GFK 2896 Mini COM Express Type 10 Module mCOM10 L1500 For public disclosure...

Page 75: ...is represented by a low electrical signal JTAG Typically used to refer to JTAG boundary scan LPC Bus A low speed interface used for peripheral circuits such as Super I O controllers which typically c...

Page 76: ...ial EEPROM associated with a bank of memory that contains the characteristics and operating parameters of the memory SPI A four wire clock data in data out and chip select bus typically used for low s...

Page 77: ...isters 46 I2C Address 52 I2C Control 52 I2C Controller Configuration Registers 52 I2C Controller Run Time Registers 67 I2C IRQ 53 Index Port 45 Interrupt Enable 57 Interrupt Identification 58 Last Res...

Page 78: ...dem Control 61 Modem Status 63 N Non Volatile Memory 28 P Package Contents 16 PCI Express PCIe 24 PCIe Ports 41 Pin Assignments JTAG 40 Module 31 PCIe Ports 41 Power Distribution 29 Power Reset Sequen...

Page 79: ...nsmit 68 Transmit Buffer 56 U UART Base Address 48 UART Configuration Registers 48 UART Control 48 UART IRQ 49 UART Mode 50 UART Run Time Registers 56 UEFI Firmware Setup 22 Unpacking and Inspecting D...

Page 80: ...Notes 80 Mini COM Express Type 10 Module mCOM10 L1500 For public disclosure...

Page 81: ......

Page 82: ...GE Intelligent Platforms 1 800 433 2682 1 434 978 5100 www ge ip com GFK 2896 For public disclosure...

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