6.7.3
Interrupt Enable
This register provides the means to enable or mask individual causes from generating an
external UART interrupt. When set to 0, the interrupt cause is masked. When set to 1, the
interrupt cause is enabled. Access to the DMA interrupt and transfer enable bits is
allowed only when DMA is enabled in the UART mode configuration register. Otherwise,
these bits are read-only and forced to zero.
UART Interrupt Enable Register (Offset 0x1)
Bit
Name
Access
Default
Description
7
TX_XFR
R/W
0
Transmit DMA transfer enable.
Automatically cleared when the
transfer is complete (as indicated
by the terminal count).
6
RX_XFR
R/W
0
Receive DMA transfer enable.
Automatically cleared when the
transfer is complete (as indicated
by the terminal count).
5
TX_DMA
R/W
0
Transmit DMA transfer complete
interrupt enable
4
RX_DMA
R/W
0
Receive DMA transfer complete
interrupt enable
3
MODEM
R/W
0
Modem status interrupt enable
2
LINE
R/W
0
Received line status interrupt
enable
1
TX
R/W
0
Transmit holding register empty
interrupt enable
0
RX
R/W
0
Received data available interrupt
enable
FPGA Registers
GFK-2896 Hardware Reference Manual 57
For public disclosure
Summary of Contents for Mini COM Express 10
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