GE Mini COM Express 10, Hardware Reference Manual

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6.9.7 Watchdog Timer Run-Time Registers
The Watchdog timer run-time registers are listed in the following table. The address
indicates the offset from the port base addresses programmed in the configuration
registers. The Watchdog timer is capable of timing intervals ranging from 8 μsec to over
128 seconds. It is clocked with a 33.33 MHz reference clock and a 125 kHz clock enable.
Upon being enabled or serviced, the Watchdog timer is loaded with the interrupt count
value, and then counts down by one every 8 μsec. If the counter reaches 0, it generates an
interrupt and automatically loads the reset count value. If the counter reaches 0 again, the
WDT signal is asserted, and if enabled, a non-maskable interrupt or a system reset is
issued.
Watchdog Timer Run-Time Registers
Offset Name
Description
0x0 Int Count Low
Interrupt count lower byte
0x1 Int Count Mid
Interrupt count middle byte
0x2
Int Count High Interrupt count upper byte
0x3
—
Reserved
0x4 Reset Count Low
Reset count lower byte
0x5 Reset Count Mid
Reset count middle byte
0x6
Reset Count High Reset count high byte
0x7 — Reserved
0x8 Control
Timer control register
0x9
—
Reserved
0xA Reload
Timer reload register
0xB
—
Reserved
0xC Status
Timer status register
0xD
—
Reserved
0xE
Interrupt Enable Interrupt Enable Register
0xF — Reserved
The interrupt and reset count register contents can be changed while the Watchdog timer
is unlocked, but the new values will not take effect until the Watchdog is serviced. The
actual timeout intervals are equal to the value in the count register plus 1, times 8 μsec.
Watchdog Interrupt Count Register (Offset 0x0-0x3)
Bit Name Access Default
Description
31:24
—
R 0x00 Reserved
23:0
INT_CNT[23:0]
R/W 0xFFFFFF
Watchdog interrupt count
value
Watchdog Reset Count Register (Offset 0x4-0x7)
Bit Name Access Default
Description
31:24
—
R 0x00 Reserved
23:0
RST_CNT[23:0]
R/W 0xFFFFFF
Watchdog reset count
value
Write access to any of the Watchdog timer registers must be preceded by a two-byte
sequence (0x17, 0x75) written to the control register address. After reset, the Watchdog is
disabled and unlocked. It may be freely enabled and disabled while it is unlocked. It may
also be freely locked and unlocked while it is disabled. If the Watchdog timer is locked
while it is enabled, it will remain in that state until it is reset.
FPGA Registers GFK-2896 Hardware Reference Manual 71
For public disclosure