Pub. 42004-392G
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e:\standard ioms - current release\42004 instr. manuals\42004-392g.doc
09/14
Table 43. DIP Switch SW2 on Main PCBA
Switch Setting
Function
SW2-1
T1 line length
SW2-2
SW2-3
SW2-4
T1/E1 receive equalizer gain limit
SW2-5
Page line transmission direction hold time
SW2-6
SW2-7
Page line peak voltage level detection threshold
SW2-8
Open (Up)
Used during testing only.
Table 44. DIP Switch SW3 on Main PCBA
Switch Setting
Function
SW3-1
T1/E1 master/slave
SW3-2
SW3-3
Enable
LVDS
“in”
SW3-4
Enable
LVDS
“out”
SW3-5
Monitor volume
SW3-6
SW3-7
SW3-8
Table 45. DIP Switch SW4 on Main PCBA
Switch
Setting
Note
SW4-1
Party line #5 connection to terminal board
SW4-2
Party line #4 connection to terminal board
SW4-3
Party line #3 connection to terminal board
SW4-4
Party line #2 connection to terminal board
SW4-5
Party line #1 connection to terminal board
SW4-6
Page line connection to terminal board
SW4-7
Monitor output connection to terminal block
SW4-8
N/A
Not
used